On-chip Balun Research Articles

Characterization of on-chip balun with patterned floating shield in 65 nm CMOS

A simple method of balun synthesis is proposed to estimate the balun structure in the operating frequency band. Then, a careful optimization is implemented to evaluate the estimated structure by a series of EM simulations. In order to investigate the impact of the patterned floating shield (PFS), the optimized baluns with and without PFS are fabricated in a 65 nm 1P6M CMOS process. The measurement results demonstrate that the PFS obviously improves the insertion loss (IL) in the frequency range and a linear improving trend appears smoothly. It is also found that the PFS gradually improves the phase balance as the frequency increases, while it has a very slight influence on the magnitude balance. To characterize the device's intrinsic power transfer ability, we propose a method to obtain the baluns' maximum available gain directly from the measured 3-port S-parameters and find that IL-comparison may not be very objective when evaluating the shielding effect. We also use the resistive coupling efficiency to characterize the shielding effect, and an imbalanced shielding efficiency is found though the PFS is perfectly symmetric in the measurement. It can be demonstrated that this phenomenon comes from the intrinsic imbalance of our balun layout.

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

A 2.4 GHz low-power, low-noise and highly linear receiver front-end with a low noise amplifier (LNA) and balun optimization is presented. Direct conversion architecture is employed for this front-end. The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer, and is optimized for the best noise performance of the front-end. The circuit is implemented with 0.35 μm SiGe BiCMOS technology. The front-end has three gain steps for maximization of the input dynamic range. The overall maximum gain is about 36 dB. The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode. The down-conversion mixer has a tunable parallel R—C load at the output and an emitter follower is used as the output stage for testing purposes. The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm2 die size.

An 80 GHz High Gain Double-Balanced Active Up-Conversion Mixer Using 0.18 $\mu{\rm m}$ SiGe BiCMOS Technology

This letter reports the performance of a W-band (75-110 GHz) high gain double-balanced active up-conversion mixer fabricated in a low-cost 200 GHz f T and f max 0.18 μm SiGe BiCMOS technology. Integrated on-chip baluns are used at RF and LO ports to facilitate on-wafer characterization. The mixer achieves a measured single sideband (SSB) power conversion gain of 6.6 dB and 3.2 dB at 75 GHz and 80 GHz, respectively. The measured output-referred 1 dB compression point (OP1dB) is -4.8 dBm and -7.3 dBm at 75 GHz and 80 GHz, respectively. The overall chip area is 830 μm×690 μm. The mixer draws a total of 31.5 mA from a nominal 3.3 V supply. To the best of authors' knowledge, this is the W-band active up-conversion mixer with the highest conversion gain reported among all prior published millimeter-wave silicon-based up-conversion mixers.

A 26 GHz Transceiver Chipset for Short Range Radar Using Post-Passivation Interconnection

We demonstrate a 26 GHz SiGe bipolar complementary metal oxide semiconductor (BiCMOS) transceiver chipset for short-range spread-spectrum (SS) radar system. The integrated frequency triplers lower the local oscillation frequency down to 8.8 GHz, and eliminate the carrier leak in the transmitting signal which enables high sensitivity. The on-chip balun connected to the mixer demodulating by the pseudo noise (PN) code in the receiver increases the dynamic range of the receiving signal. Low-loss transmission lines on Si substrate are fabricated by post-passivation interconnection process using thick benzocyclobutene (BCB). We have confirmed the transmitting signal having spread-spectrum with suppressing the carrier leak, the improvement of the dynamic range of the receiver, and the reduction of the transmission loss on Si substrate. We have demonstrated the operation of the 26 GHz ultra wide band (UWB) SS radar, corresponding to detecting a human located at 7 m away from the system.

A 160-GHz low-noise downconversion receiver front-end in a SiGe HBT technology

A 160-GHz SiGe-HBT (Heterojunction Bipolar Transistor) down-conversion receiver front-end for use in active millimeter-wave imaging arrays and D-band communication applications is presented. The monolithic front-end consists of a three-stage low-noise amplifier providing 24 dB of gain and a Gilbert-cell mixer capable of operating from a −8-dBm LO signal. A fully differential architecture compatible with balanced on or off-chip antennas is used to avoid the need for on-chip baluns in antenna-integrated applications. The implemented downconversion front-end consumes 50 mA from a 3.3 V supply and requires a 0.1 mm2 die area (excl. pads) per channel. With a 160-GHz input signal and an Intermediate Frequency (IF) of 1 GHz, the implemented front-end yields a 25-dB conversion gain, a −30-dBm input compression point, and a 9-dB/7-dB (with/without auxiliary on-chip input balun) system noise figure.

Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2$\, \times \,$2 802.11n MIMO WLAN SoC

Fully integrated dual-band power amplifiers with on-chip baluns for 802.11n MIMO WLAN applications are presented. With a 3.3 V supply, the PAs produce a saturated output power of 28.3 dBm and 26.7 dBm with peak drain efficiency of 35.3% and 25.3% for the 2.4 GHz and 5 GHz bands, respectively. By utilizing multiple fully self-contained linearization algorithms, an EVM of -25 dB is achieved at 22.4 dBm for the 2.4 GHz band and 20.5 dBm for the 5 GHz band while transmitting 54 Mbs OFDM. The chip is fabricated in standard 65 nm CMOS and the PAs occupy 0.31 mm2 (2.4 GHz) and 0.27 mm2 (5 GHz) area. To examine the reliability of the PAs, accelerated aging tests are performed for several hundreds parts without a single failure.

A W-Band Highly Linear SiGe BiCMOS Double-Balanced Active Up-Conversion Mixer Using Multi-Tanh Triplet Technique

This letter presents a W-band highly linear double- balanced active up-conversion mixer implemented in a low-cost 200 GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> 0.18 ¿m SiGe BiCMOS process. Linearization technique based on multi-tanh triplet principle is used to improve the linearity of the transconductanace stage. An integrated active frequency doubler and on-chip balun are used at LO port and RF port, respectively to facilitate on-wafer testing. The technical aspects of the mixer characterization are addressed. The up-conversion mixer achieves a single sideband (SSB) power conversion gain of 5.1 dB at 77 GHz and 3.8 dB at 80 GHz. The output-referred 1 dB compression point (OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> ) is -4.2 dBm and -5.8 dBm at 77 and 80 GHz, respectively. The active mixer, including the output buffers, draws 32.5 mA from a nominal 3.3 V supply. The chip area of the mixer is 820 ¿m × 810 ¿m (0.664 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). To the best of authors' knowledge, this is the first W-band active up-conversion mixer utilizing multi-tanh triplet technique that has demonstrated the highest measured and characterized operating frequency among all other silicon-based up-conversion mixers reported to date.

A Biphase Modulator Circuit for Impulse Radio-UWB Applications

This letter presents a circuit to provide binary phase shift keying to ultra-wideband (UWB) impulse transmitters. The circuit is based on a Gilbert-cell multiplier and uses active on-chip balun and unbalanced-to-balanced converters for single-ended to single-ended operation. Detailed measurements of the circuit show a gain ripple of ±1 dB at an overall gain of -2 dB, an input reflection below -12 dB, an output reflection below -18 dB, a group delay variation below 6 ps and a -1 dB input compression point of more than 1 dBm in both switching states over the full 3.1-10.6 GHz UWB frequency range. A time domain measurement verifies the switching operation using an FCC-compliant impulse generator. The circuit is fabricated in a 0.8 ?m Si/SiGe HBT technology, consumes 31.4 mA at a 3.2 V supply and has a size of 510 × 490 ?m2, including pads. It can be used in UWB systems using pulse correlation reception or spectral spreading.

A 60-GHz Phased Array Receiver Front-End in 0.13-$\mu {\hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.

W-band double-balanced down-conversion mixer with Marchand baluns in silicon-germanium technology

Presented is a monolithic W-band (75–110 GHz) down-conversion mixer consisting of a double-balanced core, Marchand-type on-chip baluns at inputs, and a two-stage output buffer, fabricated in a 200 GHz fT SiGe technology. Including the loss for input baluns, this mixer exhibits conversion gains of 14.4±2.8 dB and single sideband (SSB) noise figures of less than 19.5 dB across the entire W-band, drawing 28 mA from a 3.3 V supply.

50 GHz S-shaped rat-race balun with 1.4 dB insertion loss in a wafer-level chip-size package process

In millimeter-wave CMOS circuits, a balun is useful for connecting off-chip single-end devices and on-chip differential circuits to improve noise immunity. However, an on-chip balun occupies a large chip area. To reduce the chip area required for the on-chip balun, a new rat-race balun using a rewiring technology with a wafer-level chip-size package (W-CSP) is proposed. The W-CSP balun occupies no area in a die because it is placed over integrated circuits. In the proposed balun, an S-shaped structure is adopted in order to directly connect the balun to differential GSGSG pads on a chip with a small area. The S-shaped W-CSP balun was fabricated on a silicon-on-insulator (SOI) substrate. The core area of the S-shaped rat-race balun is 480×735 µm, which is 22.4% that of a square rat-race balun. As a result of measurement, we found that the minimum insertion loss is 1.4 dB and the operating frequency ranges from 40 to 61 GHz.

W-Band Active Down-Conversion Mixer in Bulk CMOS

A W-band (76-77 GHz) active down-conversion mixer has been demonstrated using low leakage (higher V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) NMOS transistors of a 65-nm digital CMOS process with 6 metal levels. It achieves conversion gain of -8 dB at 76 GHz with a local oscillation power of 4 dBm ( ~ -2 dBm after de-embedding the on-chip balun loss), and 3 dB bandwidth of 3 GHz. The SSB noise figures are 17.8-20 dB (11.3-13.5 dB after de-embedding on-chip input balun loss) between 76 and 77 GHz. IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> is -6.5 dBm and IIP3 is 2.5 dBm ( ~ -13 and ~ -4 dBm after de-embedding the on-chip balun loss). The mixer consumes 5 mA from a 1.2 V supply.

A Fully Differential 77-GHz Active IQ Modulator in a Silicon-Germanium Technology

A 77-GHz IQ modulator in a fully differential circuit configuration is presented. It includes an local oscillation (LO) buffer amplifier, a medium-power output stage, a double-balanced active mixer architecture and on-chip baluns for easy characterization. A differential branch-line coupler provides quadrature phase signals at the upconversion mixer LO inputs. The circuit is manufactured in a 200-GHz transit frequency technology, and the circuit performance is shown by on-wafer measurements.

5.8-GHz merged LNA-mixer with on-chip balun

In this paper, the design and application of an on-chip transformer balun for RFIC is presented. Single-ended primary and differential secondary are constructed without using three individual windings for simple layout. Besides, this new topology has the same physical common visual ground point for second winding, which eliminates imbalance due to the potential difference at the ground from a conventional trifilar. Furthermore, this new on-chip balun is successfully applied to the integration of a 5.8-GHz low-noise amplifier (LNA) mixer implemented on SiGe 0.35-μm BiCMOS process then achieves 4.15-dB noise figure (NF), 34.61-dB conversion gain, and a −9.5-dBm input 3rd-order intercept-point with low power consumption of 9 mW. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 508–511, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21394

An UTRA/FDD Direct-Downconversion Mixer in 0.25 μm CMOS

In this paper the design of a 2 GHz direct-downconversion mixer for a UTRA/FDD receiver is presented. The mixer is implemented using a standard low-cost 0.25 μm, single-poly, six-metal CMOS process. An on-chip passive balun is used to generate a balanced RF input signal. In-house optimized device models are used for both active and passive components to achieve a voltage conversion gain of 12.8 dB, an iIP2 of 25 dBm, an iIP3 of −3.1 dBm, and a noise figure of 8 dB. The circuit provides I and Q signal path outputs while drawing 6 mA from a 2.5 V supply.