Off-state Current Research Articles

Off-State Performance Characterization of an AlGaN/GaN Device via Artificial Neural Networks.

Due to the complexity of the 2D coupling effects in AlGaN/GaN HEMTs, the characterization of a device’s off-state performance remains the main obstacle to exploring the device’s breakdown characteristics. To predict the off-state performance of AlGaN/GaN HEMTs with efficiency and veracity, an artificial neural network-based methodology is proposed in this paper. Given the structure parameters, the off-state current–voltage (I–V) curve can therefore be obtained along with the essential performance index, such as breakdown voltage (BV) and saturation leakage current, without any physics domain requirement. The trained neural network is verified by the good agreement between predictions and simulated data. The proposed tool can achieve a low average error of the off-state I–V curve prediction (Ave. Error < 5%) and consumes less than 0.001‰ of average computing time than in TCAD simulation. Meanwhile, the convergence issue of TCAD simulation is avoided using the proposed method.

Influence of ambient condition on off-state current of polymer-blend transistors based on 6,13-bis(triisopropylsilylethynyl) pentacene with deposition of molybdenum trioxide

We have fabricated blend films comprising 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) as a semiconducting small molecule and poly(methyl methacrylate) (PMMA) as an insulating polymer by electrostatic spray deposition (ESD). A thin film (5 nm) of molybdenum trioxide (MoO3) was evaporated on the entirety of the active layer surface. Then, we found that the off-state current in OFETs using the TIPS pentacene/PMMA blend films apparently increased. This result probably indicates the formation of a conductive surface channel due to the MoO3 deposition. In this study, we performed morphological and chemical analyzes. In consequence, we found that only Mo atoms (not together with O atoms) penetrated into TIPS pentacene and oxidation of Mo to MoO x could enhance charge transfer between neighboring TIPS pentacene molecules. Furthermore, this study demonstrated that the off-state current could be modulated by changing the ambient condition, such as relative humidity.

Silicon and Germanium Vertical Super-Thin Body (VSTB) FET: A Comparative Performance Overview Including Architectural Stress-Strain Impact

This article aims to develop a comprehensive understanding of the comparative performance of a vertical super-thin body (VSTB) FET in terms of two device material variations (silicon/Si and germanium/Ge) first time with the aid of 3D Senaturus TCAD tool. More importantly, the influence of the inevitable architectural stress (exerted over the thin body by the thick dielectric walls) on the transfer characteristic of the device is also addressed for Si/Ge device. From the perspective of suitability in high-performance circuits, Ge outperforms Si by enhancing on-state current (I on ) by 30.28, 30.29, 29.91, and 26.98 μA at channel length of 10, 20, 30, and 40 nm, respectively, with an improvable deterioration in off-state leakage current, subthreshold swing, and drain-induced-barrier-lowering. Further, a three-dimensional stress analysis reveals that stress increases I on more in Ge-device compared to its Si-counterpart. As expected, a similar nature is observed for the strain application. Finally, the radio-frequency study shows that although the relative performance of Ge with respect to Si in terms of input capacitance, gate-drain capacitance, and output conductance is inferior, the greater transconductance of Ge than Si lowers intrinsic delay and enhances the peaks of intrinsic gain, unit-gain cut-off frequency, and gain-bandwidth-product.

Interfacial charge analysis and temperature sensitivity of germanium source vertical tunnel FET with delta-doped layer

The influence of interface trap charges (ITCs) and reliability of the Germanium source vertical tunnel field effect transistor with delta-doped layer (GSDD vTFET) is investigated in this paper. The analysis is carried out on the GSDD vTFET by evaluating the analog/RF performances under the consideration of donor and acceptor ITCs and temperature variations. The presence of interface trap charges at the silicon channel/gate oxide interface changes the flat-band voltage, affecting the analog and RF performances of the GSDD vTFET. The study is carried out at distinctive donor and acceptor interface trap charges. The findings indicate that as the interface trap charge densities increases, the device's output changes drastically. The off-state current of the GSDD vTFET deteriorates significantly from an order of 10−14 A to 10−8 A in the presence of positive ITC of 1012/cm2. The temperature variations over a wide range shows that OFF-state current as well as subthreshold region gets deteriorated due to dominance of Shockley–Read–Hall effect and the superthreshold region is less affected owing to dependence of band-to-band tunneling. The results reveal that when the temperature is raised from 200 K to 400 K, the ION/IOFF current ratio degrades tremendously from ~1014 to ~108 in the existence of donor ITC. It is also observed that the GSDD vTFET is less susceptible to acceptor interface trap charge in comparison with donor ITC in a temperature sensitive environment. Quantum correction (QC) of GSDD vTFET with ITC shows the same type of variations as the condition without considering QC.

Diffusion interface layer controlling the acceptor phase of bilayer near-infrared polymer phototransistors with ultrahigh photosensitivity

The narrow bandgap of near-infrared (NIR) polymers is a major barrier to improving the performance of NIR phototransistors. The existing technique for overcoming this barrier is to construct a bilayer device (channel layer/bulk heterojunction (BHJ) layer). However, acceptor phases of the BHJ dissolve into the channel layer and are randomly distributed by the spin-coating method, resulting in turn-on voltages (Vo) and off-state dark currents remaining at a high level. In this work, a diffusion interface layer is formed between the channel layer and BHJ layer after treating the film transfer method (FTM)-based NIR phototransistors with solvent vapor annealing (SVA). The newly formed diffusion interface layer makes it possible to control the acceptor phase distribution. The performance of the FTM-based device improves after SVA. Vo decreases from 26 V to zero, and the dark currents decrease by one order of magnitude. The photosensitivity (Iph/Idark) increases from 22 to 1.7 × 107.

Effect of GaN cap layer on the performance of AlInN/GaN-based HEMTs

The effect of the GaN cap layer on the performance of AlInN/GaN-based HEMTs has been studied. Detailed analysis of the DC characteristics reveals that the addition of the GaN cap layer reduces the gate leakage current and increases the saturation drain current of HEMT. We have observed a slight increase in the two-dimensional electron gas density on the addition of the GaN cap layer. The addition of the GaN cap layer shifts the threshold voltage towards the negative direction, reduces the off-state drain leakage current, improves subthreshold swing, and enhances the ION/IOFF ratio of HEMT. The TCAD simulation shows that the addition of the GaN cap layer reduces the peak electric field at the drain side edge of the gate and improves the breakdown voltage. From the double pulsed ID-VDS measurement, we have found that the presence of the GaN cap layer reduces the current collapse due to gate-lag and drain-lag by passivating the surface traps of the access regions. Although there is a slight reduction in transconductance, the current gain cut-off frequency (fT) of the HEMT with GaN cap is higher than the HEMT without GaN cap.

Investigation of Ge-Based P-Channel Planar-Doped Barrier FETs integrated on Si

Ge-based p-channel Field-Effect Transistors (FETs) are regarded as the most promising devices to replace Si-based p-channel FETs with emphasis on reducing device power-consumption. Planar-Doped Barrier FETs (PDBFETs) are considered good candidates for tuning Ge-based FETs performance: with channels almost undoped except for a very thin region, creating necessary barrier for operation. PDBFETs enables inspection of behaviour with carriers away from surface, experiencing bulk properties. The aim of this work is to show the capability of the PDBFET concept to improve the performance of Ge-based devices even on large scaled device. Applying the concept of channel doping modulation to Ge-based FETs is demonstrated through fabrication and electrical characterization of Ge-based p-PDBFETs with optimistic results achieving off-state currents of sub-nA/μm even with relatively large sized devices, which are competitive in electrostatic performance to scaled, more complicated design devices. Sources of leakage current are considered through improving surface treatment. Applying low temperature measurements elaborated the possibility of higher performance with dimension scaling availability.

I–V Characteristics of E-mode GaN-based transistors under gate floating

This study investigates the I–V behaviors of various E-mode GaN-based transistors under gate floating and zero gate bias. The p-GaN gate high electron mobility transistor (HEMTs), gate injection transistors, and Cascode GaN FETs have been adopted and compared. The high off-state drain current is observed under gate floating except for Cascode GaN FETs based on the measured I–V characteristics. The off-state drain current of p-GaN gate HEMT is up to 0.8 mA under gate floating at a drain bias of 6 V, which is about 107 times larger than zero gate bias. The devices will induce false-turn-on and reverse conduction loss during switching under gate floating due to the capacitance charging effect between the drain and the gate electrodes. The mechanism of the capacitance charging effect is discussed using the equivalent circuit of p-GaN gate HEMTs and confirmed by Silvaco TCAD simulation.

Graphene film transistors based on asymmetric gate design combining with chemical doping

Graphene is considered a promising transistor component for future integrated circuits. Due to high operating speed and low power consumption, high on/off ratio and low off state current are ideal transistors. However, due to the inherent ambipolarity of graphene, a significant ambipolarity behavior with a fairly high off state current is usually observed in graphene transistors. In this work, an asymmetric gate design combined with a chemically doped method to suppress the ambipolarity of graphene transistors was reported. Thus, the off-state current is effectively reduced and the on-state current is increased. The on/off ratio is increased by nearly two orders of magnitude. Compare to the normal gate structure device, better threshold swing and smaller threshold voltage are obtained.

Vertical short-channel MoS&lt;sub&gt;2&lt;/sub&gt; field-effect transistors

Field effect transistors (FETs) based on two-dimensional (2D) materials have great potential applications in very large-scale integration technology, and high-performance short channel 2D semiconductor FETs are essential. Owing to the difficulty in obtaining channel lengths below 10 nm for 2D materials, there are few stable methods of fabricating short channel 2D semiconductor FETs. Here we report a method of stably fabricating vertical short-channel MoS&lt;sub&gt;2&lt;/sub&gt; FETs by using graphene as the contact material and h-BN as the spacer. The 8-nm spacer transistor exhibits good switching characteristics. The on/off ratio is greater than 10&lt;sup&gt;7&lt;/sup&gt; and the off-state current is less than 100 fA/μm under different source-drain voltages, which are immune well to the direct source-to-drain tunneling effect. This method can be used to rapidly screen two-dimensional materials that are immune to short-channel effects and also are suitable for the fabrication of high-performance FETs.

Branched Polyethylenimine-Based Field Effect Transistor for Low Humidity Detection at Room Temperature

In this paper, electrically insulating branched polyethylenimine (PEI) is applied to a field effect transistor (FET) sensor platform for low relative humidity (RH) detection (< 20%) at room temperature. The platform contains horizontally aligned control gate and floating gate, so that PEI is readily formed by simple ink-jet printing process. The electrical properties of the sensor in both dry and humid N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> are measured. The subthreshold swing, gate leakage current, and off-state drain current are increased by water vapor adsorptions. The mechanism behind the phenomenon is deeply investigated by building an equivalent circuit model of the sensor and molecular simulations of water-vapor adsorptions on PEI. It could be due to the formation of the dipoles on the surface of the PEI layer by the adsorptions of water vapors via hydrogen bonding and the polarization of those dipoles by gate biases. The drain current increases with the rise of relative humidity levels and a relative high response of 137.6% is obtained corresponding to 17.8% RH. The novel sensing principle of the proposed sensor lead a high sensitivity, linearity and resolution to low RH below 20%. This research demonstrates a promising low humidity-level sensing capability of the proposed sensor and the study on the sensing principle is very useful for more gas-sensing applications of polymers based on FET platforms.

P-GaN field plate for low leakage current in lateral GaN Schottky barrier diodes

High-voltage gallium nitride Schottky barrier diodes (SBDs) suffer from large off-state leakage current, which further degrades during operation at high temperatures and limits the device blocking capabilities. The key to achieving low off-state leakage is to protect the Schottky barrier from the high electric field, which is challenging by employing conventional field plate structures due to their large pinch-off voltage. In this work, we propose a simple AlGaN/GaN SBD architecture based on a p-GaN cap layer to achieve excellent off-state performance with a very low leakage current. By properly designing the AlGaN barrier and p-GaN cap, the pinch off-voltage of the p-GaN field plate is carefully controlled and the voltage drop over the Schottky junction is effectively reduced. In addition, a large carrier concentration in the access region is achieved, leading to a reduced sheet resistance. This results in good on-state performance along with a very low leakage current of ∼1 nA/mm at 400 V, which is maintained well below 100 nA/mm up to elevated temperatures of 150 °C. Moreover, the proposed architecture shares the well-established fabrication process of commercial p-GaN HEMTs and, thus, represents a promising and viable solution for future GaN diodes.

Anatomy of high-uniform unidirectional volatile switching behavior in SiO2/TiO2-based selection device

Unidirectional volatile switching behavior is a typical resistive switching phenomenon in oxides, which has been proposed as attractive candidates for selection devices for high density memory and neuromorphic systems applications with cross-point arrays. However, the microscopic origin of the underlying mechanism is still unclear due to the lack of direct experimental evidence. Here, a high performance selection device with a low forming voltage, low OFF-state current, high nonlinearity, and excellent uniformity is proposed in SiO2/TiO2 stacked structure. The underlying nature of the unidirectional volatile switching behavior in the Pt/Ag/SiO2/TiO2/Ti selection device is revealed by using scanning electron microscope and energy-dispersive X-ray spectroscopy analysis in planar structure devices, which can be attributed to the unstable conductive filament (CF) consisting of Ag nanoparticles formed in the SiO2 layer, and the Schottky contact formed between the Ag CF and TiO2 interface. This work provides clearly experimental evidence to deepen understanding of themechanism for unidirectional volatile switching behavior, which can provide a guide to further improve the device performances for high density memory and neuromorphic systems applications.

A Study on the Isolation Ability of LOCal Oxidation of SiC (LOCOSiC) for 4H-SiC CMOS Process

The oxidation rate of SiC can be greatly enhanced by pre-amorphization ion-implantation (PAI), and the PAI process has been employed to form the LOCal Oxidation of SiC (LOCOSiC) structure for device isolation in SiC integrated circuits (ICs). This work presents the study on the defect layer below the thermally grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and the impact of the defect layer on devices. The deep-level transient spectroscopy (DLTS) analysis reveals that the defect layer consists lots of C vacancies and Si vacancies. The leakage current of the edge-intensive N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /P-junction exhibits stronger temperature dependence than that of the P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /N-junction. This result confirms that C vacancy is an effective lifetime killer in n-type SiC, but not in p-type SiC. Although these defects increase the leakage current of the edge-intensive SiC N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /P-junction by 42 times at 150 °C compared with the junction with conventional chemical vapor deposited (CVD) field oxide (FOX), the leakage current is still much lower than the required OFF-state current of ICs. The defect layer has high resistance, and it is hard to let the SiC surface into inversion state so that the threshold voltage of the field MOSFET is higher than ±24 V.

Effects of interfacial oxide layer formed by annealing process on WORM characteristics of Ag/CuxO/SiOx/n+–Si devices

In this paper, we investigate the effects of a SiOx interfacial layer on ON/OFF current ratios, endurance characteristics and read-disturb immunities of Ag/CuxO/SiOx/n+-Si write-once-read-many-times (WORM) memories. The CuxO active layers were prepared using a sol-gel process. After coating CuxO films on n+-Si substrates, the CuxO/n+-Si samples were annealed in air at 400 ℃ and 600 ℃, respectively, to obtain a SiOx interfacial layer at the CuxO/n + -Si interfaces. The 400 ℃-annealed CuxO device shows an ON/OFF current ratio of 104. However, degradation of OFF state current (IOFF) with increasing read-pulse cycles and stress time is observed. For the 600 ℃-annealed CuxO device, stable ON and OFF state currents can be observed both in an endurance test for over 1.2 × 104 read cycles and in a read-disturb test for 2 × 104 s. Moreover, a higher ON/OFF current ratio of 107 is obtained. A rigorous retention test executed at an elevated temperature of 85 ℃ indicates that the data retention time is expected to last for 10 years. The performance improvement of the 600 ℃-annealed CuxO device is due to an increase in the thickness of the SiOx interfacial oxide layer. The mechanism for the influence of the interfacial layer on memory performance is investigated and illustrated. The OFF state current of the memory is limited by hopping and trap-assisted tunneling transport in the SiOx interfacial layer. In the ON state, conductive paths in the device cause that the carriers can easily migrate by Ohmic and space charge limited conduction.

Microwave and furnace annealing in oxygen ambient for performance enhancement of p-type SnO thin-film transistors

In this study, we investigated the effect of microwave-irradiation annealing (MWA) and thermal furnace annealing (FA) in oxygen ambient on the active channel layer of p-type tin-oxide (SnO) thin-film transistors. At very low source-drain voltage of −0.1 V, the MWA at 1200 W and FA at 300 °C samples have exhibited significant improvement in the electrical characteristics such as subthreshold swing (SS) of 0.93 and 0.485 V dec−1, the I on/I off ratio of 1.65 × 104 and 3.07 × 104, the field-effect mobility (μ FE) of 0.16 and 0.26 cm2 V−1 s and ultra-low off-state current of 1.9 and 2.0 pA respectively. The observed performance enhancement was mainly attributed to the reduction of interface trap density (N t) by tuning the power of MWA and optimizing the temperature in FA. From the result, we observed the optical band gap (E g) increased by 6% in FA, and 12% in MWA, which confirms improved crystallinity and reduction of defect states. Additionally, a low thermal budget microwave anneal process has shown high transmittance of more than 86% in the visible region (380–700 nm). The physical characterization indicates the partial phase transformation of SnO to SnO2 with retaining p-type conductivity in both annealing processes. The results demonstrate that both the annealing process could be highly promising to be used in the complementary logic circuits of new generation flexible/transparent displays.

32 × 32 Pixelated High-Power Flip-Chip Blue Micro-LED-on-HFET Arrays for Submarine Optical Communication.

This work proposes the use of integrated high-power InGaN/GaN multiple-quantum-well flip-chip blue micro light-emitting diode (μ-LED) arrays on an AlGaN/GaN-based heterojunction field-effect transistor (HFET), also known as a high electron mobility transistor (HEMT), for various applications: underwater wireless optical communication (UWOC) and smart lighting. Therefore, we demonstrate high-power μ-LED-on-HEMT arrays that consist of 32 × 32 pixelated μ-LED arrays and 32 × 32 pixelated HEMT arrays and that are interconnected by a solder bump bonding technique. Each pixel of the μ-LED arrays emits light in the HEMT on-state. The threshold voltage, the off-state leakage current, and the drain current of the HEMT arrays are −4.6 V, <~1.1 × 10−9 A at gate-to-source voltage (VGS) = −10 V, and 21 mA at VGS = 4 V, respectively. At 12 mA, the forward voltage and the light output power (LOP) of μ-LED arrays are ~4.05 V and ~3.5 mW, respectively. The LOP of the integrated μ-LED-on-HEMT arrays increases from 0 to ~4 mW as the VGS increases from −6 to 4 V at VDD = 10 V. Each pixel of the integrated μ-LEDs exhibits a modulated high LOP at a peak wavelength of ~450 nm, showing their potential as candidates for use in UWOC.

Optimization of Self-Heating Driven Leakage Current Properties of Gate-All-Around Field-Effect Transistors Using Neural Network Modeling and Genetic Algorithm

As the technology nodes of semiconductor devices have become finer and more complex, progressive scaling down has been implemented to achieve higher densities for electronic devices. Thus, three-dimensional (3D) channel field-effect transistors (FETs), such as fin-shaped FETs (FinFETs) and gate-all-around FETs (GAAFETs), have become popular as they have increased effective surface areas for the channels (Weff), owing to the scaling down strategy. These 3D channel FETs, which have completely covered channel structures with gate oxide and metal, are prone to the self-heating effect (SHE). The SHE is generally known to degrade the on-state drain current; however, when AC pulsed inputs are applied to these devices, the SHE also degrades the off-state leakage current during the off-phase of the pulse. In this study, an optimization methodology to minimize leakage current generation by the SHE is examined.

18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) for low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of the proposed transistor. Different sensitivity parameters of dopingless AJ DG MOSFET such as drain extension, length of gate overlapping and oxide thickness are compared with the AJ DG MOSFET with doped channel region. The ON-state current obtained is 3.80 x \({10}^{-6 }\)A/µm with reduced OFF-state leakage current up to1.37 x \({10}^{-17 }\)A/µm. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) of the device obtained are 59.5 mV/decade and 10.5 mV/V respectively. Temperature analysis of proposed device at various temperature such as 250 K,300 K, 350 and 400 K shows a small variation in OFF-state current (< 15 %). Additionally, a p-channel AJ DG MOSFET along with n-channel AJ DG MOSFET are designed and their performance is evaluated for CMOS inverter circuit and 6T SRAM cell. All design and analysis have been done with a 2D/3D Visual TCAD device simulator.

Finger Gate Vacuum Channel Field Emission Transistors: Performance and Sensitivity Analysis

In the current research, for the first time, Nano-scale finger gate vacuum channel field emission transistor (FGVFET) scaling down and its limitations considering electrical characteristics are studied. The FGVFET with different cathode electrode materials, channel dimensions, and finger widths is considered and the impacts of these structural and physical changes on the key indicators of the device are assessed to achieve a comprehensive design guideline. The sensitivity analysis reveals that the channel height modification by changing gate-anode oxide and cathode–gate oxide thicknesses can be assumed as the most significant design factor in the determination of ON–OFF-state currents. The results indicate that the gate leakage current as a salient parameter in device performance is dependent on the cathode material, channel depth, and height. Furthermore, investigating cutoff frequency as the prominent factor in high-speed applications indicates that cathode–gate oxide thickness may fundamentally modify this factor.