OFF Current Research Articles

Doping engineering to enhance the performance of a rectangular core shell double gate junctionless field effect transistor

This paper describes different architectures of a rectangular core shell double gate junctionless field effect transistor (RCS-DGJLT). The device performance has been studied when the core has either the same or opposite type of doping to the shell. It is found that an RCS-DGJLT with an oppositely doped core without heavily doped source/drain (S/D) extension regions exhibits an OFF current of ~10−14A and an ON current of ~10−5A. In addition, an RCS-DGJLT with heavily doped S/D extension and different placements of dopant concentration in the shell and core region is explored, so that control of charge carriers in the device during the ON and OFF states can be achieved. Further, the ON current is enhanced by doping engineering in the shell and core region without significantly degrading the OFF current. The RCS-DGJLT with heavily doped S/D extension along with oppositely doped core exhibits an OFF current of ~10−12A and an ON current of ~10−4A. The performance parameters such as the OFF current, ON current, ON/OFF current ratio, subthreshold slope, threshold voltage and transconductance are calculated. The performance of the proposed RCS-DGJLT fused with doping engineering is compared with previously published results on a DGJLT integrated with technology boosters from the literature, and is found to have superior performance to its counterparts.

The impact of donor/acceptor types of interface traps on selective buried oxide TFET characteristics

This paper investigates the reliability of the selective buried oxide TFET δp+ silicon-germanium layer at the tunneling junction. The impact of various uniform and Gaussian trap distributions and energies on the band-to-band tunneling current has been examined. The device has been optimized for different gap positions in the buried oxide. The OFF current of the proposed device is 1.7 × 10−18 A/µm. It has been observed that the effect of Gaussian trap is more compared to that of uniform trap. The study quantifies the DC parameters such as ION/IOFF ratio, subthreshold swing against different types of interface traps (donor or acceptor), density (Dit), position (near the tunneling junction or oxide/channel interface) and trap energy level (Etrap). Drain current reduces in the presence of acceptor-type trap and the variation is more for large trap density (1 × 1014 cm−3). An opposite behavior is perceived in the presence of donor-type traps. The device with highest acceptor trap concentration (1 × 1014 cm−3) provides minimum ON current of 2.21 × 10−6 A/µm whereas in case of donor trap concentration (1 × 1014 cm−3), highest ON current of 2.93 × 10−5 A/µm is obtained. The device with no traps proves to be better by providing maximum ION/IOFF ratio of 3.89 × 1012 with SS of 45 mV/dec. Further, the affectability of quantum correction on various electrical parameters has been studied for different types of traps.

Impact of core thickness and gate misalignment on rectangular core–shell based double gate junctionless field effect transistor

A rectangular core is inserted in double gate junctionless transistor (DGJLT) which separates the top shell and bottom shell in the device called as rectangular core–shell double gate junctionless transistor (RCS-DGJLT). The core doping and core thickness are optimized to improve the performance of RCS-DGJLT. The core thickness is optimized for different shell thicknesses in the device which has not been explored yet in the literature. An interesting observation is found that the core thickness should be equal to the shell thickness for smaller shell thicknesses, whereas the thicker core is required for larger shell thicknesses. RCS-DGJLT has shown remarkable improvement than DGJLT. Further, the effect of gate misalignment on either side (source/drain) of the channel in RCS-DGJLT and DGJLT is studied and compared on the basis of device performance. The study of gate misalignment becomes essential due to the complications on achieving perfectly aligned gates during the fabrication of double gate device. An RCS-DGJLT is found to have better tolerance to gate misalignment than DGJLT. The best parametric values like OFF current is ∼10–16A, ON current is ∼10–5A, subthreshold slope is nearly 66.2 mV/decade, ON/OFF current ratio is ∼1010, drain induced barrier lowering is ∼42.1 mV V−1 and threshold voltage ∼0.56 V at perfectly aligned gate condition is obtained on keeping core and shell thickness at 3 nm each. As per the analysis, the gate misalignment up to 20% on either side of the channel does not impact the performance parameters much and hence reduces the stress of meeting the requirement of perfect gate alignment.

Improved Drive Capability of Silicon Nano Tube Tunnel FET Using Halo Implantation

In this paper, we focus on the improvement of comprehensive device performance of Silicon Nanotube Tunnel Field Effect Transistor (NT_TFET) for ultra low power applications. In the design we have implanted 2nm Halo region at the source side of Si NT_TFET for improving the subthreshold swing and short channel effects (SCEs). To prove the concept, the performance of Silicon Nanowire tunnel FET (NW_TFET), Silicon Nanotube TFET without Halo (NT_TFET) and Silicon Nanotube TFET with halo (NT_FET_HALO) implant are compared. The impact of halo doping profile on the Subthreshold swing, ON and OFF current are investigated. Further, the degradation of OFF state current due to Halo doping is controlled by lightly doped drain.

Investigation of Recessed Junctionless Double Gate MOSFET for Radio Frequency Applications

Junctionless Metal Oxide Semiconductor Field-Effect Transistor (JL MOSFET) is one of the promising candidate to replace the junction based MOSFET for upcoming technology nodes. Semiconductor industries are continuously urging for large ON current with the low OFF current and low specific on resistance. However, high ON current is achieved in Conventional (Conv.) JL DG MOSFET by using high doping concentration at the cost of high OFF current which leads depletion mode operation. Moreover, low doping, narrow channel thickness and high work function gate materials are using to operate Conv. JL DG MOSFET in enhancement mode (Vth > 0 V for N-JL DG MOSFET, Vth < 0 V for P-JL DG MOSFET) but ON current is reduced in all above mentioned solutions. To overcome the above mentioned problems, a new architecture is developed called Recessed JL DG MOSFET. In Recessed JL DG MOSFET silicon region is recessed under the gate region and some gate portion is extended towards source and drain region. Recessed JL DG MOSFET shows the same ON current as achieved in Conv. JL DG MOSFET with very low OFF current (leakage current) by considering high doping concentration. Surface potential, electron density, energy band distribution, drain current have been investigated to proof the enhancement mode operation of Recessed JL DG MOSFET. Figure of Merits (FOMs) for RF performance such as Trans-conductance, capacitance and intrinsic power gain (S21), Trans-conductance frequency product (TFP), Gain frequency product (GFP) and Gain trans-conductance frequency product (GTFP) have also investigated of Recessed JL DG MOSFET.

A non-uniform silicon TFET design with dual-material source and compressed drain

Tunnel FET is the well-built candidate in the field of low-power ICs mainly because of its lower subthreshold swing (SS). But its ON current is relatively small and ambipolar current is high. The advantage of having a lower SS does not hold for higher gate voltages, which leads to higher average SS. In this paper, for the first time, a non-uniform channel with double-material source and compressed drain TFET structure is introduced. The simulation results show that the proposed structure has a minimum point SS of 9 mV/decade and an average SS of 22 mV/decade for a wide range of gate voltages. In addition, the ambipolar current, ON current, and OFF current are obtained to be 10−14 A/μm, 10−5 A/μm, and 10−16 A/μm, respectively, which lead to a remarkable value of the ON–OFF current ratio of about 1011. The effects of trap charge at oxide/semiconductor interface for different trap charge distributions have been investigated. Finally, it is observed that as compared to uniform distribution traps, Gaussian distribution traps degrade the characteristics in terms of ON–OFF current ratio and SS.

A Novel Extended Source TFET with δp+- SiGe Layer

Tunnel FET (TFET) is a significant discovery in the field of low power application, which has the ability to sustain short channel effects arising due to scaling. But the disadvantage of TFET is low ON current, and it is a challenge to maintain a high ON current with very low OFF current, hence it is tough to obtain a higher switching ratio maintaining a low SS. In this paper, to investigate the influence of dimensionality and other electrical parameters on TFET with simulation, a device based on an extended source TFET (ES-TFET) with SiGe pocket layer at the edge of source channel junction is proposed. It shows excellent performance improvement over standard TFET. In this paper, for the first time the effect of increase in length of the extended source has been studied while SS degrades but threshold voltage remains unchanged, also extended source distance from surface degraded effect on SS has been improved with the introduction of SiGe layer. Various scaling parameters have been investigated to study its impact on electrical parameters showing an ON-current of 0.01 mA/μm and OFF-current of 6.48 × 10−17 A/μm neglecting gate leakage for 1 V gate and drain voltage. The Remarkable value of SS of 16 mV/decade and ON-OFF current ratio of more than 1011 for a threshold voltage of 0.4 V is obtained. Scalability of the proposed device according to ITRS is well maintained, and it is validated by its improved performance over the wide range of channel length.

Performance Analysis Of Double-Gate Carbon-Nanotube FET And MOSFET For High Speed Integrated Circuits Design

This paper explains the detailed structure as well as performance of DG-CNTFET (Double Gate Carbon Nanotube Field Effect Transistor) and its performance is compared with the DG-MOSFET (Double Gate Metal Oxide Semiconductor Field Effect Transistor). Various parameters like I-V characteristics, ON current, OFF current and ON to OFF current ratio have been evaluated using nano-TCAD ViDES. Also, the transport description of DG-MOSFET and DG-CNTFET has been described in detail. It has been observed that DG-CNTFET has lower OFF current and higher ON current in comparison to the DG-MOSFET. The higher ON current of DG-CNTFET depicts that it requires less time to turn on the device in comparison with DG-MOSFET. Also, OFF current of the DG-CNTFET is lesser as compared to MOSFET. The DG-CNTFET’s higher ON to OFF current ratio outperforms the DG-MOSFET in term of switching speed of the device. It is proposed that CNTFET can be used as an alternative of MOSFETs for high speed Integrated Circuit (IC) design.

Design and Analysis of Dual Source Vertical Tunnel Field Effect Transistor for High Performance

An optimally designed Dual Source Vertical Tunnel Field Effect Transistors is proposed and investigated using technology computer aided design simulation. The vertical tunnel FET have dispersal of source channel drain in the vertical direction which will enhance the scalability of the simulated device. The benefit of the TFET is switching mechanism which is done by quantum tunnelling method through a barrier instead of thermionic emission over the barrier as that of conventional MOSFETs. The key of this paper, we have developed two-dimensional model of single drain with dual source n-type vertical tunnel field effect transistor. Further introduction to an ultra-thin channel among the drain and gate region will makes aggressive improvement in the numerical simulations of minimum threshold voltage (VT) of 0.15 V and average subthreshold slope of 3.47 mV/decade. The variation effect in the channel thickness, source height, drain doping, source doping, temperature and work function has been simulated and examined by 2D silvaco TCAD tool. High ON current and low OFF current is recorded as 1.74 × 10−4 A/µm and 6.92 × 10−13 A/µm respectively with ION/IOFF current ratio in order of 108 to 109.

An Analytical Modeling for Dual Source Vertical Tunnel Field Effect Transistor

The given paper proposes the 2D analytical modeling of surface potential and electric field for a Dual Source Vertical Tunnel Field Effect Transistor (DSV-TFET). The 2-D Poisson equations are solved by parabolic approximation method, with the help of suitable boundary conditions and analytical expressions for surface potential and electric field distribution in DSV-TFET. The analytical results of proposed model are compared with simulation results drive using SILVACO TCAD tool, whereas in our proposed device DSV-TFET provides the high on current (ION=1.74×10-4 A/μm), low OFF current (IOFF= 6.92 ×10-13 A/μm), ION/IOFF current ratio in order of 108 to 109 with the minimum point of average subthreshold slope of 3.47 mV/decade which can be used for low power application.

Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture

This paper proposes a p-type double gate junctionless field effect transistor having opposite doping in the core with that of the silicon body referring to rectangular core–shell (RCS) architecture. The use of RCS has significantly reduced the gate induced drain leakage and therefore, obtaining improved performance parameters. It is observed that the parasitic BJT action gets diminished in RCS architecture due to enlargement of tunneling width at the channel/drain interface. Further, after validating our simulations with the experimental results of junctionless p-type FET we demonstrated that insertion of oppositely doped core in silicon body helps to achieve volume depletion in OFF state. The simulation results show that junctionless FET with RCS architecture exhibit lower OFF current, higher ON/OFF ratio, better drain induced barrier lowering (DIBL) and superior subthreshold slope (SS) at lesser channel lengths. The measured values of OFF current, ON current, ON/OFF ratio, DIBL and SS at channel length 20 nm for RCS architecture are −9.96 × 10−15 A, −2.33 × 10−5 A, 0.23 × 1010, 42.1 mV V−1 and 67.7 mV/decade respectively. Interestingly, we have found a correlation between RCS thickness and channel length. Finally, a complementary metal oxide semiconductor (CMOS) inverter with RCS architecture is also designed. The voltage transfer characteristics of RCS based CMOS has been significantly improved as compared to the conventional junctionless CMOS inverter.

Quantum simulation of a junctionless carbon nanotube field-effect transistor under torsional strain

Abstract In this paper, a MOS-like junctionless carbon nanotube field effect transistor (JL-CNTFET) has been investigated. Energy band-gap and density of states (DOS) of carriers are two major parameters which are changed according to the torsional strain and affected the performance of JL-CNTFET. In this study, the effects of torsional strain on the analog (i.e., unity gain frequency (fT), transconductance (gm) and output resistance (rout)) and digital (i.e., OFF current, am-bipolar) characteristics of the device and also the switching behavior of the device have been studied and discussed. The simulation has been done using the non-equilibrium Green's function (NEGF) approach. The results show that torsional strain exerts significant effects on the electrical properties of the device and considering the multiple application of this transistor, it can also be used to improve the electrical properties of the transistor in specific applications.

Design and Analysis of Gate All Around Tunnel FET based SRAM

Tunnel FETs (TFETs) possess all required characteristics for replacing MOSFET device in circuits with stringent requirements particularly for Internet of Things (IoT) and Biomedical applications. In particular Gate-All-Around (GAA) TFET device configuration exhibits higher ION/IOFF ratio and strong control of the gate terminal over the channel. The main objective of this research work is to explore the prospects of using GAATFET device topology for designing low power and reliable SRAM cell. In this work both n-type and p-type Tunnel FET devices have been designed and simulated using Cogenda Visual TCAD tool. Verilog-A model relying on look up tables that are extracted through device simulations has been designed for performing circuit simulations of 6T and 8T SRAM cell involving these novel devices. Device simulation results show that both NTFET and PTFET devices exhibits excellent ION/IOFF ratio and steep subthreshold slope. NTFET device simulation results show 21.2 mV/decade of subthreshold slope and ION/IOFF ratio of 1013. PTFET device has ON current of the similar order as that of NTFET and has extremely low value of OFF current of less than 1 pA. Circuit simulation results show that by using optimized sizing of transistors in outward NTFET access transistor based 6T SRAM cell leads to reliable and fast read and write operation with acceptable values of noise margin. 6T TFET based SRAM cell achieves leakage power reduction by 77.5% in comparison to leakage power consumed by 8T TFET based SRAM thereby making it a favorable choice for memory design.

Nanoscale 3D Stackable Ag-Doped HfOx-Based Selector Devices Fabricated through Low-Temperature Hydrogen Annealing.

Electrochemical metallization-based threshold switching devices with active metal electrodes have been studied as a selector for high-density resistive random access memory (RRAM) technology in crossbar array architectures. However, these devices are not suitable for integration with three-dimensional (3D) crossbar RRAM arrays due to the difficulty in vertical stacking and/or scaling into the nanometer regime as well as the asymmetric threshold switching behavior and large variation in the operating voltage. Here, we demonstrate bidirectional symmetric threshold switching behaviors from a simple Pt/Ag-doped HfOx/Pt structure. While fabricating the Pt/Ag-doped HfOx/Pt film using a 250 nm hole structure, filaments composed of Ag nanoclusters were constructed through a low-temperature (∼200 °C) hydrogen annealing process where the shape of the film in a nanoscale via a hole structure was maintained for integration with 3D stackable crossbar RRAM arrays. Finite Ag filament paths in the HfOx layer led to uniform device-to-device performances. Moreover, we observed that the hydrogen annealing process reduced the delay time through the reduction of the oxygen vacancies in the HfOx layer. Consequently, the proposed Pt/Ag-doped HfOx/Pt-based nanoscale selector devices exhibited excellent performance of high selectivity (∼105), ultralow OFF current (∼10 pA), steep turn-on slope (∼2 mV/decade), and short delay time (3 μs).

Optimizing the Properties of InGaZnOx Thin Film Transistors by Adjusting the Adsorbed Degree of Cs+ Ions.

To improve the performance of amorphous InGaZnOx (a-IGZO) thin film transistors (TFTs), in this thesis, Cs+ ions adsorbed IGZO (Cs-IGZO) films were prepared through a solution immersion method at low temperature. Under the modification of surface structure and oxygen vacancies concentrations of a-IGZO film, with the effective introduction of Cs+ ions into the surface of a-IGZO films, the transfer properties and stability of a-IGZO TFTs are greatly improved. Different parameters of Cs+ ion concentrations were investigated in our work. When the Cs+ ions concentration reached 2% mol/L, the optimized performance Cs-IGZO TFT was obtained, showing the carrier mobility of 18.7 cm2 V−1 s−1, the OFF current of 0.8 × 10−10 A, and the threshold voltage of 0.2 V, accompanied by the threshold voltage shifts of 1.3 V under positive bias stress for 5000 s.

Directed Assembly of Nanoparticle Threshold‐Selector Arrays

AbstractThe directed assembly of ordered arrays of cubic silver nanoparticles featuring distinct electrical threshold‐switching characteristics is reported. Threshold selectors are key elements for nonvolatile resistive random‐access‐memory architectures, as they suppress sneak path currents in crosspoint arrays. Nanocubes are site‐selectively immobilized on a TiO2‐coated silicon surface via a complementary molecular surface functionalization of nanoparticles and substrate based on a Cu(I)‐catalyzed alkyne‐azide cycloaddition without any physical template. Electrical characterization of individual silver nanocubes by conductive‐probe atomic force microscopy reveals pronounced and reproducible threshold‐switching behavior, featuring ultralow OFF currents below 1 pA, steep turn‐on slopes of &lt;50 mV dec−1 and ON‐OFF ratios in excess of 103. Numerical simulation of Ag‐ion migration dynamics in the TiO2 electrolyte using a kinetic Monte Carlo model supports a switching mechanism based on conductive filament formation from Ag nanoclusters, and their reversible rupture in the low‐voltage regime. Assembled Ag nanocube threshold selectors are proposed for applications in memristive memory architectures, in particular for future highly integrated 3D circuitry.

Noise behaviour of δp+ Si1−xGex layer SELBOX TFET

This paper explores an analysis of low- and high-frequency noise in a heterojunction, selective buried oxide (SELBOX) with high-k gate dielectric TFET. The electrical parameters for different doping concentrations, δp+ layer width and mole fractions have been investigated. The proposed structure has been optimized for different positions of small gap on SELBOX substrate. It has been observed that the presence of small gap on SELBOX near the source region provides the lowest OFF current. The variation of noise (flicker + diffusion + generation − recombination) with frequency has been analysed. Further, the effect of various noise components on the device performance considering the current noise spectral density (SID) and voltage noise spectral density (SVG) is investigated. The impact of germanium mole fractions on noise components has been examined in terms of normalized current noise power spectral density and subthreshold swing.

(Invited) Polymer Resistive Electronic Memory: Exploiting Bistability of Current-Voltage Characteristics

Electronic memory elements represent indispensable components of most electronic circuits. For some applications, like RFID tags used for smart packaging, for manufacturing and warehouse automation or security systems, simple low-level performance devices are required, which could be produced by cheap large scale production technology, as e.g. printing. We focus on resistor-type memory (ReRAM) made from switchable resistive materials. Unlike transistor and capacitor memory devices, ReRAM does not require a specific cell structure, which is difficult to prepare by printing. ReRAM is a simple two electrode device based on a sandwich structure, in which data are stored as different electrical conductivity states. Electrical bistability usually arises from changes of the intrinsic materials properties, such as charge transfer, phase change, conformation change and reduction–oxidation (redox) reaction, in response to an applied electric field. The basic memory cells can be integrated into a cross-point memory array, where each memory cell is unambiguously identified by its x and y coordinates, suitable for easy programming and reading the addressed cell. We show the preparation and properties of simple organic memory elements based on thin films of soluble polymers, which can be prepared using common laboratory casting techniques as spin casting, slot die or dip coating, or screen and inkjet printing in the manufacturing scale. Two systems are presented: (i) Molecularly-doped polymer based on a soluble derivative of polydiketopyrrolopyrrole mixed with a soluble low-molecular weight derivative of perylene sandwiched between ITO and Al electrodes shows pronounced hysteresis in its current voltage characteristics. Depending on the composition, the maximum achieved ON/OFF ratio was about 5 with writing/erasing voltage +/-5 V and reading voltage 0.5 V. The functionality of the structure as rewritable resistive memory is well documented on repeated read-write cycles and a retention time exceeding several hours. The properties of the memory element were further improved by the incorporation of a very thin insulating layer of high-k dielectrics containing molecular groups with high permanent dipole. Such elements reached the ON/OFF ratio about 103. (ii) A single component polymer rewritable resistive memory was prepared using a newly synthesized poly(N-(3-(9H-carbazol-9-yl)propyl)methacrylamide) sandwiched as a thin film between ITO and Al electrode. The polymer was prepared by a radical polymerization of the N-(3-(9H-carbazol-9-yl)propyl)methacrylamide using azobisisobutyronitrile as a radical initiator. The starting monomer was obtained by three-step reaction from carbazole. The molar mass of the polymer was influenced in limited extent by the reaction temperature but it was still relatively low (M w = 6000, M n = 4000, Ð = 1.50). However, the film forming abilities were sufficient, particularly in thin films (typical thickness used in the memory elements was below 100 nm). The polymer is stable at higher temperatures up to 300 °C, glass transition temperature of the polymer is 130 °C. The device showed good hysteresis in I-V characteristics with switching effects, maximum ON/OFF ratio ~ 200..A typical write/erase cycle is shown in Fig. 1 showing a good retention time exceeding 2 hours even during permanent reading in both ON and OFF states. Here, writing was at the applied voltage +5 V erasing with -5 V and reading at 0.5 V (sign refers to the polarity of the ITO electrode). After some initial instability during memory element forming, the ON and OFF current was stable during more than 40 repeated write/erase cycles. Work supported by the Grant Agency of the Czech Republic, project No.17-03984S Figure 1

Short‐Channel Vertical Organic Field‐Effect Transistors with High On/Off Ratios

AbstractA unique vertical organic field‐effect transistor structure in which highly doped silicon nanopillars are utilized as a gate electrode is demonstrated. An additional dielectric layer, partly covering the source, suppresses bulk conduction and lowers the OFF current. Using a semiconducting polymer as active channel material, short‐channel (100 nm) transistors with ON/OFF current ratios up to 106 are realized. The electronic behavior is explained using space‐charge and contact‐limited current models and numerical simulations. The current density and switching speed of the devices are in the order of 0.1 A cm−2 and 0.1 MHz, respectively, at biases of only a few volts. These characteristics make the devices very promising for applications where large current densities, high switching speeds, and high ON/OFF ratios are required.

An Analytical Modeling and Simulation of Surrounding Gate TFET with an Impact of Dual Material Gate and Stacked Oxide for Low Power Applications

In this paper, an analytical model for modified Surrounding Gate Tunnel FET with gate stack engineering and different gate metals has been developed. Further, considering the scaling advantageous of Gate stack engineering and high degree performance of dual material engineering, the both has been integrated into a novel structure known as Surrounding Gate (SG) Tunnel FET with stacked oxide SiO2/high-k and dual material (DM) has been proposed. The two dimensional (2D) potential at the surface and electric field mathematical models for the DMSG TFET are developed by solving 2D Poisson's equation with matching device boundary conditions. Based on the Kane's formula, mathematical expression for the band-to-band (BTB) tunneling generation rate is derived and then used to calculate the drain current. The impact on the proposed device performance due to the variation of different device parameters has also been studied. It has been found from the presented results that the ON current of the DMSG TFET with stack is 10-6A, OFF current is 10-13A and ON/OFF ratio is 107. The mathematical results have been verified using the simulated results obtained from TCAD, a 3-D device simulator from ATLAS.