Number Of Test Patterns Research Articles

TRAP-GATE: A Probabilistic Approach to Enhance Hardware Trojan Detection and its Game Theoretic Analysis

Rescuing Hardware from malware attacks is a great challenge today. Moreover detecting the presence of malicious intrusion using low-cost techniques is very challenging especially when it is believed that hardware Trojans are integrated into the rarely excited nodes. Though logical testing is admitted to be the accurate way to check the functional correctness of the circuit, the method becomes inefficient for circuits requiring humongous number of test patterns to activate the hardware trojan. This paper proposes a probabilistic approach to generate a set of test patterns that activate the Trojan explicitly by observing the incorrect responses to the applied test patterns. Our experimental result in ISCAS’85 benchmark circuits show that the test patterns generated by our approach enclose all nets where there is a high chance for trojan insertion. We stress that though our results are circuit specific, the proposed approach is generic and hence it can be applied to any digital circuit. In fact, we demonstrate that for the C880 circuit, our approach requires only 217 inputs to be tested whereas the naive approach needs 260 test patterns. In addition to the experimental results, we use a game-theoretic framework to show the effectiveness of our approach in generating trojan activating test patterns compared to naive and ATPG testing process.

Graph‐based approach towards hardware Trojan vulnerability analysis

The author proposes an incremental windowing technique based on graph technique to detect hardware Trojan triggering signal. First, they analyse the switching activity file generated during simulation. Then, based on the window size of choice, they extract paths of n-HT (n-hardware Trojan; n is the number of triggering signals) and compare the path information with the HT instances from HT database to determine HTs' earliest/farthest activation time. They experiment with the incremental windowing technique on 420 combinational HT instances for four combinational designs. The results indicate that small and stealthy HT is active for a limited set of the time window and the number of test patterns during these windows is compact instead of exhaustive traditional random vector based Automatic Test Pattern Generation (ATPG).

Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs

In this article, we propose a method for designing online totally self-checking (TSC) comparators for TSC systems implementable on field-programmable gate arrays (FPGAs). This method can be used to conduct exhaustive online diagnostics of each lookup table (LUT), which involves mapping the fundamental components of the comparator, with a small number of test patterns by directly measuring output of each LUT. Our method drastically reduces the number of test patterns for exhaustive diagnosis on the order of the input number n [ $O(n)$ ] ( n is the input number to the comparator) while maintaining 100% coverage, even if we only know the specifications of the LUT without knowing its detailed structure. FPGAs will be easily applicable to systems that require high dependability. To confirm the soft error rate (SER) in a static random-access memory (SRAM)-based FPGA, we also conducted an experiment involving a single-event upset (SEU) caused by neutron radiation. For this experiment, we designed an FPGA implementation of 1575 identical dual-modular-redundant TSC comparators. The experiment was conducted for 10.4 h, and 34 errors were observed regarding such failures in comparator function. The evaluated SER for the TSC comparator with the proposed method was 0.055 FIT at sea level of New York City.

Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices

Microfluidic biochips are revolutionizing the traditional biochemical experiment flow with their high execution efficiency and miniaturized fluid manipulation. To improve the flexibility of such chips, Programmable Microfluidic Devices (PMDs) have been introduced, with valves and channels built as a regular array. To take advantage of this new architecture, design automation methods have started to appear, but an efficient test generation algorithm is still unavailable. In this paper, we propose to generate test patterns based on spanning trees for this architecture. Compared with previous work, the proposed method is around 100 times faster, while the number of test patterns is still comparable.

Layout-Based Test Coverage Verification for High-Reliability Devices

Test quality is critical to eliminate test escapes and to achieve high-reliability large-scale integrated (LSI) devices. This paper proposes a new concept called “physical test coverage” to verify test coverage based on the physical layout of LSI circuits. The physical test coverage is calculated as the ratio between the critical area of all wires in a device and that of wires undetected by LSI tests. From the critical area of undetected wires and the defect density of a manufacturing line, the risk of test escapes can be predicted. To effectively develop LSI tests that can minimize the number of test patterns, undetected wires are prioritized by the critical area related to each wire. Even when the conventional “logical” test coverage is high enough to satisfy the coverage criterion, some LSI devices investigated in this paper showed low physical test coverage depending on the physical layout of the LSI circuit. The concept of physical coverage was applied in the test development of some LSI products, and the test quality was substantially improved, such that 90% of test escapes of a device were eliminated.

Test Point Insertion with Control Point by Greater Use of Existing Functional Flip-Flops

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

Built‐in self test design of power switch with clock‐gated charge/discharge transistor

It is becoming common to implement header (footer) power switches in low-power system-on-chip. However, the switches are not tested for manufacturing defects in most designs currently. In this study, a novel built-in self test (BIST) solution for power switch is proposed. To accelerate the test of the header (footer) switches, a charge (discharge) transistor is adopted in the proposed BIST circuit and the corresponding charge (discharge) transistor is gated by the test clock. Therefore the number of test patterns, the length of test vectors and the test time are all decreased. Besides, the test responses can be identified easily. If the test responses are all logic-high, the tested switches are fault-free. Or else, the tested switches are faulty. In addition, the structure of the proposed BIST circuit can be scaled freely with the amount of switches. For m switches, it takes m + 2 cycles to locate the faulty switches at worst. Finally, to verify the proposed BIST circuit, the BIST design with 255 header switches is implemented with SMIC 0.18 μm 1P6M logic process. The corresponding area is 0.043 mm 2 . The simulation results show that the BIST circuit can locate the possible manufacturing defects in the switches and discharge transistors within 257 clock cycles. The corresponding consumed power is 2.04 mW when the test frequency is 20 MHz.

Full-Custom Design and Implementation of High-Performance Multiplier

I proposed a method of using full-custom design 32 × 32 multiplier to enhance performance, reduce the power consumption and the area of layout. I use improved Wallace tree structure for partial product compression, truncated beyond the 64 part of the plot and the look-ahead logarithmic adder using Radix-4 Kogge-Stone tree algorithm raise the multiplier performance. In the design of Booth2 encoding circuit and compression circuit, I use a transmission gate logic design with higher speed and smaller area. I also use Euler path method and heuristic Euler path method to reduce the layout area. The design use SMIC 0.18μm 1P4M CMOS process, with a layout area of 0.1684mm2. In a large number of test patterns, simulation results show that the computation time of a 32 × 32 multiplication is less than 3.107ns.

Low Transition-Generalized Linear Feedback Shift Register Based Test Pattern Generator Architecture for Built-in-Self-Test

Problem statement: In Built-In Self-Test (BIST), test patterns are ge nerated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers. This nor mally requires more number of test patterns for testing the architectures which need long test time . Approach: This study presents a novel test pattern generation technique called Low-Transition Generali zed Linear Feedback Shift Register (LT-GLFSR) and it was also called Bipartite GLFSR. Intermediat e pattern (Bipartite technique) inserted in between consecutive test patterns generated by GLFSR was called LT-GLFSR technique which was enabled by a non overlapping clock scheme. Low-transition generalized linear feedback shift registers (LT-GLFSR), was used in a circuit under test to reduce the aver age and peak power during transitions. LT-GLFSR pattern generator would generate patterns with high er degree of randomness and high correlation between consecutive patterns would have efficient area impl ementation. LT-GLFSR did not depend on circuit under test and hence it could be used for both BIST and scan-based BIST architectures. Results/Conclusion: Simulation results show that this technique has re duction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces th e peak and average power consumption during test for ISCAS'89 bench mark circuits.

Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement

Acceptable faults in a circuit under test (CUT) refer to those faults that have no or only minor impacts on the performance of the CUT. A circuit with an acceptable fault may be marketable for some specific applications. Therefore, by carefully dealing with these faults during testing, significant yield improvement can be achieved. Previous studies have shown that the patterns generated by a conventional automatic test pattern generation procedure to detect all unacceptable faults also detect many acceptable ones, resulting in a severe loss on achievable yield improvement. In this paper, we present a novel test methodology called multiple test set detection (MTSD) to totally eliminate this overdetection problem. A basic test set generation method is first presented, which depicts a fundamental scheme to generate appropriate test sets for MTSD. We then describe an enhanced test generation method that can significantly reduce the total number of test patterns. Solid theoretical derivations are provided to validate the effectiveness of the proposed methods. Experimental results show that in general an 80%-99% reduction in the number of test patterns can be achieved compared with previous work addressing this problem.

Adapting Scan Based Test Vector for Compression Method Based On Transition Technique

Present complexity of System on Chip (SoC) design is increasing rapidly in the number of test patterns, huge switching activity and its transition time. This large test data volume is becoming one of the major problems in association with huge switching activity and its corresponding response time. This paper considers the problem of huge test pattern in scan based design. This proposed algorithm is based on reducing test pattern on scan shift in operation. This is achieved by identifying test data transition and equally segmenting the scan based test patterns. Each scan test pattern is considered by its transition and segmented into equal necessary blocks. This finally gives the compressed test patterns in reduced test patterns. Theoretical analysis and experimental results on ISCAS89 shows that the proposed method reduces test pattern by 37% when compared to the traditional approaches.

Generating Test Patterns for Multiple Fault Detection in VLSI Circuits using Genetic Algorithm

In this paper we propose a method for the automatic test pattern generation for detecting multiple stuck-at-faults in combinational VLSI circuits using genetic algorithm (GA). Derivation of minimal test sets helps to reduce the post-production cost of testing combinational circuits. The GA proves to be an effective algorithm in finding optimum number of test patterns from the highly complex problem space. The paper describes the GA and results obtained for the ISCAS 1989 benchmark circuits.

An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement

This paper presents a novel error-tolerance-based test methodology to grade defective chips according to their degree of acceptability so as to improve the effective yield of chips. We employ error rate as the attribute of error-tolerance to determine acceptability. We show that the number of test patterns that need to be applied to a circuit under test in estimating the circuit's error rate is highly dependent on how close the circuit's actual error rate is to the given grading thresholds. An iterative and adaptive error rate estimation technique is developed by which an appropriate number of test patterns can be efficiently determined and the circuit can be immediately classified into appropriate grades to fit various application requirements. Experimental results show that: 1) only a few iterations are required to classify a circuit, and 2) the total number of test patterns used is in general independent of the circuit size. Both of these observations imply that these techniques are applicable to large circuits.

A Low Overhead High Test Compression Technique Using Pattern Clustering With $n$-Detection Test Support

This paper presents a test data compression scheme that can be used to further improve compressions achieved by linear-feedback shift register (LFSR) reseeding. The proposed compression technique can be implemented with very low hardware overhead. The test data to be stored in the automatic test equipment (ATE) memory are much smaller than that for previously published schemes, and the number of test patterns that need to be generated is smaller than other weighted random pattern testing schemes. The proposed technique can be extended to generate test patterns that achieve high n-detection fault coverage. This technique compresses a regular 1-detection test cube set instead of an n-detection test cube set, which is typically n times larger. Hence, the volume of compressed test data for n-detection test is comparable to that for 1-detection test. Experimental results on a large industry design show that over 1600X compression is achievable by the proposed scheme with the test sequence length, which is comparable to that of highly compacted deterministic patterns. Experimental results on n -detection test show that test patterns generated by the proposed decompressor can achieve very high 5-detection stuck-at fault coverage and high compression for large benchmark circuits.

Scalable and bijective cells for C-testable iterative logic array architectures

In this study, a novel idea is proposed to test arithmetic circuits with both acceptable number of test patterns (NTP) and hardware overhead (HO). First, highly scalable full adder and full substractor are proposed. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between the NTP and the HO, which is a function of n. By adjusting the value of n, we can obtain an optimal balance between HO and NTP. An iterative logic array (ILA) based on these scalable cells will still be C-testable. Based on the novel bijective and scalable cells, the authors propose C-testable designs for multiplier-accumulator (MAC), N-tap finite impulse response (FIR) filter and matrix multiplication, where the (HO, NTP) pairs with n=2 are only about (4.87%, 74). For 4×4 matrix multiplication, the total test time of the proposed method is only about 0.19% of that with the scan-chain method. With scalable and bijective cells, all the proposed ILA solutions can be connected together into a bigger non-homogeneous ILA and save lots of test pins and build-in self-test (BIST) area. In addition, the proposed scalable cells induce a simple and systematic way to have balanced results. The proposed technique makes the ILA-based DFT schemes more practical, systematic and useful for real-world complex applications.

Design-for-testability techniques for CORDIC design

In this paper, we propose two C-testable design-for-testability (DFT) architectures for coordinate rotation digital computer (CORDIC) design. The first design is achieved by using scalable cells. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between hardware overhead (HO) and number of test patterns (NTP). Both HO and NTP change as n varies. By adjusting the value of n, we can obtain an optimal balance between HO and NTP. Based on these scalable cells, the iterative logic array (ILA) will be still C-testable. For the first proposed design, the HO and NTP for n=2 are 5.37% and 74, respectively. The second one is achieved by the reorganized test sequences, where the HO and NTP are only 3.15% and 18, respectively. The first design can be connected into a non-homogenous ILA for saving lot of test pins and built-in self-test (BIST) area; in the second one, the special properties of the sequences reduce HO/NTP significantly.

Quantum Boolean Circuits are 1-Testable

Recently, a systematic procedure was proposed to derive a minimum input quantum circuit for any given classical logic with the generalized quantum Toffoli gate, which is universal in Boolean logic. Since quantum Boolean circuits are reversible, we can apply this property to build quantum iterative logic array (QILA). QILA can be easily tested in constant time (C-testable) if stuck-at fault model is assumed. In this paper, we use Hadamard and general controlled-controlled not gates to make QILA 1-testable. That is, for any quantum Boolean circuit, the number of test patterns is independent of both the size of the array and the length of the inputs.

Design-for-testability and fault-tolerant techniques for FFT processors

In this paper, we first propose a novel design-for-testability approach based on M-testability conditions for module-level systolic fast Fourier transform (FFT) arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. Based on this testable design, fault-tolerant approaches at the bit level and the multiply-subtract-add (MSA) module level are proposed, respectively. If the reconfiguration is performed at the bit level, then the FFT/sub BIT/ network is constructed. Two types of reconfiguration schemes (Type-I FFT/sub MSA/ and Type-II FFT/sub MSA/) are proposed at the MSA module level. Since both the design for testability (DFT) and the design for yield (DFY) issues are considered at the same time for all these proposed approaches, the resulting architectures are simpler as compared with previous works. The reliability of the FFT system increases significantly. The hardware overhead is low-about 12% and 1/2N for the FFT/sub BIT/ network and the Type-II FFT/sub MSA/ network, respectively. An experimental chip is also implemented to verify our approaches. Reliabilities and hardware overhead are also evaluated and compared with previous works.

Three-stage compression approach to reduce test data volume and testing time for IP cores in SOCs

A three-stage compression technique that reduces test data volume and test application time for scan-based testing of intellectual property (IP) cores in system-on-chip integrated circuits is presented. In the first stage, referred to as width compression, the concept of scan chain compatibilities is combined with a method that exploits the logic dependencies between scan chains. This leads to a gated fanout decompression structure that uses c input channels to drive m scan chains (c≪m). Next, static compaction is used to reduce the number of test patterns, a step referred to as height compression. Finally, dictionary-based compression is used to further reduce test data volume. Structural information about the IP cores is not necessary for fault simulation, dynamic compaction, or test generation. By combining the advantages of the gated fan-out structure and dictionary-based compression, the proposed approach significantly reduces the test data volume and testing time with very little hardware overhead for on-chip decompression. Results are presented for the ISCAS-89 benchmarks and for four industrial circuits.

E-BIST: enhanced test-per-clock BIST architecture

A new built-in self-test architecture, E-BIST, suitable for a test-per-clock scheme, is proposed. The E-BIST architecture is based on STUMPS, which uses a linear feedback shift register (LFSR) as the test generator, a multiple input shift register (MISR) as the response compactor, and shift register latch (SRL) channels as multiple scan paths. In E-BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS technique. It is also shown that the masking probability of the proposed SRL channel structure is 21−(N+L), where N and L are the number of test patterns and the length of the SRL channel, respectively. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for robustly detecting path delay faults, with improved fault coverage, when the Hamming distance of the data in the SRL channel is considered.