Number Of Full Adders Research Articles

Improving security against cache memory attacks for dual field multiplier design based on elliptic curve cryptography

The elliptic curve cryptographic (ECC) technique is employed for various security standards like security key management, digital signature and data authentication. The ECC technique is capable of undertaking sequential and equivalent mode processes through the unified design that is used equally for binary field and in the leading area of cryptosystems. Furthermore, a progressive transposition method and control information route are combined with the ECC mainframe, which offers efficient throughput, and adaptive calculation with low power. The dual-field Montgomery multiplier-carry save adder (DMM-CSA) structure is designed for the ECC system. The DMM structure has been developed using CSA in this method. The adder requires more number of Full Adders for the circuit design, which has occupied more area. To overcome this problem, this work introduces the dual field Vedic multiplier-look up table carry select adder (DVM-LCSLA) which is used to increase the performance of the ECC scheme for 256 bit. The first aim of the methods mentioned above is to develop a high-performance modular inversion for the ECC technique by employing application specified integrated chip and field programmable gate array (FPGA) implementation with the help of Verilog code. FPGA results indicate the analysis of power utilization, time delay information and Hardware area overhead in DVM-LCSLA used in ECC system compared to the state-of-art methods.

Area and Power Potent VLSI Architecture for Modified CSLA with A Logic Optimization Technique

Through generations, in an endeavor to pioneer innovative circuit designs, an adder is having the greatest importance as it is a basic building block to decide the system’s overall performance. Wide varieties of adders are used for a plethora of applications in the field of Signal Processing and VLSI systems. Most predominantly used Speed efficient architecture for performing n-bit addition in VLSI applications is Square Root Carry Select Adder (SQRT-CSLA) as it pre-computes the carry and sum by assuming input carry as ‘zero’ and ‘one’. But the overall area usage is high as it uses more number of full adders when compared to Ripple Carry Adder. Though, the existing adder designing techniques are area efficient, there is still scope to achieve area efficiency as area decides the cost of the VLSI Systems. Not only area-efficient but also power potent architectures are required to accelerate the overall performance of the VLSI systems. To meet these objectives, this paper proposes an efficient VLSI architecture for carry select adder by using logic optimization technique addressing performance constraints. The proposed architecture is designed and implemented using cadence encounter tool for different data widths ranging from 16 bits to 128 bits. The performance of the proposed 128-bit architecture achieves an area improvement of 63.43% and a power improvement of 71.00923% when compared to 128-bit SQRT-CSLA architecture

Conditional Differential Coefficients Method for the Realization of Powers-of-Two FIR Filter

This paper proposes a new technique, called conditional differential coefficients method (CDCM), for hardware-efficient realization of finite impulse response filters using differential coefficients. In connection to this, a group of differential coefficients are extracted from the entire set which aims to reduce the total number of ones in the coefficient representation. Selection of the differential coefficients has been done in accordance with its difference with the original coefficient. It has the consequent effect of minimizing the total number of full adders with respect to direct method, minimum index floating point representation scheme, minimal difference DCM, and so on.

Design and Analysis of Hybrid Tree Multipliers for Reduction of Partial Products

This paper confers one of the three phases of tree multipliers, i.e. the Partial Product reduction phase. In this paper four types of hybrid tree multipliers are studied and proposed using parallel counters (full adders and half adders) for reduction of Partial Products in multiplication operation.After ANDing the bits of multiplier and multiplicand, the Partial Products are arranged into two groups for reduction, each group uses a different technique for reduction of Partial Products, resulting in a fewer gates than the parent tree reduction techniques. The results of the proposed tree reduction techniques are then tabulated and compared with the parent tree multipliers. The performance comparison is done in terms of number of gate counts of half adder and full adders used in the Partial Product reduction phase. Four types of hybrid tree multipliers are presented using CSA (Carry Save Adder) Array multiplier, Wallace Tree multiplier, Modified Wallace Tree multiplier and Dadda Tree Multiplier. The results show significant reduction in number of full adders and half adders with the slight overhead of increased final addition stage of the hybrid multiplier. The proposed multipliers can prove to be the better choice for digital signal processing designs, image processing designs and processor architecture.

Novel Minimum Index Floating Point representation for the design of powers-of-two filter

ABSTRACTIn this communication, we have suggested a new type of representation scheme for the tap coefficients of finite impulse response filter. Proposed Minimum Index Floating Point scheme divides each powers-of-two coefficient into two components, namely ‘span’ and ‘shift’, and applies one effective algorithm to reduce the highest index present in the span part. It has the consequent effect of minimising the total number of full adders as compared to direct method, Pseudo Floating Point (PFP) representation, PFP with intermediate adder stage and Differential Coefficient Partitioning Algorithm.

Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence

This paper focuses on developing an area efficient hyperbolic Coordinate Rotation Digital Computer (CORDIC) algorithm with performance improvement. The algorithm eliminates the need of scale factor calculation in the Range of Convergence (ROC). At the same time the range of convergence offered is higher than the conventional CORDIC ROC in the hyperbolic rotation mode. Being the only kind of algorithm in hyperbolic rotation with sign sequence μ?=?1 always, one complete operation requires just 5 iterations. Thus the pipelined implementation has 5 stages which provides a 50% increase in throughput in comparison to conventional CORDIC. As far as the area improvement is considered, 16-bit processor can be realized using 56% less number of full adders required by Flat-CORDIC. The x and y datapath are based on series expansion of hyperbolic functions. The complete algorithm design along with pipelined architecture implementation is detailed.

A Reduced Complexity Wallace Multiplier Reduction

Wallace high-speed multipliers use full adders and half adders in their reduction phase. Half adders do not reduce the number of partial product bits. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity. A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction. The modified reduction method greatly reduces the number of half adders; producing implementations with 80 percent fewer half adders than standard Wallace multipliers, with a very slight increase in the number of full adders.

Design of efficient multiplierless FIR filters

An algorithm for reducing the hardware complexity of linear phase finite impulse response digital filters that minimise the adder depth in the multiplier block adders (MBAs) is presented. The algorithm starts by aggressively reducing both the coefficient wordlength and the number of non-zero bits in the filter coefficients. This reduces the number of adders (the adder depth) that are needed to construct the coefficient multiplier and results in an increased operating frequency. A modification to the representation of the filter coefficients such that the number of full adders (FAs) in our hardware implementation is proportional to the product of the input signal wordlength and the number of adders is proposed. That is, in general, the number of FAs is independent of the coefficient wordlength and the number of shifts between non-zero bits in the coefficient. Results show that the proposed technique achieves a 67 and 70% reduction in the number of MBAs and the number of multiplier block FAs, respectively. A software program has been implemented, which generates a Verilog HDL description of the digital filter. The proposed technique is not limited to filters with only a small number of taps and has been successfully applied to filters with up to 500 taps.

Low-power differential coefficients-based FIR filters using hardware-optimised multipliers

A minimal-difference differential coefficients method is presented for low power and high-speed realisation of differential-coefficients-based finite impulse response filters. The conventional differential coefficients method (DCM) uses the difference between adjacent coefficients whereas we identify the coefficients that have the least difference between their magnitude values and use these minimal difference values to encode the differential coefficients. Our minimal-difference differential coefficients can be coded using fewer bits, which in turn reduces the number of full additions required for coefficient multiplication. By employing a differential-coefficient partitioning algorithm and a pseudofloating-point representation, we show that the number of full adders and the net memory needed to implement the coefficient multipliers can be significantly reduced. The proposed method is combined with common subexpression elimination for further reduction of complexity. Experimental results show the average reductions of full adder, memory and energy dissipated achieved by our method over the DCM are 40, 35 and 50%, respectively.

Low power and high-speed implementation of fir filters for software defined radio receivers

The most computationally intensive part of the wideband receiver of a software defined radio (SDR) is the intermediate frequency (IF) processing block. Digital filtering is the main task in IF processing. The computational complexity of finite impulse response (FIR) filters used in the IF processing block is dominated by the number of adders (subtracters) employed in the multipliers. This paper presents a method to implement FIR filters for SDR receivers using minimum number of adders. We use an arithmetic scheme, known as pseudo floating-point (PFP) representation to encode the filter coefficients. By employing a span reduction technique, we show that the filter coefficients can be coded using considerably fewer bits than conventional 24-bit and 16-bit fixed-point filters. Simulation results show that the magnitude responses of the filters coded in PFP meet the attenuation requirements of wireless communication standard specifications. The proposed method offers average reductions of 40% in the number of adders and 80% in the number of full adders needed for the coefficient multipliers over conventional FIR filter implementation methods

An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters

Algorithms that minimize the complexity of multiplication in digital filters focus on reducing the number of adders needed to implement the coefficient multipliers. Previous works have not analyzed the complexity of each adder, which is significant in low-complexity implementation. A multiplication algorithm for low-complexity implementation of digital filters with a minimum number of full adders (NFAs) and improved speed is proposed here. The authors exploit the fact that when multiplication is implemented using shifts and adds, the adder width can be minimized by limiting the shifts of the operands to shorter lengths. The coefficient-partitioning (CP) algorithm proposed here minimizes the shifts of the operands of the adders by partitioning each coefficient into two subcomponents. The authors show that by combining three methods, the CP algorithm, an efficient coefficient coding scheme known as pseudo floating-point (PFP) representation, and the well-known common subexpression elimination (CSE), the NFAs required in each adder of the multiplier can be reduced considerably. Design examples show that the method offers an average FA reduction of 30% for finite-impulse response (FIR) filters and 20% for infinite-impulse response (IIR) filters over CSE methods.

On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods

The most computationally intensive part of a wideband receiver is the channelizer. The computational complexity of linear phase finite impulse response (LPFIR) filters employed in the channelizer is dominated by the number of adders used in the implementation of the multipliers. In this paper, two methods are proposed to efficiently implement the channel filters in a wideband receiver based on common subexpression elimination (CSE). We exploit the fact that a significant amount of redundant multiplications exist in the filter-bank channelizer as it extracts multiple narrowband channels from the wideband signal. By forming three and four nonzero-bit super-subexpressions utilizing redundant identical shifts that exist between a two- nonzero-bit common subexpression (CS) and a third nonzero bit, or between two nonzero-bit CS, the number of adders to implement the channel filters can be reduced considerably. Furthermore, the complexity of the adders is analyzed and design examples of the channel filters employed in the digital advanced mobile phone system (D-AMPS) and the personal digital cellular (PDC) channelizers show that the proposed methods offer considerable reduction in the number of full adders when compared to conventional CSE methods.

Hardware-efficient FIR filters with reduced adder step

A technique for reducing the hardware complexity of constant coefficient finite impulse response (FIR) digital filters, without increasing the number of adder steps in the multiplier block adders, is presented. The filter coefficients are adjusted so that the number of full adders in the hardware implementation of any coefficient is independent of the coefficient wordlength and the number of shifts between nonzero bits in the coefficient. Results show that the proposed technique achieves a significant reduction in both the multiplier block adders and the multiplier block full adders when compared to existing techniques.

Fast Fourier Transforms Using the Complex Logarithmic Number System

The complex-logarithmic number system (CLNS), which represents each complex point in log/polar coordinates, may be practical to implement the Fast Fourier Transform (FFT). The roots of unity needed by the FFT have exact representations in CLNS and do not require a ROM. We present an error analysis and simulation results for a radix-two FFT that compares a rectangular fixed-point representation of complex numbers to CLNS. We observe that CLNS saves 9–12 bits in word-size for 256–1024 point FFTs compared to the fixed-point number system while producing comparable accuracy. The consequence of the word-size advantage is that the number of full adders required for CLNS is significantly smaller than for an equivalent fixed-point implementation. The major cost of CLNS is the memory, which unlike conventional LNS, is addressed by both real and imaginary parts. Table-reduction techniques can mitigate this. The simplicity of the CLNS approach requires significantly fewer full adders, which pays for some or all of the extra memory. In applications needing the magnitude of the complex parts, such as a power spectrum, the CLNS approach can actually require less memory than the conventional approach.

A real-time systolic integer multiplier

We describe the construction of two practical real-time systolic bit-serial multipliers: a pipelined multiplier and a nonpipelined multiplier. Our non-pipelined multiplier requires roughly half the hardware (number of full-adders) as compared to Atrubin's multiplier, which is the best real-time systolic multiplier known to-date. Our starting point is a serial/parallel multiplier which is not systolic, has a large number of primary inputs and does not support pipelining. We modify this design step by step using systematic methodologies until our design is obtained. The methodologies used in the design are: broadcast elimination, replacing parallel inputs with a broadcast mechanism and adding a simplified version of the circuit in order to enable pipelining. Applying these methodologies yields an improved circuit the correctness of which is easily understood.

The testability of generalized counters under multiple faulty cells

The testability of a class of circuits called generalized counters is investigated under a more powerful fault model than examined in earlier work. It is assumed that any number of full adders in a generalized counter can assume an incorrect function under fault, as long as the function remains combinational. The testability of the overall class of generalized counters is examined and it is shown that under a restricted fault model it is possible to detect all multiple faults with a test set that grows linearly with the number of counter inputs. It is then shown that for a subset of the class of generalized counters it is possible to detect multiple faults with a larger number of tests, linear to the number of counter inputs, when the restrictions on the fault model are relaxed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>