Number Of Flip-flops Research Articles

SCA-Safe Implementation of Modified SaMAL2R Algorithm in FPGA.

Cryptographic algorithms (RSA, DSA, and ECC) use modular exponentiation as part of the principal operation. However, Non-profiled Side Channel Attacks such as Simple Power Analysis and Differential Power Analysis compromise cryptographic algorithms that use such operation. In this work, we present a modification of a modular exponentiation algorithm implemented in programmable devices, such as the Field Programmable Gate Array, for which we use Virtex-6 and Artix-7 evaluation boards. It is shown that this proposal is not vulnerable to the attacks mentioned previously. Further, a comparison was made with other related works, which use the same family of FPGAs. These comparisons show that this proposal not only defeats physical attack but also reduces the number of resources. For instance, the present work reduces the Look-Up Tables by 3550 and the number of Flip-Flops was decreased by 62,583 compared with other works. Besides, the number of memory blocks used is zero in the present work, in contrast with others that use a large number of blocks. Finally, the clock cycles (latency) are compared in different programmable devices to perform operations.

High Level Synchronization and Computations of Feed Forward Cut-Set based Multiply Accumulate Unit

In a modern technology-based application, digital signal processing (DSP) is a major priority one, in this gadgets application, the Multiply Accumulate Unit (MAC) will occupy more memory usages, power consumptions and critical path delay. Due to the number of arithmetic operations, this MAC unit will play’s a major role in this application product. Thus, the pipelined based architecture will be used to reduce the number of critical paths delay and to improve the performance of MAC architecture. However, the number of flip flops will be increased in the MAC unit, due to number of pipelined architectures. Consequently, it will increase the area and the power consumption. Thus, proposed work of this paper will get a novelty process of feed forward cut-set based MAC architecture with high level synchronization of XOR-MUX full adder with compressor technique. It will reduce the number of logic gates in MAC architecture and hence prove the performance in FPGA Implementation of LUT based area, critical path delay and average power consumption.

Efficient implementation of LMS adaptive filter-based FECG extraction on an FPGA.

In this Letter, the field programmable gate array (FPGA) implementation of a foetal heart rate (FHR) monitoring system is presented. The system comprises a preprocessing unit to remove various types of noise, followed by a foetal electrocardiogram (FECG) extraction unit and an FHR detection unit. To improve the precision and accuracy of the arithmetic operations, a floating-point unit is developed. A least mean squares algorithm-based adaptive filter (LMS-AF) is used for FECG extraction. Two different architectures, namely series and parallel, are proposed for the LMS-AF, with the series architecture targeting lower utilisation of hardware resources, and the parallel architecture enabling less convergence time and lower power consumption. The results show that it effectively detects the R peaks in the extracted FECG with a sensitivity of 95.74–100% and a specificity of 100%. The parallel architecture shows up to an 85.88% reduction in the convergence time for non-invasive FECG databases while the series architecture shows a 27.41% reduction in the number of flip flops used when compared with the existing FPGA implementations of various FECG extraction methods. It also shows an increase of 2–7.51% in accuracy when compared to previous works.

Design of Low Power C Element Based Dual Data Rate Flip Flip

Fulfillment of dual edge flip-flops gets freshly develops into the goal of countless exploration to sustain expressive accomplishment of digital schemes while compressing power expenditure. Powerful low-power flip-flops acquire absolute basic district elements Gross sudden width of histrionic organizes successive circumferences / circuits. Conclude individually and remarkable testing as long as their vulnerability, Q-Delay, Rise Time Path, Fall Time Path and Average Power Consumption. While Power reveals smart effective count regarding the latest electrifying circuit transistors, uncertainly we survive balancing, including scheming comic numbers such as transistors that suspense each number of flip-flops. Analysis / inquiry on static / stable circuits is performed by Dual Data Rate (DDR) using PTM CMOS-16 nm technology alongside 5MHZ frequencies, including their victory procedure. Sensational Dual Data Rate (DDR) Flip-Flop uses 30% less capacity / power, including 14% lower C-Q delay. This paper's proposed architecture is to analyze logic size, area, and power consumption using tanner tool.

Dynamic signal driving strategy based high speed and low powered dual edge triggered flip flop design used memory applications

Power utilization assumes a massive part in any of the integrated circuits, and it’s rundown as a standout amongst essential difficulties in the universal innovation guide into semiconductors. Generally in integrated circuit, flip-flop and clock distribution system consume a lot of energy since they make and utilize the most extreme number of internal transitions. In the clock distribution system, the clock signal circulates from a typical point to every one of the components that required for the circuit. However this capacity is more important to the synchronous framework, much consideration needs to provide for the attributes of these clock signals. In the sequential circuits, a clock distribution system spends a lot of power given the high operating frequency of high capacitance. An existing approach to reducing the limits of a clock signal is based on the quantity of clocked transistors. In this, an advanced procedure is proposed and evaluated by utilizing Dual-Edge Triggered Flip-Flop (DETFF) depends on the Dynamic Signal Driving (DSD) strategy. This DETFF is executed in sequential circuits that have been ordered using Tanner Electronic Design Automation (EDA) tool which is used to simulate and examine control by using Dynamic Signal Driving (DSD) strategy. The outcomes demonstrate that the total power utilization is decreased in sequential benchmark circuit design. A number of Flip flops have been designed by various technologies such as reducing area, delay, and power, but this proposed dynamic signal driving scheme can be used for any integrated circuit- that can be reduced to all these three parameters to give the best trade-off for a particular ASIC platform.

Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops

In advanced technology nodes, bias temperature instability (BTI) has emerged as a prominent reliability concern. The worst-case effects of BTI occur during specific workload phases in which flip-flops (FFs) on a critical path do not switch their logic values for a long duration. These inactive FFs in the circuit experience accelerated workload-dependent static-BTI (S-BTI) stress. The aging effect of S-BTI for a few hours has been shown to be equivalent to one year of aging due to dynamic BTI, which can eventually cause circuit failure. The techniques available to mitigate S-BTI stress during standby mode of circuits are pessimistic, thereby limiting the performance of the circuit. To address this problem, we propose a runtime monitoring method to raise a flag when a timing-critical FF experiences severe S-BTI stress. To reduce the monitoring costs, we select a small representative set of FFs offline based on workload-aware correlation analysis and these selected FFs are monitored online for static aging phases. Our experiments conducted on two processors show that less than 0.5% of the total number of FFs is required to be selected as representative FFs for S-BTI stress monitoring. We also propose a low-overhead mitigation scheme to relax critical FFs by executing a software subroutine that is designed to exercise critical FFs.

A Novel HBE-MCM-Based Multiplier Architecture for 8-Point DCT Structure

The Discrete Cosine Transform (DCT) structure plays a significant role in the signal processing applications such as image and video processing applications. In the traditional hardware design, the 8-point DCT architecture contains more number of logical slices in it. Also, it consists of number of multipliers to update the weight. This leads to huge area consumption and power dissipation in that architecture. To mitigate the conventional drawbacks, this paper presents a novel Hierarchical-based Expression (HBE)-Multiple Constant Multiplication (MCM)-based multiplier architecture design for the 8-point DCT structure used in the video CODEC applications. The proposed work involves modified data path architecture and Floating Point Processing Element (FPPE) architecture. Our proposed design of the multipliers and DCT architecture requires minimum number of components when compared to the traditional DCT method. The HBE-MCM-based multiplier architecture includes shifters and adders. The number of Flip-Flops (FFs) and Look Up Tables (LUTs) used in the proposed architecture is reduced. The power consumption is reduced due to the reduction in the size of the components. This design is synthesized in VERILOG code language and implemented in the Field Programmable Gate Array (FPGA). The performance of the proposed architecture is evaluated by comparing it with traditional DCT architecture in terms of the Number of FFs, Number of LUTs, area, power, delay and speed.

Physical Aware Approaches for Speeding up Scan Shift Operation in SoC

System-on-Chip (SoC) designs have a number of flipflops and it requires a long scan test application time. Scan shift operation takes a significant portion of scan test application time. This paper presents physical aware approaches for speeding up a scan shift operation in SoC. To improve scan shift operation speed, we propose a layout aware flip-flop insertion and scan shift test aware physical implementation procedure. The proposed method effectively improves scan shift speed. The static timing analysis results from state-of-the-art SoC designs show that the scan shift operation is 4.1 times faster than the conventional method. The faster scan shift operation helps to shorten the scan test application time, and reduces test cost.

A P-N Sequence Generator Using LFSR with Dual Edge Trigger Technique

This paper represents the design and implementation of a low power 4-bit LFSR using Dual edge triggered flip flop. A linear feedback shift register (LFSR) is assembled by N number of flip flops connected in series and a combinational logic generally xor gate. An LFSR can generate random number sequence which acts as cipher in cryptography. A known text encrypted over long PN sequence, in order to improve security sequence made longer ie 128 bit; require long chain of flip flop leads to more power consumption. In this paper a novel circuit of random sequence generator using dual edge triggered flip flop has been proposed. Data has been generated on every edge of flip flop instead of single edge. A DETFF-LFSR can generate random number require with less number of clock cycle, it minimizes the number of flip flop result in power saving. In this paper we concentrates on the designing of power competent Test Pattern Generator (TPG) using four dual edge triggered flip-flops as the basic building block, overall there is reduction of power around 25% by using these techniques.

FPGA Implementation of Double Precision Floating Point Arithmetic Unit

Every computer has a floating point processor or a dedicated accelerator that fulfils the requirements of precision using detailed floating point arithmetic. The main applications of floating points today are in the field of medical imaging, biometrics, motion capture and audio applications, including broadcast, conferencing, musical instruments and professional audio. Floating point representation can support a much wider range of values than fixed point representation. In this design the complex logic operations which consist of various multiple numbers of stages are converted into single stage implementation. Once the inputs are applied to the input terminals the final output is obtained at the output terminals there are no intermediate stages. So now the input take less time to reach at output due to single stage implementation and the number of flip flops and other intermediate required circuits are less as a result the area require is less in the presented design called high throughput design. All four individual units addition, subtraction, multiplication and division are designed using Verilog and than combined into one single unit. The code is dumped into low cost Spartan 6 FPGA.

An Effective Bidirectional Network on Chip with Pipelining and Self Reconfigurable Channel

The Bidirectional Network on Chip (Bi-NoC) architecture is more efficient than the conventional architecture because in conventional architecture the unidirectional flow is used where as in Bi-NoC the two way data flow can be performed. The XY routing algorithm is used to perform the architecture. The Bi-NoC architecture allows each channel to transmit in all direction and increases the bandwidth, reduces the access latency and reduces power consumption. The pipelining architecture is used in this study instead of parallel architecture because this performs the reduction in size of the architecture with better result. Also it produces better transmission in the router with reduced traffic and also has less amount of access latency which enhances the performance through better resource utilization. In this proposed method the number of flip flops reduced by 35.9% and the access latency is reduced by 18.9% when compared to existing method.

A Chaotic Time-Delay Sampled-Data System and Its Implementation

Chaotic time-delay systems are attractive candidates to generate chaotic dynamics because of their relatively simple system model. The circuit realization of the time-delay part is the main drawback of these systems. In order to overcome this drawback, a chaotic time-delay system which features a binary feedback function is presented. The use of binary feedback function results in a considerably simplified implementation of the time-delay unit based on using a flip-flop chain. Modeling the system thus obtained yields a chaotic sampled-data system. The existence of chaotic dynamics in the introduced sampled-data systems is numerically verified by calculating system Lyapunov exponents and applying a detailed bifurcation analysis. The chaotic attractor of the introduced sampled-data system is verified by the circuit realization of the system. In order to minimize the number of flip-flops in the chain while keeping the system in chaos, the spectrum of Lyapunov exponent versus clock frequency of the flip-flops and a bifurcation parameter is computed. The circuit realization of the introduced sampled-data system includes a relatively simple structure compared to other chaotic time-delay systems and this overcomes the complexity of the circuit implementation of the time-delay block.

A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm

In this paper, we present an efficient distributed-arithmetic (DA) formulation for the implementation of block least mean square (BLMS) algorithm. The proposed DA-based design uses a novel look-up table (LUT)-sharing technique for the computation of filter outputs and weight-increment terms of BLMS algorithm. Besides, it offers significant saving of adders which constitute a major component of DA-based structures. Also, we have suggested a novel LUT-based weight updating scheme for BLMS algorithm, where only one set of LUTs out of M sets need to be modified in every iteration, where N=ML, N, and L are, respectively, the filter length and input block-size. Based on the proposed DA formulation, we have derived a parallel architecture for the implementation of BLMS adaptive digital filter (ADF). Compared with the best of the existing DA-based LMS structures, proposed one involves nearly L/6 times adders and L times LUT words, and offers nearly L times throughput of the other. It requires nearly 25% more flip-flops and does not involve variable shifters like those of existing structures. It involves less LUT access per output (LAPO) than the existing structure for block-size higher than 4. For block-size 8 and filter length 64, the proposed structure involves 2.47 times more adders, 15% more flip-flops, 43% less LAPO than the best of existing structures, and offers 5.22 times higher throughput. The number of adders of the proposed structure does not increase proportionately with block size; and the number of flip-flops is independent of block-size. This is a major advantage of the proposed structure for reducing its area delay product (ADP); particularly, when a large order ADF is implemented for higher block-sizes. ASIC synthesis result shows that, the proposed structure for filter length 64, has almost 14% and 30% less ADP and 25% and 37% less EPO than the best of the existing structures for block size 4 and 8, respectively.

An all-optical architecture of serial to parallel converter by using Kerr type of non-linear material

Optics is a strong and potential candidate in the field of both communication and data processing because of its several inherent advantages. In digital communication the conversion of serial to parallel and parallel to serial data is very much essential for adopting some special modulation. In this communication the authors propose a new concept of developing an all-optical converter which converts a serial data to parallel one. For this purpose the authors use several optical logic gates specifically AND, NOT, NAND gates. Also an optical memory (Flip-Flop) circuit is used to do the processing. As it is known that, one Flip-Flop is required to store only one bit, hence, the number of Flip-Flops will be equal to the number of required data to be converted. Here, a two bit serial data is converted to the two bit parallel data and then the scheme is generalized for converting n bit serial data to parallel one. The main advantage of the scheme is that, it gives a super-fast processing speed which can be used in optical communication as well as in computation.

Partial bist insertion to eliminate data correlation

A new partial BIST insertion approach based on eliminating data correlation to improve pseudo-random testability is presented. Data correlation causes the circuit to be in a subset of the states more or less frequently, which leads to low fault coverage in pseudo-random test. One important cause of correlation is reconvergent fanout. Incorporating BIST test flip-flops into reconvergent paths will break correlation, however, breaking all reconvergent fanout is unnecessary since some reconvergent fanout results in negligible correlation. We introduce a metric to determine the degree of correlation caused by a set of reconvergent fanout paths. We use this metric to identify problematic reconvergent fanout which must be broken through partial BIST insertion. We provide an algorithm to break high correlation reconvergent paths. Our algorithm provides high fault coverage while selecting fewer BIST flip-flops than required using loop breaking techniques. Experimental results produced using our algorithm rank on average among the top 11.6% of all possible solutions with the same number of flip-flops.

AQUILA: an equivalence checking system for large sequential designs

In this paper, we present a practical method for verifying the functional equivalence of two synchronous sequential designs. This tool is based on our earlier framework that uses Automatic Test Pattern Generation (ATPG) techniques for verification. By exploring the structural similarity between the two designs under verification, the complexity can be reduced substantially. We enhance our framework by three innovative features. First, we develop a local BDD-based technique which constructs Binary Decision Diagram (BDD) in terms of some internal signals, for identifying equivalent signal pairs. Second, we incorporate a technique called partial justification to explore not only combinational similarity, but also sequential similarity. This is particularly important when the two designs have a different number of flip-flops. Third, we extend our gate-to-gate equivalence checker for RTL-to-gate verification. Two major issues are considered in this extension: (1) how to model and utilize the external don't care information for verification; and (2) how to extract a subset of unreachable states to speed up the verification process. Compared with existing approaches based on symbolic Finite State Machine (FSM) traversal techniques, our approach is less vulnerable to the memory explosion problem and, therefore, is more suitable for a lot of real-life designs. Experimental results of verifying designs with hundreds of flip-flops will be presented to demonstrate the effectiveness of this approach.

Testing and testable designs for one-time programmable FPGAs

We present a methodology for production-time testing of one-time programmable field programmable gate arrays (FPGAs) such as those manufactured by Actel. The methodological principles are based on connecting the uncommitted modules (sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays, similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions for constant testability (C testability). Two design approaches are proposed. Features such as testing time and hardware requirements (measured by the number of cycles and additional transistors and primary input-output pins) are analyzed. We show that the proposed designs require considerably less testing time than a previous technique based on scan. The proposed approaches require 8+n/sub f/ vectors for testing the Actel FPGAs, where n/sub f/ is the number of flip-flops in a row. Hardware overhead for the testing circuitry is also analyzed.

Deterministic BIST with Partial Scan

An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.

Synthesis of Sequential Circuits by Redundancy Removal and Retiming

In this paper we propose a method for synthesizing sequential circuits to reduce the number of gates and flip-flops by removing both combinationally and sequentially redundant faults. In order to remove sequentially redundant faults these faults are converted into combinationally redundant faults by using retiming techniques and the combinationally redundant faults can be removed by using a test pattern generation method for combinational circuits. To simplify a given circuit retiming is utilized for two purposes in this method. One is to find sequentially redundant faults and another is to reduce the number of flip-flops and gates. Before and after each retiming the combinationally redundant faults are removed. Experimental results for ISCAS ‘89 benchmark circuits show that this method can remove many of sequentially redundant faults and can reduce a large number of gates and flip-flops.

Retiming-based partial scan

A generally effective criterion for the selection of flip-flops in the partial scan problem for sequential circuit testability is to select flip-flops that break the cyclic structure of the circuit and reduce its sequential depth. The selection of flip-flops may also be subject to a prescribed bound on the clock period of the modified circuit (timing-driven partial scan). In this paper we propose two techniques (for non-timing-driven and timing-driven partial scan) which address the above criterion based on a transformation of sequential circuits known as retiming. For non-timing-driven partial scan, we employ retiming to rearrange the flip-flops of the circuit, so that its functionality is preserved, while the number of flip-flops that are needed to break all cycles and bound the sequential depth is significantly reduced. For timing-driven partial scan, we propose a retiming-based technique that reduces the overall area overhead required to achieve the clock period bound. Experimental results on the ISCAS'89 circuits show the benefit of our approach in both timing-driven and non-timing-driven partial scan.