NPN Devices Research Articles

Broadband mid-infrared photodetectors utilizing two-dimensional van der Waals heterostructures with parallel-stacked pn junctions

Optimizing the width of depletion region is a key consideration in designing high performance photovoltaic photodetectors, as the electron-hole pairs generated outside the depletion region cannot be effectively separated, leading to a negligible contribution to the overall photocurrent. However, currently reported photovoltaic mid-infrared photodetectors based on two-dimensional heterostructures usually adopt a single pn junction configuration, where the depletion region width is not maximally optimized. Here, we demonstrate the construction of a high performance broadband mid-infrared photodetector based on a MoS2/b-AsP/MoS2 npn van der Waals heterostructure. The npn heterojunction can be equivalently represented as two parallel-stacked pn junctions, effectively increasing the thickness of the depletion region. Consequently, the npn device shows a high detectivity of 1.3 × 1010 cmHz1/2W−1 at the mid-infrared wavelength, which is significantly improved compared with its single pn junction counterpart. Moreover, it exhibits a fast response speed of 12 μs, and a broadband detection capability ranging from visible to mid-infrared wavelengths.

A unified aging compact model for hot carrier degradation under mixed-mode and reverse E-B stress in complementary SiGe HBTs

This paper presents an accurate, comprehensive and physics-based aging compact model for stress-induced degradation due to hot-carrier generation and oxide trapping in advanced complementary NPN and PNP SiGe HBTs. The analytical model equations are derived from the solution of reaction–diffusion theory and Fick’s law of diffusion combined with oxide trapping mechanism under accelerated stress conditions. The model accuracy has been validated against results from long-term aging tests performed close to the safe-operating-areas of an advanced complementary 0.25 µm BiCMOS technology. Degradation asymmetry observed between NPN and PNP devices is accurately captured by this unified aging compact model. This study highlights the challenges of predicting degradation of complementary circuits and thereby improving its functionalities by designing better-matched NPN and PNP HBTs.

Parasitic NPN and PNP Latch-Up Within a Single DMOS for High Voltage Reliability

This article discusses the robustness of field-plate-assisted reduced surface field effect (RESURF) DMOS designs to time-dependent latch-up within a single dielectrically isolated device. This work individually characterizes the dopant defined parasitic bipolar parallel to all MOS and uniquely describes the existence of another parasitic bipolar of opposite polarity through the generation of a backgate current as a result of weak impact ionization. These two NPN and PNP bipolar devices in a single DMOS device complete the latch-up mechanism once the product of their gains is greater than one. The characterized time-dependent nature of the increasing backgate current is accounted for by oxide charge trapping in the extended drain region, where measurements of this mechanism over a broad range of application and manufacturing variables enable a mathematical model for the time to failure to be described. Finally, the advantage of analyzing DMOS latch-up robustness in the context of individual parasitic NPN and PNP bipolar devices is shown by its ability to isolate out the separate variables feeding into each bipolar to implement robust solutions.

A 10 GHz inductorless active SiGe HBT lowpass filter

High-frequency (around 10 GHz) filters are necessary for many applications, in anti-aliasing filters for high-speed data converters or optical communications. Modern SiGe technology allows implementing radio-frequency circuits up to about 100 GHz. At the lower frequencies around 10 GHz, the size of passive components is a concern, and inductorless designs are used. We present a topology for an inductorless lowpass biquad filter capable of operating at 10 GHz or more in the STMicroelectronics BiCMOS55 process. The filter is simulated considering temperature, process, biasing and mismatch variations, tested with parametric and Monte Carlo simulations. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage has good dynamic range (45 dB) and power efficiency (0.65 pW/Hz/pole) with respect to comparable active lowpass filters reported in the literature, and, unlike other filters, only uses NPN devices, which are the only high-speed devices available in many Hybrid Bipolar Transistor (HBT) technologies.

A Comparative Study of InGaP/GaAs Collector-Up HBTs for High-Reliability Small-Scale PA Applications

In this paper, the characteristics of InGaP/GaAs collector-up (C-up) pnp and npn heterojunction bipolar transistors (HBTs) with the graded InGaAs base and the nonuniform doped collector are demonstrated, and the performances as well as the reliability of the novel HBTs have been compared with the conventional InGaP/GaAs HBTs with various collector structures and thermal schemes. Compared to conventional HBTs, the studied C-up HBTs exhibited better current-driving capability, higher RF efficiency, and improved long-term reliability. Note that the pnp device displayed greater thermal stability enhancements, which are distinct and reproducible, than the npn device. The favorable data of the pnp C-up HBT could be attributed to higher electron mobility, resulting in low base resistance and higher emitter resistance improving the thermal stability. The comparison results, based on pragmatic observations from the C-up HBTs without relatively large heat-dissipation configurations, should be very useful for the reliable and the cost-effective design as small-scale power amplifiers in the wideband CDMA system.

Investigation and application of vertical NPN devices for RF ESD protection in BiCMOS technology

BiCMOS technologies have been used to implement the radio-frequency (RF) integrated circuits (ICs) due to the advantages of low noise, low power consumption, high drive, and high speed. The electrostatic discharge (ESD) is one of the important reliability issues of IC. When the ESD events happen, the ESD protection devices must be turned on immediately to protect the ICs, including the RF ICs in BiCMOS technologies. In this work, the vertical NPN (VNPN) devices in 0.18μm silicon-germanium (SiGe) BiCMOS technology with base-emitter shorted and resistor trigger approaches are investigated. In component-level, using transmission-line-pulsing (TLP) and ESD simulator test the IV characteristics and human-body-model (HBM) robustness of the VNPN devices, respectively. In system-level, using ESD gun tests the system-level ESD robustness. The ESD protection of VNPN devices are further applied to a 2.4GHz low-noise amplifier (LNA). After attaching the VNPN devices to LNA, the RF characteristics are not degraded while the ESD robustness can be much improved.

A Perspective on Symmetric Lateral Bipolar Transistors on SOI as a Complementary Bipolar Logic Technology

Recently published reports suggest that symmetric lateral bipolar transistors on semiconductor-on-insulator (SOI) is CMOS compatible in fabrication process, and can be much denser than CMOS due to their much larger (5-10× larger) drive-current capability. When used in traditional bipolar circuits, SOI bipolar offers much lower power dissipation and/or much higher maximum speed. With both NPN and PNP devices of comparable characteristics, SOI lateral bipolar suggests the possibility of complementary bipolar (CBipolar) circuits in configurations analogous to CMOS. In this paper, the performance versus power dissipation of CBipolar circuits is examined using analytic equations. It is shown that for CBipolar to be superior to CMOS in both performance and power dissipation, narrow-gap-base heterojunction structures, such as Si emitter with Ge base or Si emitter with SiGe base, are required.

Predicted performance of Ge/GeSn hetero-phototransistors on Si substrate at $$1.55\,\upmu \mathrm{m}$$ 1.55 μ m

Alloys of Ge and Sn grown on Si platform show about tenfold increase in the absorption over Ge at C and L-bands due to the direct nature of the band gap in GeSn. This led us to propose a Ge/GeSn/GeSn heterophototransistor (HPT) structure on a Si-platform and to calculate the terminal currents, current gain, optical gain and responsivity of the device at $$1.55\,\upmu \mathrm{m}$$ . The model developed by Frimel and Roenker for HPTs with InGaAs base is used. In the model, the carrier density in the base is obtained by matching the diffusion-limited current with the current due to thermionic emission and tunneling across the emitter-base heterobarrier, and also considering the carrier density at the collector-end limited by the saturation drift velocity. The contribution of holes to the current is also included. The resulting carrier distribution is used to express the terminal currents and calculate the values of gain. The band gap for GeSn and the band discontinuity in the heterobarrier are calculated by using model solid theory. The calculated values for the GeSn HPT are found to be comparable with and even better than the corresponding values for the InP/InGaAs/InGaAs Npn device for lower values of the base thickness and the base doping.

Improved Frequency Response in a SiGe npn Device through Improved Dopant Activation

We study the impact of improved dopant activation in a BiCMOS SiGe technology, using laser annealing to improve activation, and a low temperature contact module to avoid de-activation. We present the results of simple DC test structure measurements and high frequency bipolar transistor measurements. Improved activation significantly reduces sheet resistance, particularly for polysilicon layers. Likewise, reductions in the bipolar device resistance parasitics cause an improvement in maximum power gain frequency (fMAX).

Improved Frequency Response in a SiGe npn Device through Improved Dopant Activation

not Available.

A Monolithic MEMS Accelerometer Process

A monolithic MEMS accelerometer process was established. This process successfully combines our standard BiCMOS technology and MEMS surface micromachining technique. The acceleration sensing element is a kind of comb-finger structure which is built by polysilicon surface micromachining technique. The polysilicon structure is designed to form two capacitors for acceleration sensing. The external acceleration will cause the value of two capacitors to vary in different direction. That means one reduces if the other increases. It was integrated with the signal conditioning circuit. In a single die, the active devices including vertical NPN, lateral PNP, PMOS and passive devices such as capacitors, resistors were fabricated which was followed by the steps to form the acceleration sensing structure. The experiment indicates that the fabricated circuit has the function of sensing capacitive variation and with a scale factor of 100mV/g.

High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches

A 0.25 µm SiGe:C BiCMOS technology family (SG25H) with high-speed npn and pnp transistors for different performance requirements is presented. A CMOS-friendly integration scheme is realized by using collector wells, implanted after shallow trench formation, and avoiding deep trenches and extra collector sinkers. Three process variants are offered. The key bipolar transistor of the SG25H1 process is a 200 GHz npn device. The SG25H3 process offers three different types of npn HBTs. The performance ranges from fT/fmax /BVCEo values of 110 GHz/180 GHz/2.3 V for the high-speed (HS) device to 50 GHz/140 GHz/4.5 V for the medium voltage (MV) device and 30 GHz/80 GHz/6.5 V for the high-voltage (HV) transistor. The SG25H2 process provides in addition to npn transistors similar to those of SG25H1 and H3 a very high-speed SiGe:C pnp HBT with fT/fmax/BVCEo values of 90 GHz/120 GHz/2.8 V.

A study of relation between a power supply ESD and parasitic capacitance

In this study, we show that increased parasitic capacitance across lateral NPN (LNPN) devices does not necessarily enhance the electro-static discharge (ESD) robustness. Since the drain-bulk displacement current decreases, the LNPN avalanche trigger current increases and the PN junctions fail early. In our case, this happened when the parasitic capacitance between supply lines is around several hundreds of Pico-Farads.

Optimisation of Heterostructure Bipolar Transistors in SiC

We present the results of a simulation study on the behaviour of 3C-SiC bipolar transistors fabricated using a 6H-SiC heterojunction emitter. We show that despite the potential barrier originating in the discontinuity of the conduction bands, that npn devices offer a higher common emitter gain in comparison to pnp devices. The base voltage corresponding to the maximum gain of the device is controlled by the tunnelling of carriers across the collector-base junction and is different for both npn and pnp devices.

0.25 micrometre smart power technology optimised for wireless and consumer applications

In this paper simultaneous optimization of 4.5-5.5V N and PMOS devices, 20-30V NLDMOS and NPN and PNP bipolar devices in a 0.25 /spl mu/m Smart Power Technology for portable wireless and consumer applications is discussed. With the addition of two designated wells, ultra-low resistance N and PMOS devices with good analog characteristics, best in class 30V NLDMOS as well as integrated high performance NPN and PNP bipolar devices is demonstrated.

A comparison of low-frequency noise characteristics and noise sources in NPN and PNP InP-based heterojunction bipolar transistors

Low-frequency noise characteristics of NPN and PNP InP-based heterojunction bipolar transistors (HBTs) were investigated. NPN HBTs showed a lower base noise current level (3.85 /spl times/ 10/sup -17/ A/sup 2//Hz) than PNP HBTs (3.10 /spl times/ 10/sup -16/ A/sup 2//Hz), but higher collector noise current level (7.16 /spl times/ 10/sup -16/ A/sup 2//Hz) than PNP HBTs (1.48 /spl times/ 10/sup -16/ A/sup 2//Hz) at 10 Hz under I/sub C/=1 mA, V/sub C/=1 V. The NPN devices showed a weak dependence I/sub C//sup 0.77/ of the collector noise current, and a dependence I/sub B//sup 1.18/ of the base noise current, while the PNP devices showed dependences I/sub C//sup 1.92/ and I/sub B//sup 1.54/, respectively. The dominant noise sources and relative intrinsic noise strength were found in both NPN and PNP InP-based HBTs by comparing the noise spectral density with and without the emitter feedback resistor. Equivalent circuit models were employed and intrinsic noise sources were extracted. The high base noise current of PNP HBTs could be attributed to the exposed emitter periphery and higher electron surface recombination velocity in P-type InP materials, while the relatively high collector noise current of NPN HBTs may be due to the noise source originating from generation-recombination process in the bulk material between the emitter and the collector.

Technology and First Electrical Characteristics of Complementary NPN and PNP InAlAs/InGaAs Heterojunction Bipolar Transistors

A selective molecular beam epitaxy (MBE) regrowth approach is presented and applied in the demonstration of complementary InP heterojunction bipolar transistor (HBT) technology for monolithic integration of NPN and PNP HBTs. State-of-art performance has been observed: The DC gain was 35 for both integrated NPN and PNP HBTs. fT of 79.6 GHz and fmax of 109 GHz were achieved for NPN devices while fT of 11.6 GHz and fmax of 22.6 GHz were achieved for PNP devices. Little performance degradation has been observed compared with same design NPN or PNP HBT layers grown on individual substrates. Monolithic microwave integrated circuits (MMICs) based on complementary InP HBT technology have been studied for the first time using this technology and their electrical characteristics are presented.

Simulation of npn and pnp AlGaN/GaN heterojunction bipolar transistors performances: limiting factors and optimum design

The performance capabilities of npn and pnp AlGaN/GaN heterojunction bipolar transistors have been investigated by using a drift-diffusion transport model. Numerical results have been employed to study the effect of the p-type Mg doping and its incomplete ionization on device performance. The high base resistance induced by the deep acceptor level is found to be one of the causes of limited current gain values for npn devices. Reasonable improvements of the dc current gain /spl beta/ are observed by realistically reducing the base thickness and consequently the transit time, in accordance with processing limitations. Base transport enhancement is predicted by the introduction of a quasi-electric field in the base. The impact of the base resistivity on high-frequency characteristics is investigated for npn AlGaN/GaN devices. Simulation results reveal the difficulty to achieve decent current gain values at high current density for pnp HBTs in common emitter configuration. Despite the high electron mobility in the n-type base that aids in reducing the base resistance, a preliminary analysis for pnp devices indicates limited rf performances caused by the reduced minority hole transport across the base.

A comparison of npn and pnp profile design tradeoffs for complementary SiGe HBT Technology

A comprehensive comparison of npn and pnp profile design tradeoffs for SiGe HBTs is conducted using calibrated simulations. The parasitic energy band barrier induced by the SiGe/Si transition in the collector–base space charge region produces very different design constraints for pnp and npn transistors, and they must be optimized separately. A single SiGe profile is found to give acceptable performance for both npn and pnp devices, while still satisfying film stability constraints.

Simulation of GaN/AlGaN heterojunction bipolar transistors: part II – pnp structures

The dc characteristics of pnp GaN/AlGaN heterojunction bipolar transistors are simulated using a quasi-3D-model. The effects of base doping and thickness, contact geometry and device operating temperature on dc current gain have been examined. Maximum gains of ∼50 are expected for high quality materials and an optimized layer design. For similar layer thicknesses, npn devices have higher gains than the pnp structures, but the latter does not suffer from a high base sheet resistance.