Non-volatile Memory Technologies Research Articles

Progress of emerging non-volatile memory technologies in industry

Progress of emerging non-volatile memory technologies in industry

The structure and formation of non-volatile memory cells of Superflash

Split-gate embedded Flash memory technology has been around for decades and has become the standard for a wide range of devices, such as microcontrollers and smart cards. Among the, due to a number of advantages, Silicon Storage Technology Super Flash non-volatile memory technology has become the most widespread. This article presents the results of a study of the memory cells structure, examines in detail the principle of their operation and the main technological stages of the production process of forming transistor structures.

Emerging non-volatile memory (NVM) technologies based nano-oscillators: Materials to applications

This comprehensive study provides a detailed review toward ongoing research on emerging non-volatile memory technologies based nano-oscillators, i.e., from the perspective of materials to applications. Depending on the materials used to fabricate them, the whole class of emerging nano-oscillators has been broadly classified into two categories: (i) electronic and (ii) spintronic oscillators. Moreover, various material-compositions explored for fabricating the oscillatory devices, their physical properties responsible for generating the oscillations, and device architectures are thoroughly reviewed. Furthermore, various advanced computing applications (i.e., realized through these oscillatory devices), such as Internet of Things, neuro-inspired computing, and sensing, are also studied and their key attributes are highlighted.

Materials, Processes, Devices and Applications of Magnetoresistive Random Access Memory

Abstract Magnetoresistive random access memory (MRAM) is a promising non-volatile memory technology that can be utilized as an energy and space-efficient storage and computing solution, particularly in cache functions within circuits. Although MRAM has achieved mass production, its manufacturing process still remains challenging, resulting in only a few semiconductor companies dominating its production. In this review, we delve into the materials, processes, and devices used in MRAM, focusing on both the widely adopted spin transfer torque (STT) MRAM and the next-generation spin-orbit torque (SOT) MRAM. We provide an overview of their operational mechanisms and manufacturing technologies. Furthermore, we outline the major hurdles faced in MRAM manufacturing and propose potential solutions in detail. Then, the applications of MRAM in artificial intelligent hardware is introduced. Finally, we present an outlook on the future development and applications of MRAM.

Exploring charge transfer and schottky barrier modulation at monolayer Ge2Sb2Te5-metal interfaces

Monolayer Ge2Sb2Te5exhibits great potential in non-volatile memory technology due to its excellent electronic properties and phase-change characteristics, while the fundamental nature of Ge2Sb2Te5-metal contacts has not been well understood yet. Here, we provide a comprehensiveab initiostudy of the electronic properties between monolayer Ge2Sb2Te5and Pt, Pd, Au, Cu, Cr, Ag, and W contacts based on first-principles calculations. We find that the strong interaction interfaces formed between monolayer Ge2Sb2Te5and Pt, Pd, Cr, and W contacts show chemical bonding and strong charge transfer. In contrast, no apparent chemical bonding and weak charge transfer are observed in the weak interaction interfaces formed with Au, Cu, and Ag. Additionally, our study reveals the presence of a pronounced Fermi level pinning effect between monolayer Ge2Sb2Te5and metals, with pinning factors ofSn=0.325andSp=0.350. By increasing the interlayer distance, an effective transition fromn-type Ohmic contact ton-type Schottky contact is facilitated because the band edge of Ge2Sb2Te5is shifted upwards. Our study not only provides a theoretical basis for selecting suitable metal electrodes in Ge2Sb2Te5-based devices but also holds significant implications for understanding Schottky barrier height modulation between semiconductors and metals.

Non-Volatile Memory Technology Poised for Game-Changing Breakthrough

Why novel nanocomposite-superlattices for low-energy, high-stability nanoscale phase-change memory is poised as an innovation touchstone for the memory segment and the entire industrial ecosystem.

Influence of HfO2 oxide layer on crystallization properties of In3SbTe2 phase change material

Phase Change Memory (PCM) represents a potential paradigm in the realm of non-volatile memory technologies, and several phase change materials are studied for utilization in PCM devices. This work employs a less explored In3SbTe2 (IST) phase change material (active layer) integrated with an oxide (HfO2) layer and investigates the influence of the oxide layer on the active layer. The oxide layer remains amorphous when annealed at 400 °C, and it doesn’t alter the crystallization temperature (290 °C) of the active layer in IST with HfO2 thin-film. However, after crystallization, the grain size of the active layer is reduced to ∼8.23 nm in IST with HfO2 thin-film, compared to only IST thin-film. XPS core-level spectra (In 3d, Sb 3d, Te 3d) of IST active layer reveal the peak shifting towards higher binding energy at 300 °C and 400 °C annealed films, implying bond energy increase with crystallization and film stability improves. The Hf or O atoms of the oxide layer don’t diffuse into the active layer with annealing, suggesting no interference with the phase switching property of IST. A higher optical bandgap of 1.154 eV in as-deposited IST with HfO2 thin-film compared to the only IST thin-film illustrates better stability of the amorphous state in the film with the oxide layer. In addition, the fabricated PCM device using the IST with the oxide layer demonstrates phase switching at a lower threshold voltage of (2.1 ± 0.1) V, compared to the IST-based device. The findings indicate that the enhanced structural and electrical switching characteristics of IST phase change layer coupled with an oxide layer make it beneficial for data storage PCM applications.

A verified durable transactional mutex lock for persistent x86-TSO

AbstractThe advent of non-volatile memory technologies has spurred intensive research interest in correctness and programmability. This paper addresses both by developing and verifying a durable (aka persistent) transactional memory (TM) algorithm, $$\text {dTML}_{\text {Px86}}$$ dTML Px86 . Correctness of $$\text {dTML}_{\text {Px86}}$$ dTML Px86 is judged in terms of durable opacity, which ensures both failure atomicity (ensuring memory consistency after a crash) and opacity (ensuring thread safety). We assume a realistic execution model, Px86, which represents Intel’s persistent memory model and extends the Total Store Order memory model with instructions that control persistency. Our TM algorithm, $$\text {dTML}_{\text {Px86}}$$ dTML Px86 , is an adaptation of an existing software transactional mutex lock, but with additional synchronisation mechanisms to cope with Px86. Our correctness proof is operational and comprises two distinct types of proofs: (1) proofs of invariants of $$\text {dTML}_{\text {Px86}}$$ dTML Px86 and (2) a proof of refinement against an operational specification that guarantees durable opacity. To achieve (1), we build on recent Owicki–Gries logics for Px86, and for (2) we use a simulation-based proof technique, which, as far as we are aware, is the first application of simulation-based proofs for Px86 programs. Our entire development has been mechanised in the Isabelle/HOL proof assistant.

Tunable magnetic synapse for reliable neuromorphic computing

Artificial neural networks (ANNs), inspired by the structure and function of the human brain, have achieved remarkable success in various fields. However, ANNs implemented using conventional complementary metal oxide semiconductor technology face significant limitations. This has prompted exploration of nonvolatile memory technologies as potential solutions to overcome these limitations by integrating storage and computation within a single device. These emerging technologies can retain resistance values without power, allowing them to serve as analog weights in ANNs, mimicking the behavior of biological synapses. While promising, these nonvolatile devices often exhibit inherent nonlinear relationships between resistance and applied voltage, complicating training processes and potentially impacting learning accuracy. This article proposes a magnetic synapse device based on the spin–orbit torque effect with geometrically controlled linear and nonlinear response characteristics. The device consists of a magnetic multilayer stack patterned into a designed shape, where the width variation along the current flow direction allows for controllable magnetic domain wall propagation. Through finite element method simulations and experimental studies, we demonstrate that by engineering the device geometry, a linear relationship between the applied current and the resulting Hall resistance can be achieved, mimicking the desired linear weight-input behavior in artificial neural networks. Additionally, this study explores the influence of current pulse width on the response curves, revealing a deviation from linearity at longer pulse durations. The geometric tunability of the magnetic synapse device offers a promising approach for realizing reliable and energy-efficient neuromorphic computing architectures.

A read-efficient and write-optimized hash table for Intel Optane DC Persistent Memory

Emerging non-volatile memory technologies are driving the next generation of storage systems and durable data structures. Among them, many hash table proposals employ NVM as the storage layer for both fast access and efficient persistence. Most of them are based on the assumption that NVM has cacheline access granularity, poor write endurance, DRAM-comparable read latency and relatively higher write latency. However, a commercial non-volatile memory product, namely Intel Optane DC Persistent Memory (Optane), has some interesting features that are different from previous assumptions, such as 256-byte OptaneLine access granularity, higher read latency than DRAM and DRAM-comparable write latency, limited read/write bandwidth, and hardware-layer wear-leveling. Confronted with the new challenges brought by Optane, we propose Rewo-Hash, a novel read-efficient and write-optimized persistent hash table. Our incremental contributions over our previous work are summarized as follows. First, provide a more detailed technical description for cached table-inclined read mechanism and log-free atomic write mechanism. Second, we devise a consistent shadowing synchronization scheme to mask the data synchronization overhead. Third, we propose a non-blocking lightweight resizing scheme and elaborate the crash recovery mechanism. Fourth, we conduct a comprehensive analysis of the implications of Intel ceasing the production of Optane, and provide a forward-looking perspective on the future of non-volatile memory. The experimental results show that compared with state-of-the-art NVM-Optimized hash tables, Rewo-Hash gains remarkable performance improvement.

Synthesis of tantalum oxide thin films using RF magnetron sputtering for RRAM application

Resistive Random Access Memory (RRAM) is a prominent contender in the realm of emerging non-volatile memory technologies owing to its numerous advantages like simple structure, low power usage, high speed, and exceptional scalability. In the current study, RRAM device was fabricated using tantalum oxide (TaOx) as a resistive switching insulating oxide layer, which was sandwiched between two conducting electrodes, namely Ag and ITO. RF magnetron sputtering was used to deposit the insulating layer of TaOx at room temperature on the ITO substrate. Further, X-ray reflectivity and hard X-ray photoelectron spectroscopy analyses were conducted to find the thickness, roughness, and elemental composition of the deposited TaOx films. Using a semiconductor analyzer, the RRAM cell's first DC switching characteristics were determined. The data acquired exhibited a resistance ratio (R HRS/R LRS) of 120 showing a good distinction between the two-resistance states. Additionally, a thorough investigation was conducted to examine the electrical conduction mechanism occurring inside the fabricated RRAM device.

Memristor In Non-Volatile Memory Technology and Computer Architecture

Memristor In Non-Volatile Memory Technology and Computer Architecture

Ultrafast high-endurance memory based on sliding ferroelectrics.

The persistence of voltage-switchable collective electronic phenomena down to the atomic scale has extensive implications for area- and energy-efficient electronics, especially in emerging nonvolatile memory technology. We investigate the performance of a ferroelectric field-effect transistor (FeFET) based on sliding ferroelectricity in bilayer boron nitride at room temperature. Sliding ferroelectricity represents a different form of atomically thin two-dimensional (2D) ferroelectrics, characterized by the switching of out-of-plane polarization through interlayer sliding motion. We examined the FeFET device employing monolayer graphene as the channel layer, which demonstrated ultrafast switching speeds on the nanosecond scale and high endurance exceeding 1011 switching cycles, comparable to state-of-the-art FeFET devices. These characteristics highlight the potential of 2D sliding ferroelectrics for inspiring next-generation nonvolatile memory technology.

Research on Improved Crystallization Properties and Underlying Mechanism of the Sb2Te3 Phase-Change Thin Film by Inserting Sn15Sb85 Layers.

As a non-volatile semiconductor memory technology, phase-change memory has a wide range of application prospects as a result of the excellent comprehensive performance. In this paper, multilayer thin films based on Sb2Te3 material were designed and prepared by inserting the Sn15Sb85 layer. The thermal and electrical properties of superlattice-like Sb2Te3/Sn15Sb85 phase-change films can be adjusted by controlling the thickness ratio of Sb2Te3/Sn15Sb85. In comparison to the monolayer Sb2Te3 film, the multilayer layer Sb2Te3/Sn15Sb85 materials have a higher crystallization temperature, larger crystallization activation energy, and longer data lifetime, indicating the great improvement of thermal stability. The changes in the phase structure and vibrational modes of multilayer Sb2Te3/Sn15Sb85 films were characterized by X-ray diffraction and Raman spectroscopy, respectively. The presence of Sn15Sb85 layers restrains grain growth and refines the grain size. The multilayer Sb2Te3/Sn15Sb85 films exhibit better surface flatness, smaller surface potential undulation, and lower thickness variations than single-layer Sb2Te3. Phase-change memory cells based on the [Sb2Te3 (1 nm)/Sn15Sb85 (9 nm)]5 thin film has a lower threshold voltage (1.9 V) and threshold current (3.1 μA) compared to the Ge2Sb2Te5 film. Meanwhile, the electrical heating model of a phase-change memory cell based on a [Sb2Te3 (1 nm)/Sn15Sb85 (9 nm)]5 multilayer structure was established by multiphysics coupling analysis, proving the great improvement in heat transfer performance and efficiency. The experimental and theoretical studies confirm that the insertion of the Sn15Sb85 layer can significantly improve the crystallization properties of Sb2Te3 films, paving the way for optimizing the phase-change materials by regulating the microstructural parameters.

A quantum sensing metrology for magnetic memories

Magnetic random access memory (MRAM) is a leading emergent memory technology that is poised to replace current non-volatile memory technologies such as eFlash. However, controlling and improving distributions of device properties becomes a key enabler of new applications at this stage of technology development. Here, we introduce a non-contact metrology technique deploying scanning NV magnetometry (SNVM) to investigate MRAM performance at the individual bit level. We demonstrate magnetic reversal characterization in individual, <60 nm-sized bits, to extract key magnetic properties, thermal stability, and switching statistics, and thereby gauge bit-to-bit uniformity. We showcase the performance of our method by benchmarking two distinct bit etching processes immediately after pattern formation. In contrast to ensemble averaging methods such as perpendicular magneto-optical Kerr effect, we show that it is possible to identify out of distribution (tail-bits) bits that seem associated to the edges of the array, enabling failure analysis of tail bits. Our findings highlight the potential of nanoscale quantum sensing of MRAM devices for early-stage screening in the processing line, paving the way for future incorporation of this nanoscale characterization tool in the semiconductor industry.

Ferro-Electric RAM

Ferroelectric RAM (FRAM) is a promising non-volatile memory technology that combines the advantages of both DRAM and Flash memory. FRAM offers fast read and write speeds, low power consumption, and high endurance, making it suitable for a wide range of applications. It stores data by utilizing the ferroelectric properties of certain materials, which can retain their polarization even when the power is off. This allows FRAM to offer high-speed operation with low power consumption, making it ideal for use in IoT devices, smart cards, and automotive systems

Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers

Large volumes of on-chip and off-chip memory are required by contemporary applications. Emerging non-volatile memory technologies including STT-RAM, PCM, and ReRAM are becoming popular for on-chip and off-chip memories as a result of their desirable properties. Compared to traditional memory technologies such as SRAM and DRAM, they have minimal leakage current and high packing density. Non Volatile Memories (NVM), however, have a low write endurance, a high write latency, and high write energy. Non-volatile Single Level Cell (SLC) memories can store a single bit of data in each memory cell, whereas Multi Level Cells (MLC) can store two or more bits in each memory cell. Although MLC NVMs have substantially higher packing density than SLCs, their lifetime and access speed are key concerns. For a given cache size, MLC caches consume 1.84× less space and 2.62× less leakage power than SLC caches. We propose Trace buffer Assisted Non-volatile Memory Cache (TANC), an approach that increases the lifespan and performance of MLC-based last-level caches using the underutilized Embedded Trace Buffers (ETB). TANC improves the lifetime of MLC LLCs up to 4.36× and decreases average memory access time by 4% compared to SLC NVM LLCs and by 6.41× and 11%, respectively, compared to baseline MLC LLCs.

Stable and repeatable ZrO2 RRAM achieved by NiO barrier layer for negative set phenomenon elimination

Resistive random-access memory (RRAM) is a promising non-volatile memory technology due to its fast operation, low power consumption, and high reliability. However, the negative set phenomenon remains a challenge for RRAM, which can lead to the deterioration of device switching parameters. In this study, we successfully addressed this issue by inserting a NiO blocking layer between the ZrO2 and Ag top electrodes in ZrO2-based RRAM. In addition, the resistive switching characteristics of the device are significantly enhanced by the incorporation of a p-type oxide NiO layer. Compared to single-layer ZrO2 devices, the double-layer Ag/NiO/ZrO2/ITO RRAM exhibits improved cycling durability (>500 cycles) and good retention time (3 × 104s). Our analysis of the device conduction mechanism and proposed resistive switching model suggest that oxygen vacancies play a connecting role in the reset process, leading to failed reset behavior. Through the incorporation of a p-type semiconductor NiO layer into ZrO2-based RRAMs, the interference of oxygen vacancies on the reset process can be effectively impeded. This approach not only provides an effective resolution to the unforeseen negative set phenomenon in RRAM devices, but it also holds paramount significance for the advancement of high-performance RRAMs.

Phase Change Heterostructure Memory with Oxygen-DopedSb2Te3 Layersfor Improved Durability and Reliability through Nano crystalline Island Formation.

Phase-change random access memory represents a notable advancement in nonvolatile memory technology; however, it faces challenges in terms of thermal stability and reliability, hindering its broader application. To mitigate these issues, doping and structural modification techniques such as phase-change heterostructures (PCH) are widely studied. Although doping typically enhances thermal stability, it can adversely affect the switching speed. Structural modifications such as PCH have struggled to sustain stable performance under high atmospheric conditions. In this study, these challenges are addressed by synergizing oxygen-doped Sb2Te3 (OST) with PCH technology. This study presents a novel approach in which OST significantly improves the crystallization temperature, power efficiency, and cyclability. Subsequently, the integration of the PCH technology bolsters the switching speed and further amplifies the device's reliability and endurance by refining the grain size (≈7nm). The resultant OST-PCH devices exhibit exceptional performance metrics, including a drift coefficient of 0.003 in the RESET state, endurance of ≈4 × 108 cycles, an switching speed of 300ns, and 67.6 pJ of RESET energy. These findings suggest that the OST-PCH devices show promise for integration into embedded systems, such as those found in automotive applications and Internet of Things devices.

Phase-change heterostructure with HfTe2 confinement sublayers for enhanced thermal efficiency and low-power operation through Joule heating localization

Although phase-change random-access memory (PCRAM) is a promising next-generation nonvolatile memory technology, challenges remain in terms of reducing energy consumption. This is primarily because the high thermal conductivities of phase-change materials (PCMs) promote Joule heating dissipation. Repeated phase transitions also induce long-range atomic diffusion, limiting the durability. To address these challenges, phase-change heterostructure (PCH) devices that incorporate confinement sublayers based on transition-metal dichalcogenide materials have been developed. In this study, we engineered a PCH device by integrating HfTe2, which has low thermal conductivity and excellent stability, into the PCM to realize PCRAM with enhanced thermal efficiency and structural stability. HEAT simulations were conducted to validate the superior heat confinement in the programming region of the HfTe2-based PCH device. Moreover, electrical measurements of the device demonstrated its outstanding performance, which was characterized by a low RESET current (∼1.6 mA), stable two-order ON/OFF ratio, and exceptional cycling endurance (∼2 × 107). The structural integrity of the HfTe2 confinement sublayer was confirmed using X-ray photoelectron spectroscopy and transmission electron microscopy. The material properties, including electrical conductivity, cohesive energy, and electronegativity, substantiated these findings. Collectively, these results revealed that the HfTe2-based PCH device can achieve significant improvements in performance and reliability compared with conventional PCRAM devices.