Noise Source Impedance Research Articles

The Effect of Geometry on the Noise Characterization of SiGe HBTs and Optimized Device Sizes for the Design of Low-Noise Amplifiers

The impacts of various layout configuration and device dimensions on device performance are examined. The geometrical scaling issues including emitter length and emitter stripe-number scaling are used to shift simultaneously the optimum noise and optimum source impedance to a point that is close to 50 /spl Omega/. Via this method, not only is the optimal transistor size for low-noise applications obtained, but the matching network is simplified to reduce the losses of passive networks and the chip area. Based on experimental results, optimum SiGe HBTs and bias suitable for low-noise amplifiers (LNAs) are determined. Via the comparison of the state-of-the-art SiGe LNAs, it is confirmed that this method is effective to obtain better performances. Using the same method, the optimum device size at any bias and any frequency for low-noise applications can also be achieved.

Measurement of Noise Source Impedance of SMPS Using a Two Probes Approach

A novel approach to determine common-mode (CM) and differential-mode (DM) noise source impedances of a low-power switched mode power supply (SMPS) has been developed using a two current probes approach. The proposed approach allows measurement of noise source impedance of a SMPS without interrupting its normal operation. With proper setup calibration, the proposed approach can derive an equivalent circuit model, consisting of resistive and reactive components, to represent the noise source impedance with reasonable accuracy. Once the equivalent circuit model of the noise source impedance is obtained through the measurement, the most effective filter configuration and suitable component values for the built-in power line electromagnetic interference (EMI) filter of the SMPS could be designed with ease.

Wide-Band CMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling

Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching device. This allows for designing wide-band impedance-matching amplifiers with NF well below 3 dB, without suffering from instability issues. An amplifier realized in 0.25-/spl mu/m standard CMOS shows NF values below 2.4 dB over more than one decade of bandwidth (i.e., 150-2000 MHz) and below 2 dB over more than two octaves (i.e., 250-1100 MHz). Furthermore, the total voltage gain is 13.7 dB, the -3-dB bandwidth is from 2 MHz to 1.6 GHz, the IIP2 is +12 dBm, and the IIP3 is 0 dBm. The LNA drains 14 mA from a 2.5-V supply and the die area is 0.3/spl times/0.25 mm/sup 2/.

Measurement of the source impedance of conducted emission using mode separable LISN: Conducted emission of a switching power supply

AbstractIn the procedure for reducing conducted emissions, it is helpful to know the noise source impedance. This paper presents a method of measuring noise source complex impedances of common and differential mode separately. We propose a line impedance stabilization network (LISN) to measure common and differential mode noise separately without changing LISN impedances of each mode. With this LISN, conducted emissions of each mode are measured inserting appropriate impedances at the equipment under test (EUT) terminal of the LISN. Noise source complex impedances of switching power supply are well calculated from measured results. © 2002 Scripta Technica, Electr Eng Jpn, 139(2): 72–78, 2002; DOI 10.1002/eej1154

Measurement of noise source impedance of SMPS usingtwo current probes

Using two clamp-on current probes, a novel method for measuring the common-mode (CM) and differential-mode (DM) noise source impedance of a switched mode power supply (SMPS) is developed. With proper setup calibration, the method is capable of measuring a wide range of impedance values with good accuracy.

Measurement of noise source impedance of off-line converters

The insertion loss method is proposed to measure the noise source impedance of off-line power supplies. The information obtained through the proposed method enables the prediction of EMI filter performance and the design of a suitable filter for a switch mode power supply.

Measurement of the Source Impedance of Conducted Emission Using Mode Separable LISN

On the reducing procedure of conducted emissions, it is helpful to know the noise source impedance. This paper presents a method to measure noise source complex impedances of common and differential mode separately. We propose a line impedance stabilization, network (LISN) to measure common and differential mode noise separately without changing LISN impedances of each mode. With this LISN, conducted emissions of each mode are measured inserting appropriate impedances at the equipment under test (EUT) terminal of the LISN. Noise source complex impedances of switching power supply are well calculated from measured results.

The Pospieszalski noise model and the imaginary part of the optimum noise source impedance of extrinsic or packaged FET's

The imaginary part X(S/sub opt/) of the optimum noise impedance for extrinsic or packaged devices is investigated. The analysis modifies the well-known Pospieszalski noise model by applying a series feedback to the source port. A simple expression for X(S/sub opt/) is developed and is verified for extrinsic and packaged devices with a decreasing level of accuracy. The results give further insights into the way the parasitic inductors L/sub g/ and L/sub s/ affect the noise performance of the transistor and can help to design low-noise amplifier with simultaneous signal and noise power match at the input port.

A new general procedure to extract the noise parameters of microwave gaAs mesfets

In this paper a generalized procedure to extract the noise parameters of GaAs MESFETs is presented. The average quadratic error between the measured values of optimum noise figure and the calculated ones is minimized in order to obtain the optimum admittance value at the amplifier input. The hypothesis of device unilaterality is assumed. A comparison between the proposed method and the previous ones has been carried out. A consequent more simplified analytical approach to evaluate the optimum noise source impedance of a GaAs MESFET amplifier allows the proposed procedure to be easly implemented in the most popular CAD tools.

A simplified approach to optimum noise source impedance determination for GaAs FET amplifiers

A simple, analytical approach to determine the optimum noise source impedance of a GaAs FET amplifier in the 3-12 GHz frequency range is developed. The procedure can also be used in the 0-5—3 GHz range, but the model on which the procedure is based may be less accurate in this frequency range. The approach requires knowledge of the transistor's small-signal model parameters and its minimum noise temperature versus frequency. The approach is relatively insensitive to errors in the value of the GaAs FET small-signal parameters, but noise in the required minimum noise temperature data is potentially a source of nonlinear errors in the computed value of the optimum noise source impedance with respect to the error in the minimum noise temperature data The amount of error in the computed value of optimum noise source resistance is roughly proportional to the error in the minimum noise temperature data when the error at each data point is correlated, while the error in the computed value of the optimum noise source reactance is roughly three times the error present in the minimum noise temperature data. When the error is uncorrelated, the method does not yield acceptable results.

Optimum noise source impedance determination for GaAs FETs at room and cryogenic temperatures

Abstract An analytical technique is developed to determine the optimum noise source impedance for an extrinsic, or packaged, gallium arsenide field-effect transistor (GaAs FET) using only the small-signal s-parameters and the minimum noise figures available from the manufacturer's data sheet. The procedure is then modified to treat the special case of the intrinsic, or chip, GaAs FET as well. The technique is then extended to determine the optimum noise source impedance and minimum noise figure at cryogenic temperature using the room temperature results. The procedure is used to determine the optimum noise source impedance of a Mitsubishi MGF-1412 and a Mitsubishi MGFC-1412 at room and cryogenic temperature. At room temperature and 4 9 GHz, the technique yields an optimum noise source impedance of 28·4 ft -Ω64·1 Ω for the extrinsic device as compared with the measured optimum noise source impedance of 20 Ω + j55Ω. At cryogenic temperature, the optimum noise source impedance obtained is 21·1 Ω + j70·8 Ω as...

Noise models for gallium arsenide field-effect transistors at room and cryogenic temperatures

An analytical technique is developed to determine the optimum noise source impedance for a chip gallium arsenide field-effect transistor (GaAs FET) using only the small-signal s-parameters and the minimum noise figures available from the manufacturer's data sheet. The technique is then extended to determine the optimum noise source impedance and minimum noise figure at cryogenic temperatures using the room temperature results. The procedure is used to determine the optimum noise source impedance of a Mitsubishi MGFC-1412 at room and cryogenic temperatures. At room temperature, the technique yields an optimum noise source impedance that is 16% in error as compared with the measured optimum noise source impedance. At cryogenic temperatures, the result is in error by 19% for the real part and by 9% for the imaginary part as compared with the available experimental value, and by 7% for the real part and by 12% for the imaginary part as compared with a more rigorous theoretical result.

A functional GaAs FET noise model

It is the purpose of this paper to develop a theory upon which the design of low noise FET amplifiers can be based. This is not a fundamenta model of the noise mechanisms in GaAs FET's, but rather, an endeavor to relate physically measurable device capacitances and resistances to the device noise figure and optimum noise source impedance. I will be shown that the noise performance of an FET can be adequately described by two uncorrelated noise sources. One, at the input of the FET, is the thermal noise generated in the various resis, tances in the gate-source loop. This noise source is frequency dependent and it can be calculated from the equivalent circuit of the FET. The second noise source, in the Output of the FET, is frequency independent, and not recognizably related to any measured parameters. This output nise is a function of drain current and voltage. The decomposition of the FET noise into two uncorrelated sources simplifies the design of broad-band low noise amplifiers. Once the equivalent circuit of a device and its noise figure at one frequency are known, the optimum noise source impedance and noise figure over a broad range of frequencies may be calculated. For the device designer this model also may be helpful in balancing input-output noise tradeoffs.