Noise In pMOSFETs Research Articles

Characterization of Random Telegraph Signal Noise of High-Performance p-MOSFETs With a High-$k$ Dielectric/Metal Gate

The behavior of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> random telegraph signal (RTS) noise of a p-MOSFET with an advanced gate stack of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /TaN is experimentally investigated and discussed. The I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -RTS noise is evaluated on a wafer level (100 sites) for statistical evaluation. The observed ratio of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -RTS noise on a wafer is quite similar to that of a p-MOSFET with the conventional plasma-SiON dielectric, which means that the noise distribution on a wafer level is independent of the gate oxide structure and/or material. However, the relative magnitude of change of the drain current to the applied current (ΔI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) of the p-MOSFETs with high-k (HK) dielectrics is greater than that of p-MOSFETs with conventional plasma-SiON dielectrics by about six times due to the greater number of preexisting bulk traps in the HK dielectric. Therefore, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -RTS noise and its associated 1/f noise can present a serious issue to the CMOSFET with an advanced HK dielectric for low-power analog and mixed-signal applications.

Gate electrode effects on low-frequency (1/ f) noise in p-MOSFETs with high-κ dielectrics

The defects related to the gate–dielectric in high-κ-MOSFETs are studied using the 1/ f noise technique. Three different types of gate electrodes were used for this purpose – poly-Si, metal (TiN/TaN) and fully Ni Silicided (FUSI) electrodes with Hf-based oxides as the gate dielectric layer. All the three types of devices show a specific behavior near the gate electrode–dielectric interface when the trap profiles are assessed using f × S I spectra. The tunneling depths were calculated and it was found that the high-κ oxide (bulk) layers are being probed. From the drain current spectra S I vs. drain current I D of the various gate material devices at given depths, it may be inferred that the concentration of oxygen-vacancy-related defects can significantly influence the 1/ f noise performance, which can explain the differences observed in noise between the gate electrodes. Comparison of FUSI gated devices, with various percentages of Hf in the dielectric layer, shows comparable noise levels ( S VG), indicating a minor dependence on Hf-content in the gate dielectric layer.

Overview of the impact of downscaling technology on 1∕f noise in p-MOSFETs to 90 nm

An overview of theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependencies of 1/f noise in all conduction regimes are summarised. Novel experimental studies on 1/f noise in MOS transistors are presented with special emphasis on p-channel transistors from 90 nm CMOS technology. In addition to the noise in the drain terminal, the gate current noise is investigated because the gate insulator is very thin and significant gate leakage current appears at high gate biases. In the subthreshold regime, the drain current noise agrees with the ΔN model, whereas in strong inversion the evolutions of the noise level can be described by Hooge&apos;s empirical relation. The gate current noise shows 1/f and white noise components. The white noise is very close to shot noise and the 1/f noise component is almost a quadratic function of the gate leakage current. Coherence measurements reveal that the increase of drain noise at high gate biases can be attributed to tunnelling effects in the gate insulator. Both the input-referred (gate) noise and the slow oxide trap density can be used as a figure of merit of the low-frequency noise in MOSFETs.

SPICE models for flicker noise in p-MOSFETs in the saturation region

The number fluctuation theory based on the McWhorter's charge-trapping model and the bulk mobility fluctuation theory based on Hooge's hypothesis are the two major existing theories to explain the origins of the flicker noise, which is the dominant low-frequency noise source in silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We have done the flicker noise measurements and SPICE simulations for both long-channel (5 /spl mu/m) and short-channel (1.2 /spl mu/m and 0.6 /spl mu/m) p-type channel metal-oxide-semiconductor (PMOS) transistors. HSPICE [device model: level 3, level 46 (BSIM 3v2) and level 47 (BSIM 3v3); noise model: NLEV=0 and NLEV=2 and 3] and PSPICE [device model: level 3, level 6 (BSIM 3v2) and level 7 (BSIM 3v3); noise model: NLEV=0 and NLEV=2 and 3] were used for the simulations. Our measurement results suggest that in the saturation region, for long-channel PMOS transistors, the flicker noise is due to the bulk effect and it follows the mobility fluctuation theory, while for short-channel ones, it is due to the surface state effect and the number fluctuation theory applies. Our simulation results showed that for both HSPICE and PSPICE, level 3 and NLEV=0 are the appropriate models for the simulations of long-channel PMOS transistor flicker noise; HSPICE with level 47 or 49 and NLEV=2 and 3 and PSPICE with level 6 and NLEV=2 and 3 are applied for the short-channel PMOS devices. The simulation results are consistent with the measurements.