Noise Figure Performance Research Articles

A 26‐GHz Low Noise Amplifier With 1.6‐dB Minimum Noise Figure in 0.15‐μm GaN‐on‐SiC Process

ABSTRACTA 24.8–29.1‐GHz four‐stage gallium nitride (GaN) low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) is presented in this letter which is fabricated in a 0.15‐μm GaN‐on‐SiC process. The proposed GaN LNA utilizes gate/drain bypass networks and source degeneration (SD) to achieve both 0–40‐GHz unconditional stability and broadband simultaneous noise and input matching (SNIM). The measured results show a peak gain of 19.9 dB with a 3‐dB bandwidth of 4.3 GHz and a low noise figure (NF) of 1.58–2.57 dB. The input and output return losses are better than 11 dB and the output‐referred third‐order intercept point (OIP3) is greater than 21 dBm. The presented LNA has a core area of 4.2 mm2 and consumes a power dissipation of 150 mW. Compared with other state‐of‐the‐art GaN LNA designs, the proposed LNA exhibits competitive NF and overall performance.

A Ku band low-voltage and low-power CMOS low-noise amplifier with bulk isolation techniques

Abstract In this paper, a broadband(12-18G) low-noise amplifier (LNA) using 65-nm CMOS technology for satellite communication is presented. This LNA was designed in a cascode common source with inductive degeneration topology. In addition, the bulk isolation technique is employed to make the proposed LNA have a higher gain. Furthermore, a two-stage cascaded configuration combined with inductive parallel peaking technology is utilized to make the LNA achieve a wide operating band. For validation, we design this LNA in a 65nm CMOS technology. The simulated results show that S21 of 17.7dB ± 0.5dB, the input/output return loss of -10dB to -33dB and -12dB to -23dB, respectively. It offers the minimum noise figure (NF) performance of 3.33dB, reverse isolation(S12) better than 60dB, and third-order input point (IIP3) of -22.8 dBm obtained over the band of interest. Excluding the output buffer stage, the LNA is consuming 5.1 mW at a supply voltage of 0.8V and its layout area occupies 0.205 mm2.

Experimental investigation on the internal stress of bismuth-doped fiber and its effect on the noise figure of Bismuth-doped fiber amplifier.

The noise figure (NF) of a fiber amplifier is one of the key measures of amplification performance, which characterizes the quality of the amplified signal. Residual stresses are inevitably generated during the manufacturing process of optical fibers, and this can lead to changes in the refractive index (RI) distribution of the fiber. Further, the change in RI distribution causes the mode-field characteristics of the fiber to change as well, and this ultimately has an impact on the NF performance of the amplifier. However, until now, there have been fewer studies on the effect of residual stress on the NF of the fiber amplifiers. In this work, we took a commercial single-mode bismuth-doped fiber (BDF) as an example and used a self-developed stress test device to measure its residual stress and refractive index distribution and compare it with that of a passive fiber. We also comprehensively compared the distribution of residual stress and refractive index of the fiber at different pump powers and pump wavelengths. Finally, we performed numerical simulations of the bismuth-doped fiber amplifier (BDFA) based on the BDF under the theoretical mode field area and BDF after the expansion of the mode field area due to stresses to compare the NF performance. The results demonstrate that: the entire cross-section (core and cladding) of the BDF exhibits tensile stress (>0 MPa), where the residual stress at the core of the BDF is nearly 9.8 MPa higher than that of the passive fiber; The residual stress makes the mode-field area of the BDF expand by 26.7% compared with the theoretical values, which ultimately makes the NF of the BDFA rise from 4.6 dB to 4.7 dB; The stress at the BDF core is exacerbated by pump excitation, where it is elevated by about 26% and 5% compared to vacancy at 1240 nm and 1310 nm pumps, which is most likely attributed to thermal effects. Therefore, it is necessary to consider the effect of residual stresses in the fabrication of optical fibers to better achieve the radius of the expected indicators. This work contributes to the better development of O-band BDFAs, especially for pre-simulation of the actual performance of BDFAs with a practical reference.

DESIGN OPTIMIZATION OF LOW NOISE AMPLIFIER FOR 900MHZ GSM BAND APPLICATIONS USING GREY WOLF ALGORITHM

In this work, the design of a high-performance single-stage Low Noise Amplifier (LNA) for GSM applications is taken into consideration. LNA design is one of the key stages of a wireless communication system due to its dominance over the whole system's noise figure performance. Although it is possible to achieve a very high gain and low noise figure with the usage of multi-stage transistors, such designs would also have a high complexity and manufacturing cost. The main aim of this work is to propose a single transistor LNA design for GSM application with a gain level of 14.3 dB, return loss level of less than 15 dB, and noise figure of 1.8 dB over the operation band of 820-980 MHz. the optimal design variables of the model is obtained via Grey Wolf optimization procedure.

An MMIC LNA for Millimeter-Wave Radar and 5G Applications with GaN-on-SiC Technology.

This paper presents a monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) that is compatible with n257 (26.5-29.5 GHz) and n258 (24.25-27.5 GHz) frequency bands for fifth-generation mobile communications system (5G) and millimeter-wave radar. The total circuit size of the LNA is 2.5 × 1.5 mm2. To guarantee a trade-off between noise figure (NF) and small signal gain, the transmission lines are connected to the source of gallium nitride (GaN)-on-SiC high electron mobility transistors (HEMT) by analyzing the nonlinear small signal equivalent circuit. A series of stability enhancement measures including source degeneration, an RC series network, and RF choke are put forward to enhance the stability of designed LNA. The designed GaN-based MMIC LNA adopts hybrid-matching networks (MNs) with co-design strategy to realize low NF and broadband characteristics across 5G n257 and n258 frequency band. Due to the different priorities of these hybrid-MNs, distinguished design strategies are employed to benefit small signal gain, input-output return loss, and NF performance. In order to meet the testing conditions of MMIC, an impeccable system for measuring small has been built to ensure the accuracy of the measured results. According to the measured results for small signal, the three-stage MMIC LNA has a linear gain of 18.2-20.3 dB and an NF of 2.5-3.1 dB with an input-output return loss better than 10 dB in the whole n257 and n258 frequency bands.

Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting Qubit Readout

This article proposes a cryogenic inverter-based low noise amplifier (LNA) for qubit readout. Its input impedance matching is realized by a high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> on-chip gate inductor and capacitive load through the gate-to-drain feedback capacitance of the input transistors. Cascode transistors are used to optimize the impedance matching, which results in a larger gate inductor and smaller load capacitor and hence a higher passive and inverter gain. Owing to the high passive gain and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factor of the gate inductor at 4 K, the noise of the active stages is substantially suppressed with a negligible noise contribution of the gate inductor. Moreover, with the current re-use in the inverter topology, less power consumption is achieved for the given transconductance of transistors. The input impedance, gain, and noise analyses of the proposed LNA are performed for room temperature (RT) operation, and its noise optimization is done by taking the cryogenic operation of the devices into account. We demonstrate with the circuit analysis and measurement results that the input impedance of the LNA has a low sensitivity to variations on device parameters at cryogenic temperatures. The LNA is implemented in a 28 nm CMOS technology. It achieves 0.4–0.7 dB noise figure (NF) with 4.2 mW power consumption at 4 K, and its operating frequency is between 6–8 GHz. The LNA consumes very low power compared to the state-of-the-art cryogenic CMOS LNAs while providing similar NF performance at 4 K, which makes it suitable for dilution refrigerators.

Frequency-Reconfigurable Dual-Band Low-Noise Amplifier With Interstage Gm-Boosting for Millimeter-Wave 5G Communication

A differential low-noise amplifier (LNA) for the 5G n257 band and a frequency reconfigurable differential LNA for both the 5G n257 and n260 bands (26.5–29.5 and 37–40 GHz), fabricated in a 65-nm CMOS process, are presented. Both LNAs achieve better gain and noise figure performances due to the use of magnetically coupled gm-boosting in the common-gate stage of a cascode amplifier. Furthermore, the frequency-reconfigurable LNA uses frequency reconfigurable matching circuits at the input, interstage, and output to achieve optimal noise and gain matchings for each band. The single band LNA has a core chip area of 0.11 mm2, a peak gain of 11.9 dB, a 3-dB bandwidth of 5.3 GHz, and a noise figure of 2.79 dB at 28.5 GHz. The dual-band LNA is capable of dual-band operation due to the reconfiguring matching circuits with switched coupled inductors (SCIs) and switched capacitors. It has a core chip area of 0.12 mm2, peak gains of 11.1/8.5 dB, 3-dB bandwidths of 4.8/9.4 GHz, and minimum noise figures of 3.49/4.01 dB at 28.5/38 GHz, respectively.

SiGe and CMOS Technology for State-of-the-Art Millimeter-Wave Transceivers

Innovation and evolution are paramount where the demand for wideband, data-intensive connectivity is ever-increasing, and the only constant is change. Standards that define the operation of next-generation mobile networks are moving away from the traditional radio frequency (RF) spectrum and into millimeter-wave (mm-wave) bands. The physical layer (PHY) for IEEE 802.11ad Wi-Fi and 802.11ay WLANs dictates operation in the unlicensed 60 GHz band. 5G New Radio (NR) applications utilize selected bands from 26 to 39 GHz. Additionally, newly developing Fourth Industrial Revolution (4IR) applications depend on 5G NR as an enabling technology. Satellite communications and wireless backhaul will occur in E-band between 70–86 GHz. Increasing demands from the market cause designers to push boundaries, and the development of standards guide technological advances. Perhaps the most substantial improvements are observed in integrated circuit technology. This article details the major Si processes, namely Complementary Metal Oxide Semiconductor (CMOS) and SiGe Bipolar CMOS (BiCMOS), and their foray into the wireless transceiver space traditionally dominated by GaAs. CMOS and BiCMOS have become popular in many communities because of their low fabrication cost and excellent digital integration capabilities. RF performance has matured to where Si is a serious competitor for tried-and-tested III-V technologies. Some extreme environments and sophisticated applications still favor GaAs and GaN, however. GaAs, for example, can yield unparalleled output power and excellent noise figure performance, albeit at a higher cost and increased design and manufacturing complexity due to the multi-chip nature of these circuits.

Design and Analysis of a Cascode Distributed LNA With Gain and Noise Improvement in 0.15-μm GaAs pHEMT Technology

This brief presents a 2.0~42.0 GHz ultra-wide bandwidth Cascode distributed low-noise amplifier (CDLNA) MMIC design. With the proposed coupled-line (CL) sections between each drain-artificial transmission line (D-ATML) node and related gate-artificial transmission line (G-ATML) node, the traveling signal is reused to enhance the gain and broaden the operation bandwidth simultaneously. To improve the gain further, the inductive gain peaking has also been employed at each drain of common-source (CS) and common-gate (CG) transistors. Meanwhile, an active termination technique incorporating active and passive elements has been adopted to achieve better noise figure (NF) performance. Employing the proposed techniques, an LNA prototype has been designed and fabricated in a 0.15- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs E-Mode pHEMT technology with the chip size of 1.53 mm2 including all the pads. From test results, the proposed CDLNA demonstrates a peak gain of 14.1 dB, the best NF of 2.1 dB, a group delay of 102 ± 58.4 ps, and 23.25/14.7 dBm best OIP3/OP1dB, respectively. The total power consumption is 129 mW under 3 V VDD.

A self-biased GaN LNA with 30 dB gain and 21 dBm P1dB for 5G communications

Abstract We present a self-biased three-stage GaN-based monolithic microwave integrated circuit low-noise amplifier (LNA) operating between 26 and 29 GHz for 5G mobile communications. The self-biasing circuit, common-source topology with inductive source feedback, and RLC negative feedback loops between gate and drain of the third transistor were implemented to achieve low noise, good port match, high stability, high gain, and compact size. Measurement results show that the LNA has a high and flat gain of 30.5 ± 0.4 dB with noise figure (NF) of 1.65–1.8 dB across the band. The three-stage topology also achieves high linearity, providing the 1 dB compression point output power (P1dB) of 21 dBm in the band. To our knowledge, this combination of NF, gain, and linearity performance represents the state of art of self-biased LNA in this frequency band.

A Simplified Vector-Sum Phase Shifter Topology With Low Noise Figure and High Voltage Gain

An simplified vector-sum phase shifter (VSPS) topology is proposed in this article. The proposed VSPS topology employs only one 90° coupler to perform as both an I/Q generator and a vector summer. Compared with the literaturally reported VSPS, the proposed VSPS features a simpler topology and improved noise figure (NF) performance. Moreover, active baluns based on the self-calibration technique are employed to provide antiphase signals and improve the gain performance of the VSPS. For demonstration, a 24–30-GHz VSPS based on the proposed topology is implemented in the 65-nm CMOS process, exhibiting 3.5° rms phase error and 0.9-dB rms gain error. The average gain of the implemented VSPS is as high as 9 dB at the central frequency of 27 GHz. The NF ranges from 4.8 to 9 dB from 24 to 30 GHz, and the core chip size is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.36\times0.59$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 1.8-2.7 GHz Triple-Band Low Noise Amplifier with 31.5 dB Dynamic Range of Power Gain and Adaptive Power Consumption for LTE Application.

This paper presents a multi-gain radio frequency (RF) front-end low noise amplifier (LNA) utilizing a multi-core based on the source degeneration topology. The LNA can cover a wide range of input and output frequency matching by using a receiver (RX) switch at the input and a capacitor bank at the output of the LNA. In the proposed architecture here, to avoid the saturation of RX chain, 12 gain steps including positive, 0 dB, and negative power gains are controlled by a mobile industry processor interface (MIPI). The multi-core architecture offers the ability to control the power consumption over different gain steps. In order to avoid the phase discontinuity, the negative gain steps are provided using an active amplification and T-type attenuation path that keeps the phase discontinuity below ±5 degrees between two adjacent power gain steps. Using the multi-core structure, the power consumption is optimized in different power gains. The structure is enhanced with the adaptive variable cores and reactance parameters to maintain different power consumption for different gain steps and remain the output matching in an acceptable operating range. Furthermore, auxiliary linearization circuitries are added to improve the input third intercept point (IIP3) performance of the LNA. The chip is fabricated in 65 nm complementary metal-oxide semiconductor (CMOS) silicon on insulator (SOI) process and the die area is 0.308 mm2. The proposed architecture achieves the IIP3 performance of −10.2 dBm and 8.6 dBm in the highest and lowest power gains, which are 20.5 dB and −11 dB, respectively. It offers the noise figure (NF) performance of 1.15 dB in the highest power gain while it reaches 14 dB when the power gain is −11 dB. The LNA consumes 16.8 mA and 1.33 mA current from a 1 V power supply that is provided by an on-chip low-dropout (LDO) when it operates at the highest and lowest gains, respectively.

Optimization of hybrid amplifier parameters for improved optical link performance

In this manuscript, the gain of the EDFA-Raman hybrid optical amplifier (HOA) is maximized using a popular nature inspired Whale Optimization Algorithm (WOA). The dominating parameters of HOA, length of Raman amplifier and EDFA and its pump powers are optimized to get the maximum possible gain. Further, the performance of WOA is compared by using other metaheuristic techniques such as Real coded Genetic Algorithm, Differential Evolution, Particle Swarm Optimization, to optimize the same model of HOA. WOA proves to be a better optimization technique as it is able to find maximum gain, have a better convergence curve and box plot performance as compared to the other three techniques. Moreover, the gain flatness and noise figure performance of HOA is compared with EDFA and Raman amplifier.

Low Noise Amplifier with Improved Gain and Reduced Noise-Figure in 90nm CMOS Technology

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented in this paper. The proposed CMOS low noise amplifier (LNA) is designed using common-gate (CG) topology as the first stage to achieve ultra-wideband input matching. The common-gate (CG) is cascaded with common- source (CS) topology with current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power. The Buffer stage is used as output matching network to improve the reflection coefficient. The proposed low noise amplifier (LNA) is implemented using CADENCE Virtuoso Analog and Digital Design Environment tool in 90nm CMOS technology. The LNA provides a forward voltage gain or power gain (S21) of 32.34dB , a minimum noise figure of 2dB, a reverse-isolation (S12) of less than - 38.74dB and an output reflection coefficient (S22) of less than -7.4dB for the entire ultra-wideband frequency range. The proposed LNA has an input reflection coefficient (S11) of less than -10dB for the ultra-wideband frequency range. It achieves input referred 1-dB compression point of 78.53dBm and input referred 3-dB compression point of 13dBm. It consumes only 24.226mW of power from a Vdd supply of 0.7V.

A Low-Power High Gain and High Linearity CMOS RF Front-End Design Involving a Charge Injection Mixer for V2X Technology

In this paper, an RF front-end (RFFE) circuit consisting of a low noise amplifier (LNA) and a down-conversion mixer for vehicle-to-everything (V2X) applications in a 65-nm CMOS process is presented. V2X standard has a carrier frequency of 5.9[Formula: see text]GHz with 10 and 20[Formula: see text]MHz bandwidth options. The LNA topology of the RFFE is based on an inductively degenerated cascode common source differential approach. The mixer design uses a double-balanced topology with a charge injection method to enhance the linearity and noise figure performance. The RFFE design shows a single sideband integrated noise figure of 4.47[Formula: see text]dB with a total conversion gain of 28[Formula: see text]dB. The IIP3 is obtained as [Formula: see text]17[Formula: see text]dBm with charge injection in the mixer which is an improvement of 5[Formula: see text]dB as compared to no charge injection. The design consumes a total current of 10.24[Formula: see text]mA from a 1.2-V supply. This work is the first CMOS RFFE design implemented for V2X applications.

A Common-Gate Current-Reuse UWB LNA for Wireless Applications in 90 nm CMOS

In this paper, a CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented. The proposed CMOS LNA is designed using common-gate (CG) topology at the first stage to achieve ultra wideband input matching. The common-gate has been cascaded with common-source (CS) current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power consumption. In order to ensure maximum power flow from CG input stage to gm boosted CS current-reused stage, parallel-series LC matching has been used. The output-matching network is used to improve the output reflection coefficient. The LNA is designed using standard 90 nm CMOS process for 3.1–10.6 GHz UWB. It exhibits a power-gain (S21) of 19.2–20.8 dB, an NF of 2.3–3.7 dB, a reverse-isolation (S12) of less − 53.8 dB and an S22 of less than − 6 dB for the entire UWB frequency range. The proposed LNA has an input reflection coefficient (S11) of less than − 10.6 dB for 3.1–10.6 GHz. It achieves input 1-dB compression point (P1dB) of − 17 dBm at 6 GHz and input third-order intercept point (IIP3) of − 8 dBm, while it consumes only 5.05 mW of power from a Vdd supply of 0.7 V.

Raman/EDFA hybrid bidirectional amplifier for fiber-optic time and frequency synchronization.

Herein, we verify that a Raman/EDFA hybrid amplifier can improve the stability of fiber-optic time and frequency synchronization systems compared to the Er3+-doped fiber amplifier (EDFA), owing to its higher gain and lower noise figure (NF) performance. We studied the variation law of Raman gain efficiency for a fiber Raman amplifier (FRA) as a function of pump power and input signal power, designed a bidirectional Raman/EDFA hybrid amplifier, and proved that equivalent NF below 0 dB can be obtained. Finally, hybrid amplifiers were compared to EDFAs in a free-running frequency synchronization system. The transfer stabilities reached 1.9678 × 10-13/1 s and 2.0248 × 10-13/1 s when FRA + EDFA and EDFA + FRA configurations were used, respectively, both exhibiting better performance than the stability of 3.0905 × 10-13/1s obtained by EDFA.

A Ka-Band MMIC LNA in GaN-on-Si 100-nm Technology for High Dynamic Range Radar Receivers

A Ka-band monolithic low-noise amplifier (LNA) with high gain and high dynamic range (DR) has been designed and implemented in a 100-nm gallium nitride (GaN)-on-Si technology. The LNA is designed as the first stage of a high DR receiver in an frequency modulated continuous wave (FMCW) radar for the detection of small drones. The three-stage monolithic microwave integrated circuit (MMIC) LNA has a linear gain of 26 dB and a noise figure (NF) of 2 dB in the frequency band 33-38 GHz. The output 1-dB compression point (P1dB) and output IP3 at 37 GHz are 20 and 28.4 dBm, respectively. To our knowledge, this combination of NF, gain, and DR performance represents the state of art in this frequency band.

A 4.4-mA ESD-Safe 900-MHz LNA With 0.9-dB Noise Figure

A 900-MHz 1.2-V 4.36-mA low-noise amplifier (LNA) with a minimum of 0.92-dB noise figure (NF) at 868 MHz, -12-dBm IIP3, with one inductor (external) is demonstrated. The circuit achieves narrowband input matching on a wideband LNA without inductive degeneration. A new half-cascoding technique is used to improve the input matching (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) while simultaneously achieving sub-1-dB NF performance. The 0.13-μm CMOS LNA is fabricated with embedded electrostatic discharge (ESD) protection diodes that add 60 and 80-fF loads at the RF input and output ports. At 868 MHz, the packaged LNA has a measured input return loss (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) of -18 dB and the transmission gain (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) of 14.2 dB. At 900 MHz, the LNA has a measured NF of 0.98 dB. The LNA (excluding the buffer) occupies an area of 0.047 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The chip passes the human body model (HBM) test with an ESD zap of 2.5 kV within 10% margin of its prezap I-V characteristics, under JEDEC standards. Multiple packaged chips were characterized with no perceptible difference in performance, indicating a robust design.

Ultra-Broadband Bismuth-Doped Fiber Amplifier Covering a 115-nm Bandwidth in the O and E Bands

In this article, we experimentally demonstrate an all-fiber optical amplifier using Bi-doped phosphosilicate fiber (BPSF) operating in both the O-band and the E-band, providing >20 dB gain from 1345 to 1460 nm for an input signal power of −23 dBm. A maximum gain of 31 dB with a noise figure (NF) of 4.8 dB was achieved at 1420 nm for −23 dBm input signal, whereas for an input signal power of −10 dBm it was 26 dB with a NF of 5.3 dB. The in-band OSNR of the proposed Bi-doped fiber amplifier (BDFA) was >22 dB from 1345 to 1460 nm for a −23 dBm input signal. The gain coefficient was found to be 0.04 dB/mW for a −23 dBm input signal. Also, the temperature dependent gain and NF performance of the BDFA within −40 to +60 °C were characterized. The temperature-dependent-gain (TDG) coefficient for a −23 dBm input signal was found to be −0.015 dB/°C at a signal wavelength of 1420 nm where the BDFA gain is maximum, while for an input signal power of −10 dBm it was −0.01 dB/°C at 1420 nm. The TDG coefficient of the proposed BDFA from 1350–1460 nm was in the range from −0.079 to −0.008 dB/°C. The BDFA gain and NF performance were also measured and compared using BPSFs with different unsaturable loss (UL) characteristics.