Next-state Function Research Articles

Finite-state residual vector quantization using a tree-structured competitive neural network

Finite-state vector quantization (FSVQ) is known to give better performance than the memoryless vector quantization (VQ). This paper presents a new FSVQ scheme, called finite-state residual vector quantization (FSRVQ), in which each state uses a residual vector quantizer (RVQ) to encode the input vector. This scheme differs from the conventional FSVQ in that the state-RVQ codebooks encode the residual vectors instead of the original vectors. A neural network predictor estimates the current block based on the four previously encoded blocks. The predicted vector is then used to identify the current state as well as to generate a residual vector (the difference between the current vector and the predicted vector). This residual vector is encoded using the current state-RVQ codebooks. A major task in designing our proposed FSRVQ is the joint optimization of the next-state codebook and the state-RVQ codebooks. This is achieved by introducing a novel tree-structured competitive neural network in which the first layer implements the next-state function, and each branch of the tree implements the corresponding state-RVQ. A joint training algorithm is also developed that mutually optimizes the next-state and the state-RVQ codebooks for the proposed FSBVQ. Joint optimization of the next-state function and the state-RVQ codebooks eliminates a large number of redundant states in the conventional FSVQ design; consequently, the memory requirements are substantially reduced in the proposed FSRVQ scheme. The proposed FSRVQ can be designed for high bit rates due to its very low memory requirements and the low search complexity of the state-RVQ's. Simulation results show that the proposed FSRVQ scheme outperforms conventional FSVQ schemes both in terms of memory requirements and the visual quality of the reconstructed image. The proposed FSRVQ scheme also outperforms JPEG (the current standard for still image compression) at low bit rates.

ペトリネットによるファジィ制御系の安定解析

ファジィ制御は、一般にif-then型のファジィルールにより制御規則の記述を行ない、ファジィ推論により操作量を求める手法であり、熟練者の経験に基づいたあいまいな制御を行なうことができるため、さまざまな分野で応用されている。ファジィ制御器の問題点として安定性の保証が困難であることが指摘されているが、近年ではファジィ制御器の安定性に関する研究が進められている。しかし、従来の安定解析手法はファジィルールを数式表現に置き換えることでなされており、ファジィ制御の分かりやすいという特徴を損なってしまっている。本論文では、制御対象および制御器のファジィルールを離散事象表現とみなすことで、ファジィ制御系をペトリネットを用いて表現し、状態推移関数を用いた安定性の解析手法を提案する。制御系のとりうる状態はペトリネットのプレースで表され、現在の制御系の状態はプレースのトークンの有無によって表される。また、ファジィルールの発火はトランジションの発火として表現される。本手法はファジィ制御の持つ挙動の分かりやすさという特徴を損なうことなく、ファジィ制御系の解析を可能にしている。本論文では、簡単な制御系に対して本手法を適用しその有用性を示す。

Correlation properties of a general binary combiner with memory

Correlation properties of a general binary combiner with an arbitrary number M of memory bits are derived and novel design criteria proposed. For any positive integer m, the sum of the squares of the correlation coefficients between all nonzero linear functions of m successive output bits and all linear functions of the corresponding m successive inputs is shown to be dependent upon a particular combiner, unlike the memoryless combiners. The minimum and maximum values of the correlation sum as well as the necessary and sufficient conditions for them to be achieved are determined. It turns out that the security of combiners with memory can be considerably improved if M is not small. An efficient linear sequential circuit approximation (LSCA) method is developed for obtaining output and input linear functions with comparatively large correlation coefficients which is feasible for large M and works for any practical scheme. The method consists in deriving and solving a linear sequential circuit with additional nonbalanced inputs that is based on linear approximations of the output and the component next-state functions. The corresponding correlation attack on combiners with linear feedback shift registers is analyzed and it is shown that every such combiner with or without memory is essentially zero-order correlation immune.

Next-state functions for finite-state vector quantization

The finite-state vector quantization scheme called dynamic finite-state vector quantization (DFSVQ) is investigated with regard to its subcodebook construction. In the DFSVQ, each input block is encoded by a small codebook called the subcodebook which is created from a much larger codebook called supercodebook. Each subcodebook is constructed by selecting, using a reordering procedure, a set of appropriate code-vectors from the supercodebook. The performance of the DFSVQ depends on this reordering procedure; therefore, several reordering procedures are introduced and their performance are evaluated. The reordering procedures investigated, are based on the conditional histogram of the code-vectors, index prediction, vector prediction, nearest neighbor design, and the frequency usage of the code-vectors. The performance of the reordering procedures are evaluated by comparing their hit ratios (the number of blocks encoded by the subcodebook) and their computational complexity. Experimental results are presented and it is found that the reordering procedure based on the vector prediction performs the best when compared with the other reordering procedures.

Next-state functions for finite-state vector quantization

The finite-state vector quantization scheme called dynamic finite-state vector quantization (DFSVQ) is investigated with regard to its subcodebook construction. In the DFSVQ, each input block is encoded by a small codebook called the subcodebook which is created from a much larger codebook called supercodebook. Each subcodebook is constructed by selecting, using a reordering procedure, a set of appropriate code-vectors from the supercodebook. The performance of the DFSVQ depends on this reordering procedure; therefore, several reordering procedures are introduced and their performance are evaluated. The reordering procedures investigated, are based on the conditional histogram of the code-vectors, index prediction, vector prediction, nearest neighbor design, and the frequency usage of the code-vectors. The performance of the reordering procedures are evaluated by comparing their hit ratios (the number of blocks encoded by the subcodebook) and their computational complexity. Experimental results are presented and it is found that the reordering procedure based on the vector prediction performs the best when compared with the other reordering procedures.

STOIC: state assignment based on output/input functions

A finite-state-machine (FSM) synthesis procedure, specifically aimed at using primary inputs and primary output functions as state variables, is proposed. The number of next-state functions that have to be implemented is thus reduced, potentially reducing the area of the synthesized circuit. Also, as more of the state variables are directly observable (the primary outputs used as state variables), and directly controllable (the primary inputs used as state variables) the testability of the implementation is increased. Experimental results are given to demonstrate the effectiveness of the procedure in reducing area. >

State machine synthesis with Weinberger arrays

The development of a digital circuit synthesis program is described. The program accepts the transition table or a state machine and returns equations for an implementation that assumes a sum-of-product next-state and output functions. From the equations for the next-state and output functions, nMOS VLSI layout for a Weinberger array is generated. D flip-flops are assumed for memory elements. Using this tool, tedious manual calculations can be avoided and layouts can be generated automatically from state table descriptions.

Aliasing errors in linear automata used as multiple-input signature analyzers

This paper deals with the aliasing probability of multiple-input data compressors used in self-testing networks. It is shown that a far more general class of linear machines than linear feedback shift registers can be used for data compression purposes. The function of these machines is modeled by a Markov process. The steady-state value of the aliasing probability is shown to be the same as for single-input signature analysis registers. An easily verifiable criterion is given that allows one to decide whether a given linear machine falls into this class of multiple-input data compressors. The steady-state value of the aliasing probability is shown to be independent of the correlation of the data streams at the inputs of the data compressor. Two kinds of circuits are analyzed in more detail with respect to their aliasing properties: linear feedback shift registers with multiple inputs, and linear cellular automata. Simulation results show the effect of the next-state function on the steady-state value of the aliasing probability and the effect of correlation on the transient response.

Reticular activation and the dynamics of neuronal networks

It is postulated that during arousal the cortical system is driven by a spatially and temporally noisy signal arising from non-specific reticulo-cortical pathways. An elementary unit of cortical neuroanatomy is assumed, which permits non-linear dynamics to be represented by stochastic linear equations. Under these assumptions the resonant modes of the system of cortical dendrites approach thermodynamic equilibrium. Specific sensory signals perturb the dendritic system about equilibrium, generate low frequency, linear, non-dispersive waves corresponding to the EEG, which in turn regulate action potential sequences, and instantiate internal inputs to the dendritic field. A large and distributed memory capacity in axo-synaptic couplings, resistance to interference between functionally separate logical operations, and a very large next-state function set emerge as properties of the network. The model is able to explain the close association of the EEG with cognition, the channel of low capacity corresponding to the field of immediate attention, the low overall correlation of action potentials with EEG, and specificity of action potentials in some neurons during particular cognitive activity. Predictions made from hypothesis include features of thermal equilibrium in EEG (determinable by autoregression) and expectation that the cortical evoked response can be accounted for as the response to a sensory impulse of specific time characteristics.

A Note on Strongly Fault-Secure Sequential Circuits

It is proved that any sequential circuit with its next-state function d and output function w is strongly fault secure for unidirectional faults in d and w if i) the outputs of w are encoded in an unordered code, and ii) d and w are implemented with inverter-free circuits.

An Algorithm for the Design of Labeled-Transition Finite-State Vector Quantizers

A finite-state vector quantizer (FSVQ) is a switched vector quantizer where the sequence of quantizers selected by the encoder can be tracked by the decoder. It can be viewed as an adaptive vector quantizer with backward estimation, a vector generalization of an AQB system. Recently a family of algorithms for the design of FSVQ's for waveform coding application has been introduced. These algorithms first design an initial set of vector quantizers together with a next-state function giving the rule by which the next quantizer is selected. The codebooks of this initial FSVQ are then iteratively improved by a natural extension of the usual memoryless vector quantizer design algorithm. The next-state function, however, is not modified from its initial form. In this paper we present two extensions of the FSVQ design algorithms. First, the algorithm for FSVQ design for waveform coders is extended to FSVQ design of linear predictive coded (LPC) speech parameter vectors using an Itakura-Saito distortion measure. Second, we introduce a new technique for the iterative improvement of the next-state function based on an algorithm from adaptive stochastic automata theory. The design algorithms are simulated for an LPC FSVQ and the results are compared with each other and to ordinary memoryless vector quantization. Several open problems suggested by the simulation results are presented.

Positive Fail-Safe Realization of Synchronous Sequential Machines

The correspondence deals with the fail-safe realization of synchronous sequential machines under the assumption that the next-state functions are in any positive form. This leads to new classes of assignments called positive fail-safe assignment's (PFSA) The feasibility conditions of such assignments are given and systematic procedures are presented for deriving them using k-out-of-n codes.

Asynchronous State Assignments with Unateness Properties and Fault-Secure Design

Techniques to construct standard state assignments that yield unate next-state functions are presented. These proposed assignments use Berger codes. Further, it is also shown how to modify the so-called (2n + 1) type assignment for unateness. The modified assignments require 2[n + I + 1og <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (n + 1)] variables Finally, a procedure to design fault-secure asynchronous networks is presented. The assignments proposed in this paper are shown to be useful for this design.

Design of Fail-Safe Sequential Machines Using Separable Codes

A method for realization of fail-safe sequential machines, using a class of separable codes called Berger codes in the state assignment, has been presented. The separability property is desirable in certain applications. Both on-set and off-set realizations are used for the next-state functions and this has the advantage over the methods using only on-set realization in that the checker is simpler. Realization of the output circuit is also considered.

State assignment and entropy

A recent paper has presented a method of state assignment based upon the maximisation of true (or false) minterms in the next-state functions. This method has the advantage of very elegant implementation. This letter seeks to interpret these results in the light of the concept of entropy. It is shown that there is some justification for using the maximisation of true (false) minterms for optimal state assignment and some indication is given of the limitations of the method.

A logical model of genetic activities in Lukasiewicz algebras: the non-linear theory.

A categorical framework for logical models of functional genetic systems is proposed. The logical models of genetic nets are shown to simulate non-linear systems withn-state components and allow for the generalization of previous logical models of neural nets. An algebraic formulation of variable ‘next-state functions’ is presented which can be used for the description of developmental processes.

Comments on "Monotone Functions in Sequential Circuits"

The above paper1 by Mago discusses the state assignment problem by means of monotone increasing (i.e., positive) next-state functions for both synchronous and asynchronous sequential networks. It may be interesting to note that the same subject for synchronous sequential networks has also been studied under a somewhat different title: Fail-Safe Realization of Sequential Machines. This is because a realization with positive next-state functions (and positive output functions) results in a fail-safe sequential circuit in a certain sense.

Channel capacity of a finite-state linear automation (Corresp.)

A finite-state deterministic linear automaton is viewed as a communication channel from a source to a receiver, accepting source symbols as inputs and generating outputs for a receiver. The automaton is assumed to be composed of two subautomata, one representing the next-state function and one the output function. With the use of Shannon's theorem for capacities of discrete channels, it is demonstrated that the channel capacities of the linear automaton and its subautomata can be readily determined by an analytical procedure rather than by applying an iterative algorithm as required for general finite-state automata.

Realization Methods for Asynchronous Sequential Circuits

This paper gives a unified approach for describing various systematic ways of using built-in delays in normal fundamental mode circuits. The transition of the circuit from one total stable state to another is characterized by the constraints imposed upon the next-state functions, and the realization method is characterized by the conditions under which these constraints can be satisfied simultaneously.

Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part II

This paper is Part II of a two-part study of systematic procedures for realizing synchronous sequential machines using flip-flop memory. In this study the methods of Dolotta and McCluskey, and Weiner and Smith are generalized so that they can be used to obtain directly good realizations of machines using flip-flop memory. In Part I the generalizations were simple, straightforward, and required a minimal amount of changes to the basic methods. For machines using trigger flip-flop memory or a combination of trigger and set-reset, or trigger and J-K flip-flops, these generalizations usually yield significantly better realizations than those obtained from the use of the ungeneralized versions of these methods along with methods for transforming the resulting next-state functions into flip-flop input functions. Minimization of changes of these methods was achieved at the expense of imposing the restriction that the inputs to each of the set-reset and J-K flip-flop types be complementary. In the present paper further generalizations for obtaining even better realizations using trigger, set-reset, and J-K flip-flops are developed by dropping the aforementioned restriction.