Network-on-Chip Mapping Research Articles

A Machine Learning Mapping Algorithm for NoC Optimization

Network on chip (NoC) is a promising solution to the challenge of multi-core System-on-Chip (SoC) communication design. Application mapping is the first and most important step in the NoC synthesis flow, which determines most of the NoC design performance. NoC mapping has been confirmed as an NP-hard (Non-Polynomial hard) problem, which could not be solved in polynomial time. Various heuristic mapping algorithms have been applied to the mapping problem. However, the heuristic algorithm easily falls into a local optimal solution which causes performance loss. Additionally, regular topologies of NoC, such as the ring, torus, etc., may generate symmetric solutions in the NoC mapping process, which increase the performance loss. Machine learning involves data-driven methods to analyze trends, find relationships, and develop models to predict things based on datasets. In this paper, an NoC machine learning mapping algorithm is proposed to solve a mapping problem. A Low-complexity and no symmetry NoC mapping dataset is defined, and a data augmentation approach is proposed to build dataset. With the dataset defined, a multi-label machine learning is established. The simulation results have confirmed that the machine learning mapping algorithm is proposed have at least 99.6% model accuracy and an average of 96.3% mapping accuracy.

New Heuristic Algorithm for Low Energy Mapping for 2.5-D Integration

A chiplet placement algorithm for 2.5-D IC integration on an interposer is discussed in this paper. Inspired by the NoC (network-on-chip) mapping problem, we propose a novel chiplet placement algorithm called the CCEOA (chiplet communication energy optimization algorithm), which takes into account the actual size of the chiplet. The CCEOA can map chiplets to mesh topology, resulting in a layout with a low CEC (communication energy consumption). The algorithm considers the spacing of the chiplets while selecting the initial nodes and the nodes to map the next chiplet. Furthermore, because there exist nodes resulting in the same CEC increment during the mapping process, the algorithm adopts a secondary local exploration strategy to further select nodes. Meanwhile, the lateral and vertical placements of chiplets are also considered. The algorithm is implemented and evaluated with a 2.5-D IC integration with 22 chiplets to demonstrate its efficiency and the accuracy.

IHPSA: An improved bio-inspired hybrid optimization algorithm for task mapping in Network on Chip

System on a chip (SoC) is the leading technology in the recent global world of digitization. The classical bus-based regular communication infrastructures of SoCs cannot handle the growing number of cores. Designers came up with new communication methods known as the network on chip (NoC) to solve this problem. NoC offers scalability, flexibility, modularity, and efficiency. As the number of cores of SoC keeps on increasing due to advancement in technology and shrinking size of transistors, the arrangement of cores on the NoC becomes more significant that can influence the Network on Chip’s overall performance and efficiency. Therefore, there is always a need for efficient and intelligent mapping algorithms for achieving optimal mapping solutions since existing mapping techniques either do not achieve optimal results or possess more execution time. To resolve this issue, we proposed an improved hybrid particle swarm and simulated annealing optimization algorithm iHPSA. The proposed iHPSA combines Improved Particle Swarm Optimization and Simulated Annealing for NoC mapping and incorporates a machine-learning K-means clustering algorithm to segregate tasks into clusters based on communication bandwidth. The Elbow method is used in the K-means clustering algorithm to predict the number of clusters in large applications intelligently.Comparative analysis of different performance factors shows that the proposed approach has performed better than the existing mapping algorithms. The proposed algorithm offers improved performance by reducing communication cost, latency, and power of the network. the proposed iHPSA shows an average enhancement on power reduction of 22.67%, 30.95% , 22.87%, 27.61%, 16.07%, 8.87%, 8.01% ,30% and 9% over PSO,SA,GA,ACO,BA,SCSO,BEMAP,CSO and ILP. Improved energy consumption by 5.70%, 20%, 25%, 24% and 4.09% over PSO, SA ,GA , BEMAP and CSO. iHPSA improved latency by 1.5% over PSO, 6.2% over SA, 6.67% over GA , 9.7% over BEMAP and 1.2% over CSO. The proposed mapping approach’s efficiency is evaluated with a comparative analysis of communication cost, power, energy, and latency for standard and randomly generated benchmark applications. The experimental results revealed that iHPSA outperforms other nature-inspired algorithms by offering an efficient application approach that reduces communication cost, power, energy, and latency.

Tasks mapping in the network on a chip using an improved optimization algorithm

PurposeA set of routers that are connected over communication channels can from network-on-chip (NoC). High performance, scalability, modularity and the ability to parallel the structure of the communications are some of its advantages. Because of the growing number of cores of NoC, their arrangement has got more valuable. The mapping action is done based on assigning different functional units to different nodes on the NoC, and the way it is done contains a significant effect on implementation and network power utilization. The NoC mapping issue is one of the NP-hard problems. Therefore, for achieving optimal or near-optimal answers, meta-heuristic algorithms are the perfect choices. The purpose of this paper is to design a novel procedure for mapping process cores for reducing communication delays and cost parameters. A multi-objective particle swarm optimization algorithm standing on crowding distance (MOPSO-CD) has been used for this purpose.Design/methodology/approachIn the proposed approach, in which the two-dimensional mesh topology has been used as base construction, the mapping operation is divided into two stages as follows: allocating the tasks to suitable cores of intellectual property; and plotting the map of these cores in a specific tile on the platform of NoC.FindingsThe proposed method has dramatically improved the related problems and limitations of meta-heuristic algorithms. This algorithm performs better than the particle swarm optimization (PSO) and genetic algorithm in convergence to the Pareto, producing a proficiently divided collection of solving ways and the computational time. The results of the simulation also show that the delay parameter of the proposed method is 1.1 per cent better than the genetic algorithm and 0.5 per cent better than the PSO algorithm. Also, in the communication cost parameter, the proposed method has 2.7 per cent better action than a genetic algorithm and 0.16 per cent better action than the PSO algorithm.Originality/valueAs yet, the MOPSO-CD algorithm has not been used for solving the task mapping issue in the NoC.

Improved Ant Colony Algorithm Based on Task Scale in Network on Chip (NoC) Mapping

Multi-core processors integrate with multiple computing units on one chip. This technology is increasingly mature, and communication between cores has become the largest research hotspot. As the number of cores continues to increase, the humble bus structure can no longer play the role of multi-core processors. Network on chip (NoC) connects components through routing, which greatly enhances the efficiency of communication. However, the communication power it consumes and network latency are issues that cannot be ignored. An efficient mapping algorithm is an effective method to reduce the communication power and network latency. This paper proposes a mapping method. First, the task is divided depending on the scale of the task. When the task scale is small, to reduce the communication distance between resource nodes, a given NoC substructure is selected to map the task; when the task scale is large, to reduce the communication between tasks, the tasks are clustered and tasks with dependencies are divided into the same resource node. Then combine with an improving ant colony algorithm (ACO) for mapping. The method proposed is being experimentally verified on NoC platforms of different scales. The experimental results show that the method proposed is very effectual for reducing communication power and network latency during NoC mapping.

Application mapping to mesh NoCs using a Tabu-search based swarm optimization

A hybrid optimization scheme is presented that combines Tabu-search, communication volume based core swapping and Discrete Particle Swarm Optimization (DPSO) for NoC (Network-on-Chip) mapping. The main goal of the optimization is to map an application core-graph such that the overall communication latency of the NoC is minimal. It is assumed that the target NoC has a 2D-mesh topology. DPSO is used as the main optimization technique where each swarm particle move is influenced by the global and local best, previous visited search space locations, and a deterministic method to reduce communication volume of existing mapping. We employ a Tabu-list to discourage swarm particles to re-visit the explored search space and propose an alternative direction towards the intended movement direction. The methodology is tested for some multimedia applications as well as randomly generated large network of synthetic cores-graphs. For larger applications, our hybrid scheme generates high quality NoC mapping solutions as compared to DPSO based existing techniques.

Models of computation for NoC mapping: Timing and energy saving awareness

A complex application implemented as a System-on-Chip (SoC) demands extensive system level modeling. Its implementation encompasses a large number of cores and an advanced interconnection scheme such as a Network-on-Chip (NoC). This type of application normally requires energy efficiency and execution time minimization, which implies high-level exploration for cores/tasks placement into the target architecture. A Model of Computation (MoC) captures some characteristics of the applications aiming to fulfill high-level explorations. This work analyzes MoCs employed on the static and dynamic mapping of applications onto regular NoCs, providing a classification based on aspects of computation and communication. Additionally, this paper discusses advantages and drawbacks of these MoCs, such as the complexity of capturing application aspects, as well as the mapping quality. Finally, this work implements the five MoCs more applied on the mapping and compares them applying a benchmark composed of synthetic and embedded applications running on various NoC sizes.

A Classification and Evaluation Framework for NoC Mapping Strategies

Network on Chip (NoC) is a new communication medium used for systems-on-chip (SoCs). In an SoC, the placement of the communicating elements across the network has an impact on system performance. Such a placing is called the MAPPING phase in networks on chip design process. Many approaches dealing with the mapping phase have been proposed but selecting the best technique for a given NoC remains a challenging problem. This paper attempts to provide an answer to this issue. It motivates and presents a definition and a classification according to some criteria: (i) the algorithms used for solving the mapping problem, (ii) the moment in which the mapping is executed, (iii) the impact of combining mapping with other phases during NoC design and (iv) the target architecture.

Performance-driven assignment and mapping for reliable networks-on-chips

Network-on-chip (NoC) communication architectures present promising solutions for scalable communication requests in large system-on-chip (SoC) designs. Intellectual property (IP) core assignment and mapping are two key steps in NoC design, significantly affecting the quality of NoC systems. Both are NP-hard problems, so it is necessary to apply intelligent algorithms. In this paper, we propose improved intelligent algorithms for NoC assignment and mapping to overcome the drawbacks of traditional intelligent algorithms. The aim of our proposed algorithms is to minimize power consumption, time, area, and load balance. This work involves multiple conflicting objectives, so we combine multiple objective optimization with intelligent algorithms. In addition, we design a fault-tolerant routing algorithm and take account of reliability using comprehensive performance indices. The proposed algorithms were implemented on embedded system synthesis benchmarks suite (E3S). Experimental results show the improved algorithms achieve good performance in NoC designs, with high reliability.

Pareto optimal mapping for tile-based network-on-chip under reliability constraints

Mapping for network-on-chip (NoC) is one of the key steps of NoC design. To improve the performance and reliability of NoC architectures, we present a comprehensive optimization algorithm with multiple objectives. We propose to find the Pareto optimal solutions, rather than a single solution usually obtained through scalarization, e.g. weighting the objective functions. In order to meet the NoC mapping requests and strengthen the capability of searching solutions, the standard particle swarm optimization (PSO) algorithm is improved and a fault-tolerant routing is proposed. These methods help to solve the tradeoff between high performance and system reliability. We present a mathematical analysis of the convergence of the improved algorithms, and prove sufficient conditions of convergence. The improved algorithms are implemented on the Embedded Systems Synthesis Benchmarks Suite (E3S). Experimental results show our algorithms achieve high performance and reliability compared with the standard PSO.

A multiobjective scatter search algorithm for fault-tolerant NoC mapping optimisation

Mapping IP cores to an on-chip network is an important step in Network-on-Chip (NoC) design and affects the performance of NoC systems. A mapping optimisation algorithm and a fault-tolerant mechanism are proposed in this article. The fault-tolerant mechanism and the corresponding routing algorithm can recover NoC communication from switch failures, while preserving high performance. The mapping optimisation algorithm is based on scatter search (SS), which is an intelligent algorithm with a powerful combinatorial search ability. To meet the requests of the NoC mapping application, the standard SS is improved for multiple objective optimisation. This method helps to obtain high-performance mapping layouts. The proposed algorithm was implemented on the Embedded Systems Synthesis Benchmarks Suite (E3S). Experimental results show that this optimisation algorithm achieves low-power consumption, little communication time, balanced link load and high reliability, compared to particle swarm optimisation and genetic algorithm.