Netlist Structure Research Articles

Low Cost Functional Obfuscation of Reusable IP Cores Used in CE Hardware Through Robust Locking

Intellectual property (IP) cores used in consumer electronics devices mandate protection against reverse engineering (RE) attacks. Functional obfuscation protects the design functionality by enhancing the complexity of RE attacks. This paper proposes a novel low cost (based on power-delay tradeoff) functional obfuscation methodology through employment of robust IP locking technique. In the proposed obfuscation methodology, several strong multipairwise secure IP locking block designs are presented that can only be actuated through application of valid serial key bits. As demonstration, this paper also shows a practical example of a functional obfuscated netlist structure of FIR filter. Proposed obfuscation on comparison with a recent approach for several DSP cores yielded a power reduction of ~10%, design cost reduction ~ 6.5% and security enhancement (strength of obfuscation) of $>\,\,4.29\,\,{e+9}$ times.

A study of netlist structure and placement efficiency

In this paper, we examine the relationship between netlist structure and the efficiency of placers measured in terms of quality and stability of results. We analyze three types of placers: analytic, simulated-annealing based, and partition based. We have tested these placers on industrial and synthetic benchmarks. Based on our observations and analyzes of experimental results, we draw several useful conclusions: 1) Various placers favor netlists with different structural characteristics; 2) placement efficiency correlates with interconnection complexity of the circuits; 3) global nets increase the effort to eliminate overlaps of cells and degrade the efficiency of analytic placers; and 4) global nets can improve placement stability of partition-based placers.

Measurements for structural logic synthesis optimizations

Routability or wiring congestion in a very large scale integration chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. Although advances in placement algorithms have attempted to alleviate this problem, the inherent structure of the logic netlist has a significant impact on the routability irrespective of the placement algorithm used. Placement algorithms find optimal assignments of locations to the logic and do not have the ability to change the netlist structure. Significant decisions regarding the circuit structure are made early in synthesis during the technology-independent logic-optimization step. Optimizations in this step use literal count as a metric for optimization and do not adequately capture the intrinsic entanglement of the netlist. Two circuits with identical literal counts may have significantly different congestion characteristics after placement. In this paper, we postulate that a property of the network structure called adhesion can make a significant contribution to routing congestion. We then provide a metric to measure this property. We evaluate the utility of adhesion as measured by this metric to estimate and optimize postrouting congestion early in the design flow. A heuristic for measuring adhesion is evaluated as well.