NetFPGA Platform Research Articles

Enhancing TCP via Hysteresis Switching: Theoretical Analysis and Empirical Evaluation

In this paper we study the relationship between the TCP packet loss cycle and the performance of time-sensitive traffic in data centers. Using real traffic measurements and analysis, we find that such loss cycles are not long enough to enable most partition-aggregate time-sensitive TCP applications to recover their packet losses via the TCP 3-dup ACKs mechanism. As a result, the Timeout (RTO) mechanism is frequently triggered, leading to the expansion of the flow completion times (FCT) of such applications by orders of magnitude. Hence, we seek an alternative method that does not change the virtual machines and that can effectively expand the loss cycle duration to enable short flows to finish their transfer without incurring the cost of the RTO. To this end, we propose a novel TCP-AQM mechanism that alternates between a slow constant bitrate (CBR) mode and a fast TCP rate via hysteresis switching to expand the loss cycle. We prove the stability of the proposed TCP-AQM via a control theoretic model, then evaluate its performance gains via small and large scale NS2 simulation and by real FPGA implementation of a prototype on the NetFPGA platform. The results show considerable improvements in FCT distribution and reduction of missed deadlines in simulation and real experiments.

High‐performance anomaly intrusion detection system with ensemble neural networks on reconfigurable hardware

SummaryIn this article, we propose an ensemble neural network approach so that multiple neuron network models can be deployed concurrently for detecting anomalies in a system. Additionally, a high‐performance architecture integrating the neural networks for reconfigurable hardware is also designed to exploit the parallelism of the technology. We carefully implement four different models for detecting SYN, DNS, UNP, and ICMP attacks with the same configuration of neural networks on the NetFPGA platform. The neural networks can be executed in the pipeline to improve performance. Experiments with the generated dataset are conducted to test both performance in terms of throughput and accuracy. Our experimental results show that the system can process packets with throughput up to 30.48Gbps and is able to recognize 99.98% attacking packets with only 0.98% false alarms.

BloomTime: space-efficient stateful tracking of time-dependent network performance metrics

Network monitoring is essential to tasks ranging from planning to troubleshooting. Unfortunately, comprehensive real-time monitoring of complex networks with large traffic volume is challenging. In particular, tracking of time-dependent metrics, such as round-trip latency or transmission rate requires maintaining state and this is hard to scale. We propose BloomTime: a network monitoring primitive in hardware that employs standard bloom filters to approximately track the times between packets. We have prototyped BloomTime on the NetFPGA platform. As a use case, we use BloomTime to monitor the mean and variance of packet inter-arrival times. We have compared BloomTime against end-host measurements and a centralized solution using classic stateful monitoring. We show that BloomTime can monitor 70 times more flows than the traditional stateful approach with approximation errors below 20%. BloomTime was validated in a realistic test environment using real traces. We show that BloomTime can monitor simultaneously 2000 flows on the NetFPGA 1G board (first generation) with 4 MB of SRAM.

Analysing and improving convergence of quantized congestion notification in Data Center Ethernet

Quantized Congestion Notification (QCN) has been approved as the standard congestion management mechanism for the Data Center Ethernet (DCE). However, lots of work pointed out that QCN suffers from the problem of unfairness among different flows. In this paper, we found that QCN could achieve fairness, merely the convergence time to fairness is quite long. Thus, we build a convergence time model to investigate the reasons of the slow convergence process of QCN. We validate the precision of our model by comparing with experimental data on the NetFPGA platform. The results show that the proposed model accurately well characterizes the convergence time to fairness of QCN. Based on the model, the impact of QCN parameters, network parameters, and QCN variants on the convergence time is analysed in detail. Results indicate that the convergence time of QCN can be decreased if sources have the same rate increase probability or the rate increase step becomes larger at steady state. Enlightened by the analysis, we proposed a mechanism called QCN-T, which replaces the original Byte Counter and Timer at sources with a single modified Timer to reduce the convergence time. Finally, evaluations show great improvements of QCN-T in both convergence and stability.

The hardware and software co-design of a configurable QoS for video streaming based on OpenFlow protocol and NetFPGA platform

In order to guarantee the Quality of Service (QoS) requirements of multimedia network, based on the concept of Software Defined Networking (SDN) and OpenFlow protocol, this paper presents the hardware and software co-design of a configurable QoS scheme for video streaming. Specifically, we present the architecture of an OpenFlow switch where the allocated network bandwidth for each multimedia traffic can be dynamically configured by the SDN controller. The detailed structures of software and hardware components are illustrated in this paper. For proof of concept, we realize the proposed switch based on a System on Chip (SoC) platform. We first implement a basic OpenFlow switch based on the state-of-the-art NetFPGA-CML platform. This design occupies 40% of total resources, and is promising for further researches and developments of multimedia networks. We realize the proposed OpenFlow switch with configurable QoS on this platform and carry practical experiments and measurements. The experimental results show that the proposed configurable QoS scheme enhances the QoS and received PSNR of the video streaming.

A source-controlled data center network model.

The construction of data center network by applying SDN technology has become a hot research topic. The SDN architecture has innovatively separated the control plane from the data plane which makes the network more software-oriented and agile. Moreover, it provides virtual multi-tenancy, effective scheduling resources and centralized control strategies to meet the demand for cloud computing data center. However, the explosion of network information is facing severe challenges for SDN controller. The flow storage and lookup mechanisms based on TCAM device have led to the restriction of scalability, high cost and energy consumption. In view of this, a source-controlled data center network (SCDCN) model is proposed herein. The SCDCN model applies a new type of source routing address named the vector address (VA) as the packet-switching label. The VA completely defines the communication path and the data forwarding process can be finished solely relying on VA. There are four advantages in the SCDCN architecture. 1) The model adopts hierarchical multi-controllers and abstracts large-scale data center network into some small network domains that has solved the restriction for the processing ability of single controller and reduced the computational complexity. 2) Vector switches (VS) developed in the core network no longer apply TCAM for table storage and lookup that has significantly cut down the cost and complexity for switches. Meanwhile, the problem of scalability can be solved effectively. 3) The SCDCN model simplifies the establishment process for new flows and there is no need to download flow tables to VS. The amount of control signaling consumed when establishing new flows can be significantly decreased. 4) We design the VS on the NetFPGA platform. The statistical results show that the hardware resource consumption in a VS is about 27% of that in an OFS.

Traffic Aware Energy Efficient Router: Architecture, Prototype and Algorithms

Energy efficient routers are important and promising devices in the roadmap toward green networking. In this paper, we explore this topic with a traffic aware design that can automatically adapt the router’s energy consumption to the network traffic in real time with transitions at the scale from microseconds to nanoseconds. In this paper, we make three contributions. First, we propose an energy efficient router architecture using frequency scaling, which is extended from the contemporary line card architecture of the router. Second, we prototype our architecture on a gigabit NetFPGA platform, which extends a router design on that platform to dynamically work at six frequencies. Then, we discuss the implementation in detail and present a per-packet-based power consumption model from real-world measurements. Third, we further propose four algorithms, which efficiently and automatically adapt power grades under the methodology of periodical and threshold-based scaling. Our experiments are carried out on two platforms, a NetFPGA prototype for feasible scenarios and a simulator for other scenarios in excess of the NetFPGA port limit with parameters synthetically generated to the real-world measurement. Experimental results show that approximately 25% power can be saved with our architecture and algorithms. Conclusions are also given to summarize our findings.

CQ Ethernet Switch Implementation on the NetFPGA Platform

In this paper, we present an original design for an Ethernet switch with crosspoint-queued crossbar switching fabric and analyze its performance. Recently, significant progress has been made on performance analysis of crosspoint queued crossbar switches using analytical and simulation methods. We propose a hardware implementation on the NetFPGA platform that can provide reliable results obtained in an experimental environment. It is shown that the proposed design performs as expected and outperforms reference design under some incoming traffic conditions.

Measure and Evaluate Delay Time for Wakeup on Lan (Wol) Method of OpenFlow Switch

Currently, there are many ways to save energy for the switch such as change the operating modes to low power modes: <i>SLEEP PORT</i> and <i>SLEEP SWITCH</i> when there is no traffic flowing through the Ethernet ports. The switch will be waked up to normal modes when traffic flows pass through it. However, the changes of the modes of the OpenFlow Switch will create DELAY-TIME. If we know DELAY-TIME, then we will make routing algorithms and get appropriately mechanisms to ensure no impact on the transmission of data and loss packets. In this paper, we propose a remedy to measure and evaluate DELAY-TIME when we use the Wakeup On Lan (WOL) method for OpenFlow switch based on NetFPGA platform.

Sliding Mode Congestion Control for Data Center Ethernet Networks

Recently, Ethernet is enhanced as the unified switch fabric of data centers, called data center Ethernet. One of the indispensable enhancements is end-to-end congestion management, and currently quantized congestion notification (QCN) has been ratified as the corresponding standard. However, our experiments show that QCN suffers from large oscillations of the queue length at the bottleneck link such that the buffer is emptied frequently and accordingly the link utilization degrades, with certain system parameters and network configurations. This phenomenon is corresponding to our theoretical analysis result that QCN fails to enter into the sliding mode motion (SMM) pattern with certain system parameters and network configurations. Knowing the drawbacks of QCN and realizing the advantage that congestion management system is insensitive to the changes of parameters and network configurations in the SMM pattern, we present sliding mode congestion control (SMCC), which can enter into the SMM pattern under any conditions. SMCC is simple, stable, fair, has short response time, and can be easily used to replace QCN because both of them follow the framework developed by the IEEE 802.1Qau work group. Experiments on the NetFPGA platform show that SMCC is superior to QCN, especially when traffic pattern and network states are variable.

Energy saving for OpenFlow switch on the NetFPGA platform based on queue engineering.

Data centers play an important role in our daily activities. The increasing demand on data centers in both scale and size has led to huge energy consumption that rises the cost of data centers. Besides, environmental impacts also increase considerably due to a large amount of carbon emissions. In this paper, we present a design aimed at green networking by reducing the power consumption for routers and switches. Firstly, we design the Balance Switch on the NetFPGA platform to save consumed energy based on Queue Engineering. Secondly, we design the test-bed system to precisely measure the consumed energy of our switches. Experimental results show that energy saving of our switches is about 30% - 35% of power consumption according to variation of input traffic compared with normal Openflow Switch. Finally, we describe performance evaluations.

Phase Plane Analysis of Quantized Congestion Notification for Data Center Ethernet

Currently, Ethernet is being enhanced to become the unified switch fabric in data centers. With the unified switch fabric, the cost on redundant devices is reduced, while the design and management of data center networks are simplified. Congestion management is one of the indispensable enhancements on Ethernet, and Quantized Congestion Notification (QCN) has just been ratified as the formal standard. Though QCN has been investigated for several years, there exist few in-depth theoretical analyses on QCN. The most possible reason is that QCN is heuristically designed and involves the property of variable structure. The classic linear analysis method is incapable of handling the segmented nonlinearity of the variable structure system. In this paper, we use the phase plane method, which is suitable for systems of segmented nonlinearity, to analyze the QCN system. The overall dynamic behaviors of the QCN system are presented, and the sufficient conditions for the stable QCN system are deduced. These sufficient conditions serve as guidelines toward proper parameters setting. Moreover, we find that the stability of QCN is mainly promised by the sliding mode motion, which is the underlying reason for QCN's stable queue shown in numerous simulations and experiments. Experiments on the NetFPGA platform verify that the analytical results can explain the complex behaviors of QCN.

Analysis of Backward Congestion Notification with Delay for Enhanced Ethernet Networks

At present, companies and standards organizations are enhancing Ethernet as the unified switch fabric for all of the TCP/IP traffic, the storage traffic and the high performance computing traffic in data centers. Backward congestion notification (BCN) is the basic mechanism for the end-to-end congestion management enhancement of Ethernet. To fulfill the special requirements of the unified switch fabric, i.e., losslessness and low transmission delay, BCN should hold the buffer occupancy around a target point tightly. Thus, the stability of the control loop and the buffer size are critical to BCN. Currently, the impacts of delay on the performance of BCN are unidentified. When the speed of Ethernet increases to 40 Gbps or 100 Gbps in the near future, the number of on-the-fly packets becomes the same order with the buffer size of switch. Accordingly, the impacts of delay will become significant. In this paper, we analyze BCN, paying special attention on the delay. We model the BCN system with a set of segmented delayed differential equations, and then deduce sufficient condition for the uniformly asymptotic stability of BCN. Subsequently, the bounds of buffer occupancy are estimated, which provides direct guidelines on setting buffer size. Finally, numerical analysis and experiments on the NetFPGA platform verify our theoretical analysis.

Reducing Power Consumption of Openflow Switch on the NetFPGA Platform

Reducing power consumption of swiontributes to scale down the overall energy neededata centers. In this paper, we propose some nergy saving modes for the OpenFlow switch baseNetFPGA platform, which are LOW-POWER modeSLEEP mode. In normal scenario, switch operatHIGH-POWER mode; however, when the traffic ghrough the switch becomes lower than a cehreshold level, it will be activated in LOW-POmode; moreover, if there is no traffic, it will operaSLEEP mode to save most energy. Experimental rehow excellent evident in energy saving accordinarious ranges of traffic load. Our switch can bout 46.6% of power consumption when runninLOW-POWER mode and up to about 60% if runninSLEEP mode by comparing to HIGH-POWER mode.

Comparative study of power consumption of a NetFPGA-based forwarding node in publish–subscribe Internet routing

Making the Internet more energy efficient is one of the objectives of future Internet research because of the rising energy cost and environmental concerns. As most Internet users are only interested in accessing information and not the physical location of it, there is also active research on evolving the current host-centric network architecture to an information-centric network (ICN) architecture, which also promises better support for security and mobility. This paper focuses on examining the power consumption of a routing node in ICN. It is experimentally demonstrated that the Bloom filter based forwarding node in ICN is more energy efficient than the longest prefix match based forwarding in the current host-centric network. The experiments were conducted on a Bloom filter (zFilter) forwarding node implemented on the open-source NetFPGA platform. The results in the paper show that using identical operation frequency and packet size of 60 bytes, the zFilter consumes less power than the IPv4 reference router by up to 3.5%. By reducing the operational core frequency, the zFilter at 62.5MHz can reduce the total power by 9.9–13.8% and FPGA power by 17.8–26.1% compared to the reference router at 125MHz, while still outperforming the reference router in terms of the packet loss and throughput. In addition, per packet energy consumption is evaluated for the zFilter and it is shown that the zFilter lowers the per packet energy consumption by up to 41.6% when compared with the IPv4 reference router.

Evaluation of Communication Architectures for Switched Real-Time Ethernet

Safety-critical distributed real-time applications operating with strict temporal constraints rely on deterministic networks with low latency and jitter. Traditional fieldbus systems deliver these guarantees, but they have limited compatibility with open infrastructures and limited support for high transmission rates. Ethernet technology rises as a low-cost, high-speed, and ubiquitous alternative to fieldbus systems; however, standard Ethernet requires special arbitration mechanisms to support real-time traffic because of the standard's inherent nondeterministic behavior. This work explores the associated tradeoffs for three different solutions for real-time communication over switched Ethernet. The paper presents and discusses three architectures that modify different network components, enhancing them with additional customized modules to support time-triggered communication based on Network Code. Using the NetFPGA platform as the unified prototyping technology for all the components, we developed an open-source framework to characterize each solution using experimental data for the latency, jitter, throughput, robustness, and cost in logical resources. The results provide insights to help future developers of real-time communication technology decide which components to modify according to the requirements of their applications.

Energy Saving for OpenFlow Switch on the NetFPGA platform Using Multi-Frequency

Improving energy efficiency in switch is becoming an increasingly important research topic. In this paper, we present the lesson gained by experimenting with a power management mechanism aimed at reducing the power consumption. One solution for this problem is to control intelligently the power consumption of switches used in data centers. This paper proposes an extension to OpenFlow switches to support different power saving modes. The extension includes defining new messages in Openflow standard and designing a Clock Controller (CC) on the hardware of switch based on NetFPGA platform to implement a frequency driver of the switch under various ranges of traffic loads. Experimental results demonstrate an excellent energy saving according to different working modes. Our results show that all the functions of the Clock Controller of the designed system are valid, and the designed system is feasible for the switch to save energy.

Reconfigurable Data Planes for Scalable Network Virtualization

Network virtualization presents a powerful approach to share physical network infrastructure among multiple virtual networks. Recent advances in network virtualization advocate the use of field-programmable gate arrays (FPGAs) as flexible high performance alternatives to conventional host virtualization techniques. However, the limited on-chip logic and memory resources in FPGAs severely restrict the scalability of the virtualization platform and necessitate the implementation of efficient forwarding structures in hardware. The research described in this manuscript explores the implementation of a scalable heterogeneous network virtualization platform that integrates virtual data planes implemented in FPGAs with software data planes created using host virtualization techniques. The system exploits data plane heterogeneity to cater to the dynamic service requirements of virtual networks by migrating networks between software and hardware data planes. We demonstrate data plane migration as an effective technique to limit the impact of traffic on unmodified data planes during FPGA reconfiguration. Our system implements forwarding tables in a shared fashion using inexpensive off-chip memories and supports both Internet Protocol (IP) and non-IP-based data planes. Experimental results show that FPGA-based data planes can offer two orders of magnitude better throughput than their software counterparts, and FPGA reconfiguration can facilitate data plane customization within 12 seconds. An integrated system that supports up to 15 virtual networks has been validated on the NetFPGA platform.

Design a Flexible Software Development Environment on NetFPGA Platform

Among numerous embedded platforms, NetFPGA provides developers with a freely programmable FPGA component to design custom functionalities in networking. However, most hardware projects are developed based on reference designs without embedded operating system. For hybrid developments on multi-layers, there will be some difficulties to apply. On the other hand, due to the limited resources on embedded platform, both performance and flexibility need to be concerned on implementation. And for networking processing, it is quite difficult to adjust control parameters without software environment. Therefore, this paper proposes an integrated architecture using PowerPC processor on NetFPGA and embedded Linux operating system on NetFPGA platform. This not only provides developers with an environment for software execution which added more flexibility, but also enhanced the system to provide more applied possibilities on development.

Online NetFPGA decision tree statistical traffic classifier

Classifying online network traffic is becoming critical in network management and security. Recently, new classification methods based on analysis of statistical features of transport layer traffic have been proposed. While these new methods address the limitations of the port based and payload based traffic classification, the current software-based solutions are not fast enough to deal with the traffic of today’s high-speed networks. In this paper, we propose an online statistical traffic classifier using the C4.5 machine learning algorithm running on the NetFPGA platform. Our NetFPGA classifier is constructed by adding three main modules to the NetFPGA reference switch design; a Netflow module, a feature extractor module, and a C4.5 search tree classifier. The proposed classifier is able to classify the input traffics at the maximum line speed of the NetFPGA platform, i.e. 8Gbps without any packet loss. Our method is based on the statistical features of the first few packets of a flow. The flow is classified just a few micro seconds after receiving the desired number of packets.