Neighborhood Pattern Sensitive Faults Research Articles

A Review Paper on Memory Fault Models and its Algorithms

The significance of testing semiconductor memories has grown significantly in the semiconductor industry due to the increased density of modern memory chips. This paper aims to investigate and analyze different types of functional faults present in today's memory technology. These faults include stuck-at faults, transition faults, coupling faults, address decoder faults, and neighborhood pattern-sensitive faults. The paper also delves into the techniques utilized to identify and detect these faults. In particular, the focus is placed on the importance of zero-one, checkerboard, and March pattern tests, which are widely employed to assess functional memory defects at different levels, such as the chip level, array level, and board level. Furthermore, the study provides an in-depth exploration of various test algorithms and thoroughly examines their fault coverage capabilities. Overall, this review paper provides valuable insights into the challenges posed by the dense nature of modern memory chips and offers a comprehensive analysis of functional faults in memory technology. By emphasizing the importance of testing and presenting a detailed exploration of fault detection methods and test algorithms, this study contributes to the advancement of reliable and high-performance memory devices in the electronic industry suggesting that MARCH algorithms outperform others when considering factors like fault coverage, power efficiency, area optimization, and time complexity parameters, making them the preferable choice for reliable and high-performance memory devices in the electronic industry.

Fault Coverage Re-Evaluation of Memory Test Algorithms With Physical Memory Characteristics

A memory fault model (FM) is an abstraction of the physical mechanism of memory failure. When the physical failure mechanisms are not fully represented in FMs, the coverage of the FMs can be different from that of the failure mechanisms. However, it is impractical (or impossible) to model every electrical aspect of the failure mechanisms with one or more FMs. This problem has become even worse with emerging technologies. Thus, in this study, the fault coverage (FC) consequences are investigated when the physical memory characteristics are not properly linked to the FMs or even test algorithms. Three physical characteristics were considered for this exploration: electrical masking, address scrambling, and electrical neighborhoods. To this end, memory fault simulations were performed, and the test algorithms were re-evaluated in terms of FC. Simulations were performed on the 1 kB area of the example SRAM model; three classes of FMs (56 static faults (SFs), 126 dynamic faults (DFs), and 192 neighborhood pattern-sensitive faults (NPSFs)) were simulated for FC evaluation; and March MSS, March MD2, and March 12N were used to re-evaluate the FCs of SFs, DFs, and NPSFs, respectively. From the simulation results, we observed the negative impact of physical characteristics on FC. When masking was considered, FC reductions of 10.72% SFs and 9.52% DFs were observed; when address scrambling was not available, an FC reduction of 80.21% NPSFs was observed. Finally, considering electrical neighborhood changes depending on the physical memory structure, an FC reduction of 41.67% NPSFs was observed.

Fpga Implementation of Active Neighborhood Pattern Sensitive Fault Testing Using Tiling Method

Test structure for Active Neighborhood Pattern Sensitive Fault (ANPSF) in memories with high switching speed is modeled in this paper. Algorithm for ANPSF testing is developed using type-1 neighborhood approach. The type-1 neighborhood, also known as tiling method has one victim and four aggressor cells. It is used to identify the ANPSF effect on base cell by the switching of patterns in the corresponding deleted neighborhood cells. The required test pattern can be generated using a Binary counter, Hamiltonian or Gray pattern generator where the two successive values differ in only one binary digit. The BIST architecture allows to incorporate the hardware required by the user to select the victim and corresponding aggressor cells to test the complete memory. It helps in application of test pattern for the memory circuit under test on user’s choice. The main objective of this model is to develop the architecture for tiling methodology with test pattern generator to detect the transitions in aggressor cells with edge detection technique. The proposed work enables to verify the response of victim cell which may cause a change in value resulting in an active neighborhood pattern sensitive fault scenario. The complete ANPSF model architecture for memory testing is developed using Verilog hardware descriptive language. The process of simulation and synthesis report is validated using Xilinx 14.2 and implemented on Nexys 4 DDR Artix 7 FPGA board.

Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs

Due to their high density, modern DRAMs are very susceptible to the interactions between adjacent cells, which in turn increases the difficulty and complexity of memory testing. In this work, we studied the interaction mechanisms among neighbouring DRAM cells in order to provide an efficient testing solution. According to the open literature, there are two mechanisms responsible for this interaction: leakage currents and cell state transitions. The frequently used Coupling Fault (CF) model is inadequate to model the combined effect of these mechanisms, while testing procedures using the Neighborhood Pattern Sensitive Fault (NPSF) model are not time efficient solutions. Towards this direction, we propose a new fault model, the Neighborhood Leakage and Transition Fault (NLTF) model for DRAMs, which effectively models the faulty behavior related to neighbouring cell interference. In addition, we developed a new test algorithm which is based on the NLTF model, and provides test application time reductions ranging from 68 to 87 percent with respect to the existing testing algorithms in the literature that are capable to cover the NLTFs. Finally, the proposed algorithm is extended to cover NLTFs in word-oriented DRAMs.

Layout-Based Refined NPSF Model for DRAM Characterization and Testing

As dynamic random access memories (DRAMs) are becoming denser with technology scaling, more complex fault behaviors emerge; examples are leakage, coupling effects, and cell neighborhoods interaction. The neighborhood pattern sensitive fault (NPSF) model is suitable to address such faulty behaviors and identify them during the characterization and/or test of new DRAM chips. However, NPSF test algorithms are extremely time-consuming and therefore not economically affordable. In this brief, we show how layout information can be used to refine and significantly simplify the NPSF model and reduce the test time complexity. As a case study, the folded DRAM array is considered. A realistic NPSF model, the $\Delta$ -type neighborhood, is introduced together with a time efficient test algorithm which is more than two-times cheaper than traditional ones. Even when incorporating bit-line influence and word-line coupling effects, along with NPSFs, the test algorithm time complexity almost remains unaltered. Therefore, the proposed approach makes NPSF testing economically affordable, and hence, suitable for the characterization/test of dense DRAMs in the nanoera.

March Test for Static Neighborhood Pattern-Sensitive Faults in Random-Access Memories

A multibackground March test (March-76N) for a model of static neighborhood pattern sensitive faults (NPSFs) in N ´ 1 random-access memories is presented. March-76N is able to cover both simple and linked NPSFs. As any other test dedicated to the NPSFs, March-76N assumes that the storage cells are arranged in a rectangular grid and the mapping from logical addresses to physical cell locations is known completely. With a length of 76N, this March test is more efficient than other published tests dedicated to this model. Ill. 4, bibl. 16, tabl. 4 (in English; abstracts in English and Lithuanian).DOI: http://dx.doi.org/10.5755/j01.eee.119.3.1369

A Programmable Built-in Self-Test for Embedded Memory Cores

A memory test algorithm for detecting neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF), is proposed in this paper. The patterns can also detect all the traditional faults present in the memory array such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs) and address decoder faults. Next, a programmable BIST architecture is designed. The BIST circuit allows the users to select a vast variety of test algorithms based on their choice. The single BIST circuit is capable of testing different types of memory cores embedded in SOC. The proposed BIST circuit is shared among the different memory cores in an SOC. For this purpose, test wrappers for the shared BIST circuits and the memory cores are designed. Finally, a test scheduling algorithm is developed to reduce the overall test time.

An Efficient Built-In Self-Test Algorithm for Neighborhood Pattern- and Bit-Line-Sensitive Faults in High-Density Memories

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories

The authors present test algorithms for go/no-go and diagnostic test of memories, covering neighborhood pattern-sensitive faults (NPSFs). The proposed test algorithms are March based, which have linear time complexity and result in a simple built-in self-test (BIST) implementation. Although conventional March algorithms do not generate all neighborhood patterns to test the NPSFs, they can be modified by using multiple data backgrounds such that all neighborhood patterns can be generated. The proposed multibackground March algorithms have shorter test lengths than previously reported ones, and the diagnostic test algorithm guarantees 100% diagnostic resolution for NPSFs and conventional RAM faults. Based on the proposed algorithms, the authors also present a cost-effective BIST design. The BIST circuit is programmable, and it supports March algorithms, including the proposed multibackground one.

New fault models and efficient BIST algorithms for dual-port memories

The testability problem of dual-port memories is investigated. A functional model is defined, and architectural modifications to enhance the testability of such chips are described. These modifications allow multiple access of memory cells for increased test speed with minimal overhead on both silicon area and device performance. New fault models are proposed, and efficient O(/spl radic/n) test algorithms are described for both the memory array and the address decoders. The new fault models account for the simultaneous dual-access property of the device. In addition to the classical static neighborhood pattern-sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, duplex dynamic neighborhood pattern-sensitive faults (DDNPSF).

Built-in self-test for folded bit-line Mbit DRAMs

In this paper an efficient and comprehensive algorithm for deriving near optimal parallel tests for neighborhood pattern sensitive faults (NPSFs) detection for an arbitrary type of neighborhood is presented. When k is odd (even) it is based on the decomposition of a directed (undirected) k-cube into a minimal number of edge-disjoint tours. The approach considerably simplifies test-pattern generator (TPG) requirements and makes it suitable for implementation on a VLSI chip. The proposed algorithm is utilized to derive a parallel self-test for detection of unidirectional NPSFs in solded bit-line Mbit DRAM chips. An integrated test strategy covers the most typical functional and parametric faults by execution of retention and marginal tests during the parallel test for unidirectional NPSFs detection. Results showed an improved test coverage of k-coupling faults by approximately 10–65% compared to “tiling” method when k varies from 2 to 9. The total chip area expansion is less than 0.5% for Mbit DRAMs. A test length is 1072 N w when a lower bound is 1024 N w, where N w is the number of word-lines. Thus 64 MBit DRAM {8192 × 8192} is tested within a second when the speed of the test clock is 10 MHz.

Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults

State-of-the-art RAM chips are designed with spare rows and columns for reconfiguration purposes. After a RAM chip is reconfigured, physically adjacent spare cells may no longer have consecutive logical addresses. Another aspect that results in distinct logical and physical neighborhoods in RAM's is the scrambling of address lines, necessitated by the need to minimize the overall silicon area and the critical path lengths. Test algorithms used to test reconfigured RAM's and scrambled address RAM's for the detection of physical neighborhood pattern sensitive faults have to consider that the physical and logical neighborhoods are different and that the address mapping of the reconfigured RAM is no longer available. In this paper, we present a test algorithm that detects static five-cell physical neighborhood pattern sensitive faults in reconfigured RAMs and RAMs with scrambled address lines. This algorithm is based on the widely used MSCAN and Marching test algorithms, and requires only O(N[log/sub 2/N]) reads and writes to test an N-bit RAM array.

On-chip testing of random access memories

This article gives an overview of the Built-In Self-Test techniques for stand alone Random-Access Memory chips. It identifies the limitations of the existing fault models and the test algorithms used to test large RAMs. Methods to reduce test time for testing large RAMs are categorized. The article argues that even linear time test algorithms must use architecture and design for testability induced parallelisms to keep the total test time to an acceptable limit. Following that two algorithms are presented that can be used to test large RAMs for neighborhood pattern sensitive faults. Test lengths and test time for application of these algorithms are computed and it is suggested that a microprogrammed controller based scheme be used to implement self-test in stand alone RAMs.

Hypergraph coloring and reconfigured RAM testing

RAM decoders are designed with a view to minimize the overall silicon area and critical path lengths. This can result in designs in which-physically adjacent rows (and columns) are not logically adjacent. Even if physically adjacent rows (and columns) are logically adjacent, there are other issues that preclude the possibility of identical physical and logical addresses. State-of-the-art memory chips are designed with spare rows and spare columns for reconfiguration purposes. After a memory chip is reconfigured, physically adjacent cells may no longer have consecutive logical addresses. Test algorithms used at later stages for the detection of physical neighborhood pattern sensitive faults have to consider the fact that the address mapping of the memory chip is no longer available. We present test algorithms to detect 5-cell and 9-cell physical neighborhood pattern sensitive faults and arbitrary 3-coupling faults, even if the logical and physical addresses are different and the physical-to-logical address mapping is not available. These algorithms have test lengths of O(N[log/sub 3/N]/sup 4/) and O(N[log/sub 3/N]/sup 2/), respectively, for N-bit RAMs, and are especially suited for testing reconfigured DRAMs. They also detect other conventional faults such as stuck-at faults and decoder faults. These test algorithms are based on efficiently identifying all triplets of objects among a group of n objects. We formulated this triplet identification problem as a hypergraph coloring problem, and developed an efficient 3-coloring algorithm that colors the n vertices of a complete uniform hypergraph of rank 3 such that each edge of the hypergraph is trichromatically colored in at most [log/sub 3/n]/sup 2/ coloring steps.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Deterministic tests for detecting singleV-coupling faults in RAMs

We consider the problem of detecting singleV-coupling faults (as defined by Nair, Thatte, and Abraham) inn×1 random-access memories (RAMs). First we derive a lower bound of 2 V−2 nlog2 n+(2 V +3)n on the length of any test that detects all singleV-coupling faults, for 2≤V≤47 andn=2 e whereeɛ{8,...,34}. In the derivation we make use of a family of binary codes which we call (n, θ)-exhaustive codes. We then describe a procedure which, given any (n, V−1)-exhaustive code, constructs a test that detects all singleV-coupling faults, forn≥V>2. Following this approach, optimal (n,1)- and (n, 2)-exhaustive codes are used to construct S2CTEST and S3CTEST, which are efficient tests of length 10n and 4nlog2 n+18n that detect all single 2- and 3-coupling faults, respectively. S3CTEST is roughly five times shorter, for current RAM capacities, than Papachristou and Sahgal's test of length 24n[log2 n]+n. Codes generated according to Tang and Chen are used similarly to construct S4CTEST and S5CTEST, which are tests of approximate length 8.6n(log2 n)1.585 and 9.6n(log2 n)2.322 that detect all single 4- and 5-coupling faults, respectively. S5CTEST has the interesting property of being able to detect all single physical neighborhood pattern-sensitive faults without requiring the mapping from logical cell addresses to physical cell locations. S5CTEST also detects the scrambled pattern-sensitive fault recently proposed by Franklin and Saluja; moreover, the new test is approximately fourteen times shorter (for 1 and 4 Mbit RAMs) than the test they describe.