nc-Si Thin-film Transistors Research Articles

Nano-Crystalline Silicon-Based Bottom Gate Thin-Film Transistor Grown by LTPECVD With Hydrogen-Free He Diluted ${\hbox{SiH}} _{4}$

The bottom-gate nc-Si based thin-film-transistors (TFTs) grown by using the low-temperature plasma-enhanced chemical vapor deposition (LT-PECVD) system with He diluted SiH are demonstrated. With the RF plasma power increasing from 20 to 100 W, the crystalline volume ratio of the nc-Si inside the a-Si:H film significantly increases from 12.5% to 32%, and its deposition rate is also enhanced from 9.5 to 14.5 nm/min. The faster deposition at higher plasma greatly suppresses the residual oxygen content in nc-Si film to 4% or less, which reduces the flat-band shifted voltage of the MOS diode by 2 volts. The increased crystalline volume with suppressed oxide in nc-Si films contribute to the enhanced Hall mobility and conductivity. The nc:Si TFT decreases its threshold voltage from 3.3 V to 2.7 V, and enlarges its field mobility from 0.3 to 1.3 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V-s. The defect density in the nc-Si TFTs further decrease by one order of magnitude to 7.5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> eV, which causes a shrinkage on the sub-threshold operation range to make easier the operation of the nc-Si TFTs entering into the above-threshold regime at lower voltage. The hydrogen-free He diluted SiH growth has shown its compatibility with the conventional recipe for the high-mobility nc-Si TFT fabrication.

Low-temperature fabrication of spiking soma circuits using nanocrystalline-silicon TFTs.

Spiking neuron circuits consisting of ambipolar nanocrystalline-silicon (nc-Si) thin-film transistors (TFTs) have been fabricated using low temperature processing conditions (maximum of 250 °C) that allow the use of flexible substrates. These circuits display behaviors commonly observed in biological neurons such as millisecond spike duration, nonlinear frequency-current relationship, and spike frequency adaptation. The maximum drive capacity of a simple soma circuit was estimated to be approximately 9200 synapses. The effect of bias stress-induced threshold voltage degradation of component nc-Si TFTs on the spike frequency of soma circuits is explored. The measured power consumption of the circuit when spiking at 100 Hz was approximately 12 nW. Finally, the power consumption of the soma circuits at different spiking conditions and its implications on a large-scale system are discussed. The fabricated circuits can be employed as part of a compact multilayer learning network.

Logic Gates and Ring Oscillators Based on Ambipolar Nanocrystalline-Silicon TFTs

Nanocrystalline silicon (nc-Si) thin film transistors (TFTs) are well suited for circuit applications that require moderate device performance and low-temperature CMOS-compatible processing below 250°C. Basic logic gate circuits fabricated using ambipolar nc-Si TFTs alone are presented and shown to operate with correct outputs at frequencies of up to 100 kHz. Ring oscillators consisting of nc-Si TFT-based inverters are also shown to operate at above 20 kHz with a supply voltage of 5 V, corresponding to a propagation delay of &lt;10 μs/stage. These are the fastest circuits formed out of nanocrystalline silicon TFTs to date. The effect of bias stress degradation of TFTs on oscillation frequency is also explored, and relatively stable operation is shown with supply voltages &gt;5 V for several hours.

Submicron Ambipolar Nanocrystalline Silicon Thin-Film Transistors and Inverters

Nanocrystalline silicon (nc-Si) thin-film transistors (TFTs) fabricated at a maximum processing temperature of 250 °C operate with high field-effect mobility compared with amorphous-silicon TFTs. By reducing the oxygen content in the channel layer, ambipolar behavior can be obtained. Two levels of electron-beam lithography are employed to fabricate nc-Si TFTs with nanoscale dimensions that operate without significant short-channel effects for gate lengths down to 200 nm. The TFTs have current-voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> ) characteristics with on-off ratio >; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> at ±1 V drain voltage and low threshold voltage shift. Simulation Program with Integrated Circuit Emphasis (SPICE) software is used to model the TFTs, and it is validated by performing the fit to devices of different dimensions. An inverter constituent of nc-Si TFTs offers high voltage gain (10-12) and frequency response better than 2 MHz. The crowbar current associated with the inverter can be minimized by using an optimized geometry ratio based on the leakage currents of the TFTs. An amplifier circuit is also demonstrated, offering an ac gain in the frequency range of 100 Hz-10 kHz. SPICE simulations of the inverter and amplifier show close agreement with measured data. The fabricated devices are well suited for use in high-density architectures.

Effects of neutral particle beam on nano-crystalline silicon thin films, with application to thin film transistor backplane for flexible active matrix organic light emitting diodes

A novel deposition process for nano-crystalline silicon (nc-Si) thin films was developed using neutral beam assisted chemical vapor deposition (NBaCVD) technology for the application of the thin film transistor (TFT) backplane of flexible active matrix organic light emitting diode (AMOLED). During the formation of a nc-Si thin film, the energetic particles enhance nano-sized crystalline rather microcrystalline Si in thin films. Neutral Particle Beam (NPB) affects the crystallinity in two ways: (1) NPB energy enhances nano-crystallinity through kinetic energy transfer & chemical annealing, and (2) heavier NPB (such as Ar) induces damage & amorphization through energetic particle impinging. Nc-Si thin film properties effectively can be changed by the reflector bias. As increase of NPB energy limits growing the crystalline, the performance of TFT supports this NPB behavior. The results of nc-Si TFT by NBaCVD demonstrate the technical potentials of neutral beam based processes for achieving high stability and reduced leakage in TFT backplanes for AMOLEDs.

High mobility bottom gate nanocrystalline-Si thin-film transistors

We developed high mobility bottom gate nanocrystalline (nc)-Si thin-film transistors (TFTs). nc-Si film was deposited using inductively coupled plasma chemical vapor deposition method on SiNx gate insulator. Because of good film crystallinity and low ion damage, we could get high performance TFT characteristics. Our TFT showed field effect mobility of 9.4cm2 V−1 s−1 for electrons. These results showed that bottom gate nc-Si TFT could be used in applications such as next generation high definition television and organic light-emitting diode display.

Hebbian Learning in Spiking Neural Networks With Nanocrystalline Silicon TFTs and Memristive Synapses

Characteristics similar to biological neurons are demonstrated in SPICE simulations of spiking neuron circuits comprised of submicron nanocrystalline silicon (nc-Si) thin-film transistors (TFTs). Utilizing these neuron circuits and corresponding device models, the properties of a two-neuron network are explored. The synaptic connection consists of a single nc-Si TFT and a memristor whose conductance determines the synaptic weight. During correlated spiking of the pre- and postsynaptic neurons, the strength of the synaptic connection increases. Conversely, it is diminished when the spiking is uncorrelated. This synaptic plasticity and Hebbian learning are essential for performing useful computation and adaptation in large-scale artificial neural networks. The importance of the result is augmented by the fact that these properties are demonstrated using models based on measured data from devices with potential for 3-D integration into a nanoscale architecture with extremely high device density.

Reactive particle beam based deposition process of nano-crystalline silicon thin film at low temperature for the flexible AM-OLED backplane

A novel deposition process for depositing nano-crystalline silicon (nc-Si) thin films at low temperature was developed using reactive particle beam assisted chemical vapor deposition (RPB-CVD) for applications to the thin film transistor (TFT) backplane of flexible active matrix-OLEDs with plastic substrates. During the formation of nc-Si thin films by the RPB-CVD process with a silicon reflector electrode at low temperatures or room temperature, energetic particles could induce the formation of a crystalline phase in polymorphous Si thin films without additional substrate heating. The effects of the incident RPB energy controlled by the reflector bias were confirmed by Raman spectroscopy. The dark conductivity of polymorphous Si thin films increased with increasing reflector bias, whereas the ratio of photo and dark conductivity decreased monotonically. The optical band gap of the Si thin films also could be changed from amorphous to nano-crystalline by controlling the reflector bias. The first results of a primitive nc-Si TFT by RPB-CVD at room temperature demonstrate the technical potential of RPB-based processes as flexible TFT backplanes.

Effect of Drain Bias Stress on Stability of Nanocrystalline Silicon Thin Film Transistors with Various Channel Lengths

We report the electrical stability of bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs) with various channel lengths under drain bias stress for the first time. As the bias stress at the drain terminal increases at a fixed gate bias, the threshold voltage (VTH) shift of the nc-Si TFTs decreases significantly. Under the drain bias stress, the VTH shift decreases with channel length. The smaller VTH shift was analyzed on the basis of the concentration of the channel charge. A high drain bias reduces the carrier concentration near the drain terminal. Also, the ratio of the depleted charges to total charges increases with decreasing channel length due to the drain bias. Thus, a short-channel TFT has a smaller normalized channel charge than a long-channel TFT. A low carrier concentration induces a small number of defect states; thus the VTH shift of a short-channel TFT is smaller than that of a long-channel TFT.

The quantum size effects on the surface potential of nanocrystalline silicon thin film transistors

The impact of the grain size of nc-Si (nanocrystalline silicon) on the surface potential of doped nc-Si TFTs (thin film transistors) is discussed. Quantum size effects cause the change in both band gap and dielectric constant of nc-Si. Numerical calculation of the surface potential in nc-Si TFTs shows that the diameter of nc-Si has a larger effect on the surface potential of nc-Si TFTs. The results demonstrate that, for medium size (7 – 50 nm), the change in the band gap of nc-Si should be considered, whereas, for small size (< 7 nm), the change in the dielectric constant of nc-Si should be considered. A simplified surface potential equation for nc-Si TFTs under strong inversion condition is proposed, and shows good agreement with the original equation via numerical calculation.

Nanocrystalline Silicon Thin-Film Transistor Fabricated without Substrate Heating for Flexible Display

We fabricated nanocrystalline silicon (nc-Si) thin-film transistors (TFTs) without any substrate heating. High quality nc-Si and silicon dioxide films were deposited at room temperature employing an inductively coupled plasma chemical vapor deposition (ICP-CVD) system. For the nc-Si film, a crystalline phase was grown as a columnar structure and the crystalline volume fraction was 27%. On the silicon dioxide film, hydrogen plasma post-treatment was performed, and the electrical characteristics of silicon dioxide film improved owing to charge reduction and the annealing effect. The nc-Si and silicon dioxide films were used for the fabrication of nc-Si TFTs without substrate heating. Although there was no external heating, a mobility of 6.42 cm2·V-1·s-1 was achieved. This result indicates that nc-Si TFTs fabricated without substrate heating may be a suitable devices for a flexible display.

Highly Stable Bottom-Gate Nanocrystalline Silicon Thin Film Transistor Fabricated Employing ICP-CVD

Bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs) were fabricated and evaluated their characteristics and electrical stability under various stress condition. nc-Si with high crystallinity was deposited employing Inductively coupled plasma chemical vapor deposition(ICP-CVD) system. We employed helium gas diluted deposition and all the process temperature was kept under 350oC. We fabricated conventional inverted-staggered nc-Si TFTs. Fabricated nc-Si TFTs showed fine electrical characteristics, such as electrical mobility of 0.64~0.77 cm2/V⋅sec. We investigated its stability through constant-voltage stress and constant-current stress. The threshold voltage shift after 30,000 seconds gate bias (10V) stress was only 0.098V, which is considerably less compared to a-Si:H TFT. Under the static current stress condition, the threshold voltage of the nc-Si TFT was shifted less than that of a-Si:H TFT. It demonstrates that nc-Si TFT exhibit better stability than conventional a-Si:H TFT.

The Effects of Nanocrystalline Silicon Thin Film Thickness on Top Gate Nanocrystalline Silicon Thin Film Transistor Fabricated at 180℃

We studied the influence of nanocrystalline silicon (nc-Si) thin film thickness on top gate nc-Si thin film transistor (TFT) fabricated at 180 ℃. The nc-Si thickness affects the characteristics of nc-Si TFT due to the nc-Si growth similar to a columnar. As the thickness of nc-Si increases from 40 ㎚ to 200 ㎚, the grain size was increased from 20 ㎚ to 40 ㎚. Having a large grain size, the thick nc-Si TFT surpasses the thin nc-Si TFT in terms of electrical characteristics such as field effect mobility. The channel resistance was decreased due to growth of the grain. We obtained the experimental results that the field effect mobility of the fabricated devices of which nc-Si thickness is 60, 90 and 130 ㎚ are 26, 77 and 119 ㎠/Vsec, respectively. The leakage current, however, is increased from 7.2×10?¹? to 1.9×10?? A at V GS =-4.4 V when the nc-Si thickness increases. It is originated from the decrease of the channel resistance.

Absence of defect state creation in nanocrystalline silicon thin film transistors deduced from constant current stress measurements

The authors discuss time and temperature dependences of the shift in threshold voltage (ΔVT) of nanocrystalline silicon (nc-Si) thin film transistors (TFTs) stressed at constant drain currents. In contrast to the behavior of the hydrogenated amorphous silicon (a-Si:H) counterpart, a weak temperature dependence of ΔVT was observed. The results follow the charge trapping model and the predicted stretched-exponential time dependence that saturates at prolonged stress times. In addition, ΔVT does not fit into the thermalization energy concept that was developed based on the defect state creation model for a-Si:H TFTs. The results indicate absence of defect state creation in nc-Si TFTs.

Above-threshold drain current model including band tail states in nanocrystalline silicon thin-film transistors for circuit implementation

A simple analytical expression for the above threshold voltage drain current is derived in nanocrystalline silicon thin-film transistors (TFTs), based on an exponential energy distribution of band tail states. When the characteristic temperature distribution of the band tails is equal to 1.5 times the lattice temperature, the derived expression leads to the basic “quadratic” metal-oxide-semiconductor current expression. By including the impact ionization effect and using the same trap distribution parameters, the model describes adequately the output characteristics of TFTs with different channel dimensions, making the proposed model suitable for the design of circuits with nc-Si TFTs.

Hydrogenation of nanocrystalline Si thin film transistors employing inductively coupled plasma chemical vapor deposition for flexible electronics

We have investigated the plasma hydrogenation effect on a nanocrystalline silicon (nc-Si) thin film transistor (TFT) fabricated by inductively coupled plasma chemical vapor deposition (ICP-CVD) at 150 °C. The top-gate nc-Si TFT showed a mobility of ∼ 6 cm 2/Vs and V th of 8 V. The hydrogenation employing ICP-CVD was performed at 100 °C for 4 min in order to improve the characteristics of nc-Si TFT. The mobility was increased from ∼ 6 cm 2/Vs to 11 cm 2/Vs. The V th of the nc-Si TFTs was decreased to about 6.8 V from 8.1 V. The on-current at the saturation regime also increased by 66% while the off current was increased slightly. The improvement of mobility, threshold voltage and on-current can be attributed to the hydrogen passivation of the Si dangling bonds in the nc-Si film. The experimental results showed that the 100 °C ICP-CVD hydrogenation is effective to improve the 150 °C nc-Si TFT.

High Mobility Nanocrystalline Silicon TFTs for Display Application

AbstractNanocrystalline silicon (nc-Si) thin film transistors (TFTs) of which active layer thickness was 100nm were fabricated using inductively coupled plasma chemical vapor deposition (ICP-CVD) at 150°C. The fabricated nc-Si TFT exhibits rather high field effect mobility exceeding 22cm2/Vs and excellent sub-threshold slope of 0.45V/dec. The nc-Si film deposited 150°C as an active layer of the TFT shows high crystallinity more than 70% and very thin incubation layer less than 20nm. ICP-CVD provides high density plasma with reduced ion bombardment during the deposition on nc-Si and He dilution can enhance the decomposition of SiH4 into Si, SiHX radicals and atomic H, so that high quality nc-Si film can be fabricated. The gate insulator SiO2 film deposited by ICP-CVD at 150°C shows good electrical characteristics such as flat band voltage of -1.8V and breakdown voltage of 6.2MV/cm.

Hot-Wire Deposited Nanocrystalline Silicon TFTs on Plastic Substrates

AbstractHot-wire chemical vapor deposition (HWCVD) technique was used to deposit nanocrystalline silicon (nc-Si) thin film transistors (TFT) on thin polyimide sheets. Two straight tantalum filaments at 1850°C with a substrate to filament distance of 4 cm was used to deposit HWCVD nc-Si with no thermal damage to plastic sheet. Top-gate staggered TFTs were fabricated at 150°C and 250°C using a HWCVD nc-Si channel, PECVD silicon nitride gate dielectric, and microcrystalline n+ drain/source contacts. Leakage current of 3.3×10-12 A, switching current ratio of 3×106, and sub threshold swing of 0.51 V/decade were obtained for TFTs with aspect ratio of 1400 µm / 100 µm fabricated at 150°C. The highest electron field effect mobility was found to be 0.3 cm2/V.s observed for TFTs deposited at lower substrate temperature. Measurements showed superior threshold voltage stability of HW nc-Si TFTs over their amorphous silicon (a-Si) counterparts.

Analytical current-voltage model for nanocrystalline silicon thin-film transistors

An analytical model for the drain current above threshold voltage, based on an exponential energy distribution of band tail states, has been applied to bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors (TFTs). Analysis of the model shows that the slope of the exponential band tails determines the behavior of the device current-voltage characteristics. Comparison with experimental data shows that few fundamental model parameters, related to the material quality and different physical effects, can be used to describe consistently both output and transfer characteristics of nc-Si TFTs over a wide range of channel lengths.