Narrow Width Devices Research Articles

Defect spectroscopy of sidewall interfaces in gate-all-around silicon nanosheet FET

Through time-dependent defect spectroscopy and low-frequency noise measurements, we investigate and characterize the differences of carrier trapping processes occurred by different interfaces (top/sidewall) of the gate-all-around silicon nanosheet field-effect transistor (GAA SiNS FET). In a GAA SiNS FET fabricated by the top-down process, the traps at the sidewall interface significantly affect the device performance as the width decreases. Compare to expectations, as the width of the device decreases, the subthreshold swing (SS) increases from 120 to 230 mV/dec, resulting in less gate controllability. In narrow-width devices, the effect of traps located at the sidewall interface is significantly dominant, and the 1/f 2 noise, also known as generation–recombination (G–R) noise, is clearly appeared with an increased time constant (τ i ). In addition, the probability density distributions for the normalized current fluctuations (ΔI D) show only one Gaussian in wide-width devices, whereas they are separated into four Gaussians with increased in narrow-width devices. Therefore, fitting is performed through the carrier number fluctuation-correlated with mobility fluctuations model that separately considered the effects of sidewall. In narrow-width GAA SiNS FETs, consequently, the extracted interface trap densities (N T ) distribution becomes more dominant, and the scattering parameter () distribution increases by more than double.

Origin of the channel width dependent field effect mobility of graphene field effect transistors

A model to explain the origin of channel width dependent field effect mobility is proposed. According to our model accounting the effect of non-uniform carrier transport in a graphene channel, the field effect mobility of wide channel graphene FET has been severely underestimated as much as two times, even without accounting the fringing field effect. Based on our model, we propose a more accurate protocol to extract the field effect mobility of graphene FET involving the use of narrow channel width devices.

Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits

Strain engineering and inverse narrow width effect (INWE) are among the main causes of layout-dependent variations in narrow width devices. Transistor sizing and layout without considering these effects at a prelayout stage may result in suboptimal design and design/layout iterations. In this paper, we model the channel stress variations in multifinger gate structure (MFGS) empirically using 3-D technology computer aided design simulations. Thereafter, we use these stress models along with a model for INWE to establish a physics-based relationship between effective drive current and number of fingers in MFGS. We also design single-stage combinational standard cells and predict the values of their logical effort using our approach. The performance of the standard cells using our approach improves significantly compared with the conventional approach. Inverter chains (buffers) are representative and extensively used multistage circuits. Using our model of effective drive current, we propose a methodology to optimize the buffer designed and layout to maximize performance in stress-enabled technologies. We observe that the proposed methodology results in a significant reduction in power dissipation up to 35% and reduction in silicon area up to 43% as compared with the existing methodologies.

SiGe channel deposition by batch epitaxy

Batch epitaxy has been introduced for high volume manufacturing of SiGe channels in order to reduce the cost for this epitaxial process by a factor of 3. Beside cost, SiGe channel deposition by batch epitaxy offers many benefits for manufacturing. The stability of the process and the reduced variability of the SiGe thickness greatly improve the variation of VT. The batch epitaxy process does not show a pattern loading effect for SiGe thickness reducing the complexity for manufacturing significantly. However, since the tool concept is very different to that of the widely used single wafer tools, there are some tool specific issues that need to be managed. The wafer backside is critical for batch epitaxy. A nitride backside facing the front side of the wafer results in a clear degradation of the uniformity and a change of the morphology of the SiGe channel compared to that facing a Si backside. The thermal rounding is more pronounced for the channels deposited in a batch tool for both large and narrow width devices. The device parameters of the large width device are not affected by thermal rounding but the performance of the narrow width device is clearly degraded. The thin SiGe layer at the edge of the channel driven by thermal rounding affects the VT and thus the effective device width. An in-situ etching before SiGe deposition to avoid thermal rounding was not feasible due to defects issues which were induced by the wafer backside. Finally a thermal rounding of the Si by an aggressive H2 bake before SiGe deposition improves the SiGe channel uniformity and recovers the performance degradation of the narrow width device partly.

The Enhanced Role of Shallow-Trench Isolation in Ionizing Radiation Damage of Narrow Width Devices in 0.2 μm Partially-Depleted Silicon-on-Insulator Technology

An anomalous total dose effect is observed in narrow-width devices fabricated in a 0.2 μm partially-depleted silicon-on-insulator (SOI) technology. The previous radiation-induced narrow channel effect manifests itself with obvious threshold voltage shift after the transistors are subjected to total dose radiation in bulk technology. Nevertheless, a sharply increasing off-state leakage current dominates the total dose effects in narrow devices of this partially-depleted SOI technology instead of threshold voltage shifts. A radiation-induced positive charge trapping model is introduced to understand this phenomenon. The enhanced role of shallow-trench oxide induced by compressive mechanical stress in narrow devices is discussed in detail in terms of modification of the edge impurity density and charge trapping characteristics, which affect the total dose sensitivity.

The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design

In this work we investigate the impact of process-induced mechanical stress in narrow width devices and its implication on circuit design. We observe that the channel stress and hence drive strength of narrow width devices significantly depend upon the width of a device. We present a model for estimating width dependent channel stress and effective drive current in strain engineered devices. Width dependent change in drive strength causes WP/WN ratio (also referred to as ‘β’) in inverters to change with inverter scaling factor ‘S’. If not accounted for, this results into a suboptimal circuit design and unaccounted change in performance. Finally, considering the narrow width effects (NWEs), we propose a model to design variable-taper CMOS buffer. In our model the taper factor from one inverter stage to the next is a variable and depends upon the location of an inverter in the buffer chain. We observe that buffer designed using our model takes less area, consumes less power and gives marginal improvement in delay also.

Channel width dependence of mechanical stress effects induced by shallow trench isolation on device performance of nanoscale nMOSFETs

Channel width dependence of mechanical stress effects on a nanoscale n-channel metal–oxide-semiconductor field-effect transistor using the shallow trench isolation (STI) is investigated. The results indicate that the mechanical stress induced by the STI enhances mobility, off currents, and the impact ionization significantly. 841MPa of tensile stress is extracted using the subthreshold current method. In addition, the off-state stress is measured at 125°C, and the narrow width device is more seriously degraded than wide width devices.

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

The impact of device width on the variability of radiation-induced leakage currents in 90nm and 65nm CMOS technologies is investigated. The off-state leakage current variability increases with decreasing channel width for both technologies, and with increasing total ionizing dose for three different process variants from the 90nm technology. More variability is observed for narrow width devices compared to wider devices before and after irradiation. Device-to-device variability is compared for two technologies (65 and 90nm) and three process variants (low, standard, and high threshold voltage). These results illustrate the importance of process-induced variability on the radiation response of MOS devices and integrated circuits.

Trade-Offs Between RF Performance and Total-Dose Tolerance in 45-nm RF-CMOS

The hot carrier and ionizing radiation responses of 45-nm SOI RF nMOSFETs are investigated. Devices with “tight” source/drain (S/D) contact spacing have improved RF performance but degraded hot carrier reliability and radiation tolerance. Devices with “loose” gate finger-to-gate finger spacing have improved RF performance and also improved hot carrier and radiation tolerance. The effects of finger width on the hot carrier stress and ionizing radiation degradation of strained silicon-on-insulator RF MOSFETs are also investigated. Enhanced degradation is observed for devices with wide finger widths and is attributed to the greater channel-region mechanical stress induced impact ionization. This result is contrary to the previous studies which showed that narrow channel width devices should exhibit greater damage. Taken together, these results have serious consequences for RF circuits that require large widths for sufficient RF gain. Finally, devices with symmetric halo doping are observed to exhibit greater total-dose degradation than devices with asymmetric halo doping.

Total ionizing dose effect in an input/output device for flash memory

Input/output devices for flash memory are exposed to gamma ray irradiation. Total ionizing dose has been shown great influence on characteristic degradation of transistors with different sizes. In this paper, we observed a larger increase of off-state leakage in the short channel device than in long one. However, a larger threshold voltage shift is observed for the narrow width device than for the wide one, which is well known as the radiation induced narrow channel effect. The radiation induced charge in the shallow trench isolation oxide influences the electric field of the narrow channel device. Also, the drain bias dependence of the off-state leakage after irradiation is observed, which is called the radiation enhanced drain induced barrier lowing effect. Finally, we found that substrate bias voltage can suppress the off-state leakage, while leading to more obvious hump effect.

Effective Edge Width for 65-nm pMOSFETs and Their Variations Under CHC Stress

The narrow-width W effect of metal-oxide-semiconductor field-effect transistors (MOSFETs) with shallow trench isolation technology has been widely reported. The factor of most concern is the edge width Δw affecting the electrical characteristics of the MOSFETs. In this letter, the negative variation value of Δw, as explained in the content, was derived from 65-nm node p-channel MOSFETs (pMOSFETs). To verify the validity of Δw, the pMOSFETs were stressed by channel-hot-carrier stress conditions. According to the experimental results, the device parameter degradation, i.e., the threshold voltage VTH, was obviously dominated by |Δw|/W, and the degradation of the narrow-width device was also increased for the wide width.

NMOS Narrow Width Devices Drive Current Improvements through STI Processes and Channel Implantation Optimization

NMOS narrow width transistor driving current as a function of shallow trench isolation (STI) processes and channel implant conditions were studied on a 65nm CMOS technology. It is found that the magnitude of compressive stress in STI could modulate the trend of NMOS drive current versus width dependence that was attributed to channel dose profile uneven distribution under the influence of stress. It is seen that the channel body effect factor (gamma) of large width (W=10um) transistor is smaller than that of narrow width device (W=0.12um). This difference increases as STI compressive stress scales up. The phenomena are consistent with the analysis that Boron dose distribution varies as STI stress changes. it is shown that the down trend of drive current for narrow width transistors could be minimized by STI process optimization, or by introducing indium implantation during channel implantation processes.

New opportunities for SiGe and Ge channel p-FETs

A thin body (fully depleted) strained SGOI device structure (FDSGOI), and a strained SiGe channel layer on SOI, were fabricated using scaled high- κ gate dielectrics and metal gate technology. The uniaxial strain effect and corresponding drive current enhancement reported by Irisawa et al. [1] for narrow-width devices was investigated on these structures. Although the strained FDSGOI device structure exhibited reduced off-state leakage compared to thicker body devices, and long-channel drive current enhancement under uniaxial strain, the loss of drive current enhancement at short channel length led to uncompetitive I ON– I OFF characteristics. The SiGe on SOI structure showed the highest long-channel drive current enhancement (nearly 3×) in the narrowest devices, and also showed a significant reduction in off-state current. This trend was maintained down to the shortest channel lengths studied here and resulted in I ON– I OFF characteristics that were competitive with contemporary uniaxial strained Si channel devices.

A novel STI etching technology to mitigate an inverse narrow width effect, and improve device performances for 90 nm node and beyond CMOS technology

A new STI (shallow trench isolation) with automatic top corner rounding (ATCR) to improve 90 nm CMOS narrow width device performance has been studied in detail. Experimental results show that the ATCR mitigates the inverse narrow width effect, and increases the driving current (Idsat) by 8% together in a unit process step, thus getting easy process control and cost down benefits, which cannot be achieved through conventional methods. Additionally, the ATCR attained a better trench depth uniformity, and thus a wider process window (20–50 s) than that of the conventional method. Furthermore, the technique does not degrade the gate oxide integrity and junction leakage current; thus the developed ATCR STI technique is more suitable for 90 nm and beyond narrow width CMOS technologies.

The superconducting transition width and illumination wavelength dependence of the response of MgO substrate YBCO transition edge bolometers

Dependence of the phase and magnitude of the response of MgO substrate YBa 2Cu 3O 7− δ (YBCO) transition edge bolometers to the near infrared radiation on the superconducting transition width is presented in this work. The bolometers were made of YBCO thin films of 200 nm thickness that were grown on single crystal MgO (1 0 0) substrates by DC inverted cylindrical magnetron sputtering. We have measured the responses of both large and small area devices with respect to the bias temperature and radiation modulation frequency. We have observed that the superconducting transition width has major effects on the response of the bolometers such as; on a dip of the phase of the response versus modulation frequency curve around 1 Hz, the rate of decrease of the magnitude of the response, and dependence of the phase of the response on temperature at mid-range modulation frequency. We have investigated a correlation between the superconducting transition width and the YBCO film surface morphology of the devices. In addition, the illumination wavelength dependence of the optical response of both wide and narrow transition width devices has been investigated. Here we present the analysis and the possible mechanisms that can affect the response of the bolometers at the superconducting transition region.

Suppression of boron diffusion due to carbon during rapid thermal annealing of SiGe based device materials—some comments

The development of silicon-germanium alloys to extend the range of silicon high-frequency circuits has highlighted the need to understand diffusion mechanisms in this important material. To optimise performance, it is necessary to minimise the diffusion of dopants such as boron, in these very narrow width devices. This paper discusses recent progress in understanding the role of carbon doping in retarding boron diffusion. Much progress in understanding the diffusion mechanisms in silicon has been gained using selective defect injection, building on the discovery in 1972 that broadening of marker layers could monitor the injection of defects. The technique has now been used successfully in silicon-germanium alloys, and has shown that interstitial type defects are responsible for boron diffusion both in SiGe and in SiGe:C. The effects of carbon in retarding boron diffusion in as-grown structures, as well as ion-implanted structures, are discussed.

Characteristics of MOCVD-Grown Thin p-Clad InGaAs Quantum-Dot Lasers

Thin p-clad quantum-dot lasers grown by metal-organic chemical vapor deposition are fabricated and shown to lase in ground state for device lengths greater than 2.5 mm. The device characteristics are presented and the modal behavior is investigated. The threshold current density is found to be much larger for narrow (4 μm) stripe width devices than expected from the wider (50 μm) stripe width devices. This is attributed to gain saturation within the devices.

An anomalous device degradation of SOI narrow width devices caused by STI edge influence

The effects of shallow trench isolation (STI) on silicon-on-insulator (SOI) devices are investigated for various device sizes with three different gate shapes. Both NMOSFETs and PMOSFETs with the channel region butted to the STI show a reduction in mobility (NMOSFETs and PMOSFETs) and an increase of low-frequency noise as the channel width is reduced. In comparison, the devices without the STI-butted channel region show much less variation in mobility for various channel widths. The degradation of MOSFET yield in SOI MOSFETs with the STI is found to be dependent on the device width since the contribution of the interface roughness (or damage) between the STI and the channel formed during the dry etch process becomes significant with the decrease of channel width and the increase of channel length. From the charge-pumping results, the interface state (N/sub it/) generated by the STI process was identified as the cause of the anomalous degradation.

The behavior of narrow-width SOI MOSFETs with MESA isolation

Narrow-width effects in thin-film silicon on insulator (SOI) MOSFETs with MESA isolation technology have been studied theoretically and experimentally. As the channel width of the MOSFET is scaled down, the gate control of the channel potential is enhanced. It leads to the suppression of drain current dependence on substrate bias and punchthrough effect in narrow-width devices. The variation of threshold voltage with the channel width is also studied and is found to have a strong dependence on thickness of silicon film, interface charges in the buried oxide and channel type of SOI MOSFETs.

Hot carrier degradation for narrow width MOSFET with shallow trench isolation

We have investigated the hot carrier reliability characteristics of narrow width MOSFET with shallow trench isolation. In the case of maximum substrate current condition, the lifetime of nMOSFET is slightly degraded by decreasing the device width. However, a significant degradation of device lifetime of the narrow width device was observed under channel hot electron condition ( V g= V d). In the case of pMOSFET, we also found enhanced degradation of narrow width device under channel hot electron condition. Enhanced degradation of MOSFETs can be explained by both the current crowding and enhanced charge trapping at the shallow trench isolation edge. Considering pass transistor in DRAM cell, the degradation of lifetime for narrow width device under high gate bias condition causes a significant impact on circuit reliability.