Narrow Width Devices Research Articles

High-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

In this paper, we demonstrate for the first time a high-performance and high-reliability 80-nm gate-length dynamic threshold voltage MOSFET (DTMOS) using indium super steep retrograde channel implantation. Due to the steep indium super steep retrograde (In SSR) dopant profile in the channel depletion region, the novel In-SSR DTMOS features a low V/sub th/ in the off-state suitable for low-voltage operation and a large body effect to fully exploit the DTMOS advantage simultaneously, which is not possible with conventional DTMOS. As a result, excellent 80-nm gate length transistor characteristics with drive current as high as 348 /spl mu/A//spl mu/m (off-state current 40 nA//spl mu/m), a record-high Gm=1022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7 V operation. Moreover, the reduced body effects that have seriously undermined conventional DTMOS operation in narrow-width devices are alleviated in the In-SSR DTMOS, due to reduced indium dopant segregation. Finally, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS.

Linearity and CNR Improvement Technologies against Optical Reflection inFiber-Oriented Wireless Access Systems

It is important to consider optical reflection conditions when designing fiber-oriented wireless access systems around subcarrier optical transmission since the noise characteristic can be significantly degraded by optical reflection, especially if narrow spectral width devices are used. The superluminescent diode (SLD) offers stable noise and 3rd-order intermodulation distortion (IM3) characteristics that follow the ideal cubic law, even under multiple optical reflection. The SLD-predistorter combination is proposed as a way to overcome the SLD's narrow dynamic range. It is experimentally found that the predistorter reduces IM3 by 8 dB. The receiver sensitivity of a practical system that uses the SLD-predistorter combination is discussed from the viewpoint of overall design. A superimposed subcarrier modulation (SSM) technique is also proposed in order to reduce the reflection noise. We experimentally confirm that the SSM technique reduces the noise degradation and provides stable optical transmission. An SSM design methodology is presented that takes both noise and linearity into account. The SLD-predistorter and the SSM scheme make it possible to realize stable transmission performance and wider dynamic range in the presence of optical reflection.

Channel width dependence of hot-carrier induced degradation in shallow trench isolated PMOSFETs

Channel width dependence of the hot-carrier induced degradation in pMOSFETs with a shallow trench isolation structure is investigated. Enhanced degradation is observed in a narrow channel width device. The narrow width device shows large electron trapping efficiency of the gate oxide film though the gate current is smaller than the wide width device. The mechanical stress caused by shallow trench isolation may be responsible for this phenomenon.

SOI MOSFET with buried body strap by wafer bonding

Although the buried oxide in the silicon-on-insulator (SOI) MOSFET makes possible higher performance circuits, it is also responsible for various floating body effects, including the kink effect, drain current transients, and history dependence of output characteristics. It is difficult to incorporate an effective contact to the body because of limitations imposed by the SOI structure. One candidate, which maintains device symmetry, is the lateral body contact. However, high lateral body resistance makes the contact effective only in narrow width devices. In this work, a buried lateral body contact in SOI is described which consists of a low-resistance polysilicon strap running under the MOSFET body along the device width. MOSFET's with effective channel length of 0.17 /spl mu/m have been fabricated incorporating this buried body strap, showing improved breakdown characteristics. Low leakage of the source and drain junctions demonstrates that the buried strap is compatible with deep submicron devices. Device modeling and analysis are used to quantify the effect of strap resistance on device performance. By accounting for the lateral resistance of the body, the model can be used to determine the maximum allowable device width, given the requirement of maintaining an adequate body contact.

Impact of scaling silicon film thickness and channel width on SOI MOSFET with reoxidized MESA isolation

The characteristics of reoxidized MESA isolation for silicon-on-insulator (SOI) MOSFET have been studied in terms of the dependence of device performance on silicon film thickness and channel width scaling. For devices with silicon film thickness (T/sub Si/) smaller than a critical thickness, humps appear in subthreshold IV and negative threshold voltage shift is observed in narrow width devices. The width encroachment (/spl Delta/W) also increases rapidly with reducing T/sub Si/. These observations can be explained by the formation of sharp beak and accelerated sidewall oxide growth in these devices. A simple guideline is given to optimize the reoxidation process for different T/sub Si/.

Gate width effects on deep level spectra in implanted GaAs MESFETs on LEC substrates

The presence of deep levels in 1 μm gate length GaAs MESFETs has been studied by channel-current deep level transient spectroscopy. Narrow-width devices (10 μm) show only the presence of the EL2 level, while two traps with activation energies of 0.68 eV (hole like) and 0.96 eV, are detected in 40 and 100 μm wide devices. From the above level behavior, it is suggested that the first one reflects electron capture at the GaAs/Si 3N 4 ungated surface, while the second level is a donor center located in, or just below, the same region. In small area devices, the total gate perimeter, rather than the gated to ungated area ratio, appears to be important.

Defect Passivation Kinetics and Small Geometry Effects in Polysilicon Thin Film Transistors

AbstractThe effects of hydrogen plasma passivation on n-channel polycrystalline silicon thin film transistors fabricated with a maximum temperature of 600°C are investigated. It is found that charge, sharing, avalanche multiplication, grain size, and gate edge in-situ passivation or even partial hydrogenation can all contribute to the small geometry effect. At low drain bias, the channel charges supported by the source and drain fringing fields cause threshold shifts for short channel devices; at high drain bias avalanche multiplication is the dominant effect. The charge sharing effect may be related to the unpassivated trap-states in the channel since thresholds of fully hydrogenated devices became independent of channel length at low drain bias. The threshold shifts of narrow width devices were also diminished with increasing hydrogenation time. An anomalous turnaround effect of the field effect mobility in saturation regime for the short channel devices is observed near saturated hydrogenation. This effect is probably due to the passivation of back-channel defects and the reduction in impact ionization rate by hydrogenation. Saturated hydrogenation not only improves device performance but also reduces small geometry effects. Avalanche multiplication remains the dominant mechanism for short channel effect in the saturated hydrogenated devices.

Width dependence of substrate and gate currents in MOSFET's

Width dependence of hot-electron currents in MOSFET's fabricated with LOCOS, non-LOCOS, and a modified LOCOS processes are studied. The experimental results show that the substrate and gate currents are apparently enhanced in narrow width devices. The enhancement, however, is due to different voltage drops across the source-drain series resistance. The voltage drops are usually larger in wider devices. After correcting for the resistance effect, the substrate and gate currents scale with the device width. With this typical LOCOS process, the bird's beak and in-diffusion of field implant dopants do not cause excess hot-electron activities along the channel/field edges as has been suspected. Some other LOCOS process could, of course, produce a different result. Studies using wide test devices must consider the series resistance effect. With this precaution taken, models derived from wide-channel data will be applicable to narrow-channel devices, at least for some processes.

A new method to electrically determine effective MOSFET channel width

A new, easy, and accurate electrical measurement method for determining process bias of MOSFET channel width is proposed. This method is based on the linear relationship between the effective width and the channel conductance (or drain current) of a MOSFET operating in the linear region. Constant and sufficiently high gate voltages compared with the threshold voltage of the device are used in the measurement to minimize the error due to the threshold-voltage variation with W in narrow-width devices. The validity of the method is supported by identical results obtained using different gate voltages.

Fringing Field Effect in MOS Devices

Fringing field action in metal-oxide-semiconductor (MOS) devices is discussed theoretically. Line capacitance coefficients on silicon-on-sapphire (SOS) and bulk configurations are determined from a three-dimensional model. Increase of threshold voltage of narrow-width devices due to fringing is described.