Nanoscale Ge Research Articles

Theoretical Assessment of Impacts of Energy Band Valley Occupation on Diffusion Coefficient of Nano-Scale Ge Wires

The purpose of this paper is to theoretically predict the significant impacts of valley occupation on the overall diffusion coefficient of Ge nanowires physically confined by various surfaces. This paper derives an approximate analytical expression of the diffusion coefficient that exists around room temperature. In Ge wires physically confined by {100} surfaces, the overall diffusion coefficient is, around room temperature, almost constant for wire widths larger than 10 nm. However, a step-like decrease is found for wire widths smaller than 7 nm. This behavior of the overall diffusion coefficient stems from the fall in the L-valley component of diffusion coefficient and the rise of X-valley component of diffusion coefficient for wire widths smaller than 10 nm. The behavior of diffusion coefficient of wires physically confined by {111} surfaces is also investigated around room temperature. The overall diffusion coefficient is almost the same as the diffusion coefficient component of X valley because electrons primarily occupy X valleys. It is clearly revealed that the behavior of the diffusion coefficient is primarily ruled by the valley occupation fraction of electrons in Ge wires. These dominant features of the diffusion coefficient of Ge wires are quite different from those of Si wires. Simulation results are assessed in comparisons with past experimental results and past calculation results. Finally, additional consideration is given from the viewpoint of device applications.

Investigation on Ge0.8Si0.2-Selective Atomic Layer Wet-Etching of Ge for Vertical Gate-All-Around Nanodevice.

For the formation of nano-scale Ge channels in vertical Gate-all-around field-effect transistors (vGAAFETs), the selective isotropic etching of Ge selective to Ge0.8Si0.2 was considered. In this work, a dual-selective atomic layer etching (ALE), including Ge0.8Si0.2-selective etching of Ge and crystal-orientation selectivity of Ge oxidation, has been developed to control the etch rate and the size of the Ge nanowires. The ALE of Ge in p+-Ge0.8Si0.2/Ge stacks with 70% HNO3 as oxidizer and deionized (DI) water as oxide-removal was investigated in detail. The saturated relative etched amount per cycle (REPC) and selectivity at different HNO3 temperatures between Ge and p+-Ge0.8Si0.2 were obtained. In p+-Ge0.8Si0.2/Ge stacks with (110) sidewalls, the REPC of Ge was 3.1 nm and the saturated etching selectivity was 6.5 at HNO3 temperature of 20 °C. The etch rate and the selectivity were affected by HNO3 temperatures. As the HNO3 temperature decreased to 10 °C, the REPC of Ge was decreased to 2 nm and the selectivity remained at about 7.4. Finally, the application of ALE in the formation of Ge nanowires in vGAAFETs was demonstrated where the preliminary Id–Vds output characteristic curves of Ge vGAAFET were provided.

Engineering of effective back-contact barrier of CZTSe: Nanoscale Ge solar cells – MoSe2 defects implication

Using temperature-dependent measurements and device modeling, we systematically study the effective back-contact barrier of CZTSe devices to improve the property of the back-contact interface. By comparing with CZTSe devices with various nanoscale Ge configurations, CZTSe nanoscale Ge bi-layers devices show the improved power conversion efficiency by 1.1%. DC magnetron sputtering is used to fabricate CZTSe: nanolayer Ge devices. Critical device parameters are characterized to understand the impact of nanoscale Ge films on the back-contact device characteristics. Based on empirical results, modeling is performed for the influence of MoSe2 defects on the effective back-contact barrier. Analysis of experimental results of Ge bi-layers devices with the improved back-contact barrier makes a good agreement with modeling and Sentaurus TCAD simulation at the 95% confidence-level. The conversion efficiency of CZTSe: nanoscale Ge bi-layers devices is improved up to 8.3%.

High Thermoelectric Performance Achieved in GeTe–Bi2Te3 Pseudo‐Binary via Van der Waals Gap‐Induced Hierarchical Ferroelectric Domain Structure

AbstractGeTe is an interesting material presenting both spontaneous polarization (ferroelectrics) and outstanding electrical conductivity (ideal for thermoelectrics). Pristine GeTe exhibits classic 71° and 109° submicron ferroelectric domains, and near unity thermoelectric figure of merit ZT at 773 K. In this work, it is demonstrated that Bi2Te3 alloying in GeTe lattice can introduce vast Ge vacancies which can further evolve into nanoscale van der Waals gaps upon proper heat treatment, and that these vacancy gaps can induce 180° nanoscale ferroelectric domain boundaries. These microstructures eventually become a hierarchical ferroelectric domain structure, with size varying from submicron to nanoscale and polarization from 71°, 109° to 180°. The establishment of hierarchical ferroelectric domain structure, together with the nanoscale Ge vacancy van der Waals gaps, has profound effects on the electrical and thermal transport properties, resulting in a striking peak thermoelectric ZT ≈ 2.4 at 773 K. These findings might provide an alternative conception for thermoelectric optimization via microstructure modulation.

Atomic layer germanium etching for 3D Fin-FET using chlorine neutral beam

In case of using pure chlorine chemistry, Ge etching reactivity is three times higher than Si etching reactivity because of the larger lattice spacing in Ge. As a result, during the chlorine plasma etching of a Ge Fin structure, there are serious problems such as a large side-etching and large surface roughness on the Ge sidewall. Conversely, the authors found that several-ten nanometer-width Ge Fin structures with defect-free, vertical, and smooth sidewalls were successively delineated by chlorine neutral beam etching. Based on these results, the problems caused by chlorine plasma etching are considered to be due to the enhancement of chemical reactivity caused by defect on the sidewall with the irradiation of ultraviolet/vacuum ultra violet (UV/VUV) photons. Namely, it is clarified that the neutral beam etching could achieve real atomic layer etching by controlling the defect without any UV/VUV photons on the sidewall surface for future nanoscale Ge Fin structures.

Role of Post-Deposition Annealing of Sputtered Ti on Fermi Level Depinning in Ti/TiOx/n-Ge

In this work, Ti/interfacial layer (IL) /n-Ge MIS structures with TiOx IL formed by different methods were compared on depinning the Fermi level (FL) between n-Ge and metal. It is found that with the TiOx IL formed by sputtered Ti with a post-deposition annealing (PDA) at 150°C, a low SBH, around 0.08 eV of the Ti/IL/Ge MIS structure is obtained with around 2 nm IL, while SBH of 0.24 eV is obtained for 3 nm TiO2 formed by atomic layer deposition (ALD). The IL formed for the sputtered Ti itself can also reduce the SBH to 0.3 eV while the E-beam evaporated (EBE) Ti cannot depin the FL. TEM and XPS results show that a Ti-O-Ge interlayer formed for the TiOx formed during PDA process and for the sputtered Ti itself, a TiOx layer also formed yet the O content is much less than the former, which might be the reason of less Fermi-level pinning (FLP) effect. This work provides a promising technique in solving the contact barrier problem caused by FLP for nanoscale Ge n-channel devices.

Nanoscale Ge fin etching using F- and Cl-based etchants for Ge-based multi-gate devices

In this paper, nanoscale germanium (Ge) fin etching with inductively coupled plasma equipment with SF6/CHF3/Ar and Cl2/BCl3/Ar gas mixes are experimentally demonstrated. The impact of the gas ratio on etching induced Ge surface flatness, etch rate and sidewall steepness are comprehensively investigated and compared for these two kinds of etchants and the optimized gas ratio is provided. By using silicon oxide as a hard mask, nanoscale Ge fin with a flat surface and sharp sidewall is experimentally illustrated, which indicates great potential for use in nanoscale Ge-based multi-gate MOSFETs.

Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate

In this paper, self-heating effects (SHE) in nanoscale Ge p-channel FinFETs with Si substrate are evaluated by TCAD simulation. Hydrodynamic transport with modified mobilities and Fourier s law of heat conduction with modified thermal conductivities are used in the simulation. Ge p-channel single-fin FinFET devices with different S/D extension lengths and fin heights, and multi-fin FinFETs with different fin numbers and fin pitches are successively investigated. Boundary thermal resistances at source, drain and gate contacts are set to 2000 ${\rm~\mu~m^{2}K/W}$ and the substrate thermal boundary condition is set to 300 K so that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) 14 nm Ge p-channel single-fin FinFETs with a 47 nm fin pitch experience 9.7% on-state current degradation. (ii) Considering the same input power, FinFETs with a longer S/D extension length show a higher lattice temperature and a larger on-state current degradation. (iii) Considering the same input power, FinFETs with a taller fin height show a higher lattice temperature. (iv) The temperature in multi-fin FinFET devices will first increase then saturate with the increasing fin number. At last, thermal resistances in Ge p-channel single-fin FinFETs and multi-fin FinFETs are investigated.

Experimental Investigation of Ballistic Carrier Transport for Sub-100-nm Ge n-MOSFETs

We demonstrate an experimental study on the ballistic transport behavior of sub-100 nm GeOI n-MOSFETs, by adopting an ultrafast pulsed I–V system for measurement. High performance GeOI n-MOSFETs suffer severer self-heating effect and traps in the dc characterization process than in a “real” high-speed IC circuit. In this letter, the ballistic transport parameters for nanoscale Ge n-MOSFETs are extracted by the pulsed I–V method, and is compared with the SOI n-MOSFETs. The ballsiticity for Ge MOSFETs is higher than Si transistors at the same gate length ${L}_{\text {G}}$ . Furthermore, the scalability of the ballistic parameters for Ge n-MOSFETs is modeled and predicted for the sub-10-nm technology nodes.

Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO2/GeO2 Interlayer Stack.

A perfect ohmic contact formation technique for low-resistance source/drain (S/D) contact of germanium (Ge) n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is developed. A metal-interlayer-semiconductor (M-I-S) structure with an ultrathin TiO2/GeO2 interlayer stack is introduced into the contact scheme to alleviate Fermi-level pinning (FLP), and reduce the electron Schottky barrier height (SBH). The TiO2 interlayer can alleviate FLP by preventing formation of metal-induced gap states (MIGS) with its very low tunneling resistance and series resistance and can provide very small electron energy barrier at the metal/TiO2 interface. The GeO2 layer can induce further alleviation of FLP by reducing interface state density (Dit) on Ge which is one of main causes of FLP. Moreover, the proposed TiO2/GeO2 stack can minimize interface dipole formation which induces the SBH increase. The M-I-S structure incorporating the TiO2/GeO2 interlayer stack achieves a perfect ohmic characteristic, which has proved unattainable with a single interlayer. FLP can be perfectly alleviated, and the SBH of the metal/n-Ge can be tremendously reduced. The proposed structure (Ti/TiO2/GeO2/n-Ge) exhibits 0.193 eV of effective electron SBH which achieves 0.36 eV of SBH reduction from that of the Ti/n-Ge structure. The proposed M-I-S structure can be suggested as a promising S/D contact technique for nanoscale Ge n-channel transistors to overcome the large electron SBH problem caused by severe FLP.

Local structure of amorphous and nanoscale systems by numerical XANES calculations

We examined sensitivity of the x-ray absorption near edge structure (XANES) to the local atomic arrangements in amorphous GaSb and nanoscale Ge. We demonstrate that XANES can be reliably used to obtain information about the local symmetry in these systems where lack of periodicity precludes the use of powerful diffraction methods. We used well-studied bulk amorphous GaSb as a reference to verify our approach and then extended it to matrix-free Ge nanoparticles. We show that in small (~4nm) Ge nanoparticles prepared by colloidal synthesis where there is evidence for structural disorder, the local tetrahedral (diamond-type) symmetry is still preserved out to the second coordination shell on average. We find the XANES data collected in transmission and optical detection modes for Ge nanoparticles show distinctive differences with the bulk samples and attribute this to particles size and surface effects. This approach is thus capable of delivering structural information on local symmetry, structure and morphology in nanoscale systems.

Performance Improvement in Nanoscale Ge–GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate

Performance Improvement in Nanoscale Ge–GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate

Studies on Halo Implants in Controlling Short-Channel Effects of Nanoscale Ge Channel pMOSFETs

We report the impact of halo implants on short-channel effects of nanoscale Ge channel pMOSFETs in terms of different electrical device parameters such as threshold voltage ( $V_{\rm TH}$ ), subthreshold slope (SS), and drain-induced barrier lowering. The analysis is based on 2-D surface potential approach taking into account the interface-trapped-charge density, the fixed-oxide-charge density, and halo implants. The higher value of halo concentration as well as halo length shifts the $V_{\rm TH}$ toward the more negative value making pMOS devices suitable for circuit applications and also reduces SS. A design space defined by halo concentration and halo length for $V_{\rm TH}$ almost independent of channel length has been predicted for Ge pMOS devices with gate lengths down to 20 nm. Results obtained from our model show excellent agreement with numerical simulation data obtained using ATLAS and with reported experimental data.

Selective Adsorption ofC60onGe/SiNanostructures

Selective adsorption of C60 on nanoscale Ge areas can be achieved, while neighboring Si(111) areas remain uncovered, if the whole surface is initially terminated by Bi. Fullerene chemisorption is found at Bi vacancies which form due to partial thermal desorption of the Bi surfactant. The growth rate and temperature dependence of the C60 adsorption were measured using scanning tunneling microscopy and are described consistently by a rate equation model. The selectivity of the C60 adsorption can be traced back to an easier vacancy formation in the Bi layer on top of the Ge areas compared to the Si areas. Furthermore, it is also possible to desorb C60 from Ge areas, allowing the use of C60 as a resist on the nanoscale.

Improvement of Thermal Stability of Ni-Germanide with Ni/Co/Ni/TiN Structure for High Performance Ge Metal–Oxide–Semiconductor Field Effect Transistors

In this paper, the thermal stability of Ni-germanide is improved by utilizing Ni/Co/Ni/TiN structure for Ge metal–oxide–semiconductor field effect transistors (MOSFETs) technology. It was shown that the Ni/Co/Ni/TiN structure improved the thermal stability of Ni-germanide mainly due to the suppression of Ni diffusion, and/or the retardation of agglomeration. The incorporated Co atoms distributed, mainly in the top region of the Ni-germanide and it is believed that this Co-rich Ni-germanide layer in the upper region of Ni-germanide enhanced the thermal stability. Therefore, the proposed Ni/Co/Ni/TiN structure is promising for the formation of a highly thermally immune Ni-germanide for nanoscale Ge MOSFETs technology.

Thermal Endurance and Microstructural Evolution of PtGe for High-Performance Nano-Scale Ge-on-Si MOSFETs

The thermal endurance and microstructural evolution of Ni-germanide (NiGe) and Pt-germanide (PtGe) on a Ge-on-Si substrate were compared in this paper. In case of the Ni/TiN structure, the sheet resistance exhibited a stable RTP window of 350 to 600 degrees C, while that of the Pt/TiN structure showed more stable characteristics up to 700 degrees C. Furthermore, after post-germanidation annealing, NiGe exhibited the formation of islands due to the severe agglomeration as well as a prominent grain boundary grooving, which accounts for the sharp increase of the sheet resistance from 550 degrees C, whereas PtGe showed a smooth and continuous surface morphological stability without signs of agglomeration even up to 600 degrees C. Although about two times higher resistivity (31.5 micro ohms-cm) and greater Ge consumption (3.27 nm) were shown, PtGe showed more stable sheet resistance, better surface and interface morphological stability and a wider thermal processing window above 100 degrees C than NiGe. Therefore, PtGe is more suitable for the germanided shallow source/drain for nano-scale Ge MOSFETs than NiGe.

Interfaces and performance: What future for nanoscale Ge and SiGe based CMOS?

SiGe and Ge based CMOS are very attractive for the sub-22 nm nodes. In this paper we discuss the challenges regarding the integration of these materials in the channels of advanced MOSFETs. After a review of the recent achievements in the field of SiGe and Ge based substrates, we focus on the different solutions that enable to obtain SiGe and Ge channel MOSFETs and on the status concerning the best high mobility CMOS (from cSGOI and GeOI MOSFETs to DualChannel CMOS). After this topical outline, we conclude on the possible ways for SiGe and Ge to replace Si for very aggressive nodes.

Electrical study of trapped charges in nanoscale Ge islands by Kelvin probe force microscopy for nonvolatile memory applications

Isolated Germanium nanoisland on top of silicon dioxide (SiO2) layer has been studied by Kelvin probe force microscopy (KPFM) at room temperature. Different surface potentials between Ge island and SiO2 dielectric layer were directly visualized from the KPFM image. The image contrast greatly increased after electron injection by applying a negative bias of −7 V. The dissipation of injected electrons was evaluated by measuring the surface potential variation due to the leakage of these injected charges. The long retention time of local charges in Ge dot is promising for applications in nonvolatile memories.

Improvement of Thermal Stability of Ni Germanide Using a Ni–Pt(1%) Alloy on Ge-on-Si Substrate for Nanoscale Ge MOSFETs

In this paper, thermally stable Ni germanide using a Ni-Pt(1%) alloy and TiN capping layer is proposed for high-performance Ge MOSFETs. The proposed Ni-Pt(1%) alloy structure exhibits low-temperature germanidation with a wide temperature window for rapid thermal processing. Moreover, sheet resistance is stable and the germanide interface shows less agglomeration despite high-temperature postgermanidation anneal up to 550 °C for 30 min. In addition, the surface of the Ni-Pt(1%) alloy structure is smoother than that of a pure Ni structure both before and after the postgermanidation anneal. Only the NiGe phase and no other phases such as PtxGey and NixPt1-xGey can be observed in X-ray diffraction results, but X-ray photoelectron spectroscopy shows that PtGe is formed during the postgermanidation anneal. The larger Pt atomic radius is believed to inhibit the diffusion of Ni into the Si substrate, thereby improving the thermal stability of the NiGe. The higher melting point of PtGe is also believed to improve thermal stability. Therefore, this proposed Ni-Pt(1%) alloy could be promising for high-mobility Ge MOSFET applications.

The Quantitative Study of Trapped Charges in Nano-Scale Ge Islands probed by EFM Measurement

AbstractIn this work, an individual Ge island on top of silicon dioxide layer has been charged by a conductive EFM tip and quantitatively characterized at room temperature. Electrons or holes were successfully injected and were trapped homogenously in the isolated nano-scale Ge island. In order to quantitatively study these trapped charges, a truncated capacitor model was used to approximate the real capacitance between the tip and island surface. The analytical expression of the quantity of trapped charges in isolated Ge island as a function of the EFM phase signal was deduced. Applying a tip bias for -7V during 30 seconds leads to an injection about 800 electrons inside an individual Ge island.