Nanoscale Semiconductor Devices Research Articles

Kinetic study of velocity distributions in nanoscale semiconductor devices under room-temperature operation

Quasiballistic electron transport in nanoscale semiconductor structures is investigated to clarify the importance of scatterings under room-temperature operation as reflected in the velocity distribution functions. The analyses are carried out for n+-n-n+ structures based on the semiclassical Boltzmann transport equation (BTE). It is shown that the number of electrons with negative velocity grows exponetially due to scatterings around the top of the electronic potential barrier in the channel region and, thus, the scatterings cannot be neglected even in nanoscale device structures. This is closely related to the mathematical structure of the BTE whose solution exhibits the boundary-layer structure.

Silicon nanoelectronics: Precise fabrication via a bottom-up approach

This issue of JOM includes four articles on silicon nanoelectronics critically selected and reviewed by the Thin Films & Interfaces Committee of the Electronic, Magnetic, & Photonic Materials Division of TMS. Silicon nanoelectronics is the fi eld of silicon-based electronic devices whose properties are deliberately manipulated at the atomic level in an attempt to produce electronic devices on the nanometer (10m) scale. As the term suggests, silicon nanoelectronics is a subset of much broader nanotechnology with an emphasis on silicon and electronics at the nano (from the Greek word nanos, which means dwarf) level. Thus, size does matter, but this fi eld does not simply stand for miniaturizing electronic devices to the nano regime. Like emerging nanotechnology in general, silicon nanoelectronics is often viewed in light of a paradigm shift for how we deliberate about fabricating an electronic device. For example, instead of a conventional top-down approach used for many years in electronic device fabrication plants, some silicon nanodevices can now be fabricated by adopting a bottom-up approach (i.e., utilizing self-assembly of atoms into silicon nanostructures). This novel approach in electronics is considered a more precise technique of engineering such devices at the nano-level. In addition, silicon nanoelectronics may include revolutionary design, materials, and process research endeavors to achieve ever-increasing device density and performance targets using fi eldeffect transistors (FETs). Many of the requirements for future ultrafi ne devices (projected to be at the ~20 nm level within the next decade) do not have known solutions, indicating there is no guarantee that the historically triumphant FET scaling will continue its success by relying only on evolutionary approaches to device miniaturization. Progress in the fi eld of silicon nanoelectronics is being actively reported by many academic and governmental institutes and private corporations through publications and patents. As one can imagine, it would be a challenging task to review all of them. However, it was not too diffi cult for this committee to select the following four papers, which I hope will serve as valuable references for JOM readers. The fi rst paper, “The Development of Nanocrystalline Silicon for Emerging Microelectronic and Nanoelectronic Applications” by C.C. Striemer, R. Krishnan, and P.M. Fauchet from the University of Rochester presents an overview of nanocrystalline silicon fabrication technologies potentially advantageous for memory-device and single-electron transistor applications. The authors address key engineering challenges related to applying the bottom-up approach to assembling such devices beyond the laboratory environment. The second paper, “The Production and Electrical Characterization of Free-Standing Cubic Single-Crystal Si Nanoparticles” by S.A. Campbell, U. Kortshagen, A. Bapat, Y. Dong, S. Hilchie, and Z. Shen from the University of Minnesota presents a technique to synthesize free-standing cubic singlecrystal silicon nanoparticles in an aerosol which may be transferred onto a wafer to build devices. Campbell et al. also describe a methodology to characterize the silicon nanostructures utilizing a novel sample preparation technique. The third paper, “Interconnect Challenges for Nanoscale Electronic Circuits” by N. Srivastava and K. Banerjee from the University of California at Santa Barbara deals with various performance and reliability challenges related to nanoscale interconnects that serve as key components of an electronic device by connecting building blocks such as transistors. Along with addressing materials and design challenges for the interconnects associated with sub-100 nm FETs, they include brief discussions on emerging interconnect technologies such as three-dimensional interconnects, optical interconnects, and carbon nanotube interconnects. The fourth paper, “The Magnetic Field-Assisted Assembly of Nanoscale Semiconductor Devices: A New Technique” by S. Shet, V.R. Mehta, A.T. Fiory, M.P. Lepselter, and N.M. Ravindra from the New Jersey Institute of Technology and BTL Fellows, Inc. introduces a novel magnetic fi eld-assisted assembly technique that may have potential applications for the placement of nanostructures into receptor sites fabricated on semiconductor wafers. The authors present this technique by discussing its potential advantage as a cost-effective and reliable way of assembling nanodevices. The Thin Films & Interfaces Committee hopes that JOM readers will fi nd these four articles interesting and informative and, more importantly, will recognize that silicon nanoelectronics is an emerging fi eld with technological and economic innovations for the future.

Quantum Corrected Monte Carlo Simulation of Semiconductor Devices Using the Effective Conduction-Band Edge Method

In recent years much effort has been devoted to the quantum mechanically corrected Monte Carlo simulation of nano-scale semiconductor devices. The effective potential and the Wigner or the Bohm quantum potential are usually chosen for making such quantum correction. In this study we propose another approach based on the Bohm potential by transforming the density gradient to an effective conduction-band edge gradient. Similar to the effective potential method, this method has the advantage of not being affected by density fluctuations. We have applied this method to the simulation of a double-gate nMOSFET. Results are compared to those obtained from the semi-classical Monte Carlo simulation without the quantum correction.

Characterization of interfaces in nanoscale semiconductor devices by optimization of depth resolution in SIMS depth profiling

Optimization of depth resolution in secondary ion mass spectrometry (SIMS) depth profiling has been carried out prior to characterization of different nanoscale semiconductor devices based on Si, GaAs and SiGe. The optimization of depth resolution was carried out by adjusting different experimental parameters like primary ion beam energy, ion mass, angle of incidence, sputter rate, etc. Such adjustments control the basic processes like recoil mixing, cascade mixing or penetration depth which in turn control the depth resolution Δ z. Certified reference material Ta 2O 5/Ta was used as standard to optimize the parameters and the actual experiments were performed keeping them in view. Various nanoscale semiconductor devices were characterized for their interfaces, e.g.: 1. InP/InGaAs/InP… quantum well (QW) structures. 2. Si x N y / n-GaAs structures with NH 3 plasma pre-treatment of GaAs for MIS devices. 3. Ga 2O 3(Gd 2O 3)/Si 0.74Ge 0.26/Si structures for MIS devices. 4. Ga 2O 3(Gd 2O 3)/GaAs structures for MOS devices. 5. Au/GaN/Si schottky diodes. 6. Ge/Si bilayer films for swift heavy ion beam induced interface-mixing experiment. It has been observed that Cs + primary ion beam with 10–11 keV energy gives Δ z ∼2–3 nm for most of the depth profiles while O 2 + with 7 keV energy can also give Δ z of similar order (∼2 nm) in some of the systems depending on ion–matrix interaction and secondary ion yield response.

Kinetic simulation tools for nano-scale semiconductor devices

Kinetic simulation tools for design of nano devices based on deterministic solution of the classical Boltzmann equation with quantum corrections are described. We used two-term spherical harmonic expansion in velocity space, reducing the Boltzmann equation for electrons to a Fokker–Planck equation in a four-dimensional space (three spatial coordinates and energy). Details of the numerical implementation of the four-dimensional Fokker–Planck solver using kinetic and total energy domains are presented. The effect of quantum corrections on spatial distribution of carriers is taken into account. Simulation results for the nonlocal nonequilibrium electron transport, short submicron n+nn+ Si diode, quantum single barrier problem, and ultra-small “well tempered NMOSFET” are presented and compared with drift-diffusion, experimental and other author results. The numerical method employed is the finite volume technique with time-splitting factorization of spatial and energy space transport.

Effects of Externally Applied Stress on the Properties of Quantum Dot Nanostructures

An array of semiconductor quantum dots is studied computationally using an approach that couples linear elasticity to electronic and optical properties. The effect of strain on the photoemission behavior of the quantum dot array is of particular interest. With a realistic quantum dot array morphology as input, finite element analysis is first used to compute electron energy levels in the domain. From these energy levels, optical conductivity is computed for the system, which is directly comparable with experimental optical absorption and emission spectra. Then, to simulate the effect of microscope tip-sample interaction, the strain field associated with a rigid cylindrical indenter is superimposed on the sample and the calculation is performed again. The computed optical spectrum shows a distinct blue-shift as a result of the indentation strain field. This observation is qualitatively and quantitatively in agreement with near field scanning optical microscopy (NSOM) experiments on the same material system. The result shows that in nanoscale semiconductor devices, mechanical and electronic properties are coupled over the same length scales and can be treated together in a coupled continuum finite element formulation.

Electric, Field-Dependence of the Scattering Rate in non-Linear Quantum Transport

The role of the finite collision duration in high electric fields is examined for its effect on the scattering rate relevant in many submicron and nanoscale semiconductor devices. Starting from a general non-linear quantum transport equation, an approximate high field quantum kinetic equation is derived, which can be viewed as the first step towards a quantum Boltzmann equation. Based on this equation, the high field scattering rate of electrons is calculated for GaAs in the case of optical phonon scattering at room temperature.

Nanoelectronic device applications of a chemically stable GaAs structure

We report on nanoelectronic device applications of a nonalloyed contact structure which utilizes a surface layer of low-temperature grown GaAs as a chemically stable surface. In contrast to typical ex situ ohmic contacts formed on n-type semiconductors such as GaAs, this approach can provide uniform contact interfaces which are essentially planar injectors, making them suitable as contacts to shallow devices with overall dimensions below 50 nm. Characterization of the native layers and surfaces coated with self-assembled monolayers of organic molecules provides a picture of the chemical and electronic stability of the layer structures. We have recently developed controlled nanostructures which incorporate metallic nanoclusters, a conjugated organic interface layer, and the chemically stable semiconductor surface layers. These studies indicate that stable nanocontacts (4 nm×4 nm) can be realized with specific contact resistances less than 1×10−6 Ω cm2 and maximum current densities (1×106 A/cm2) comparable to those observed in high quality large area contacts. The ability to form stable, low resistance interfaces between metallic nanoclusters and semiconductor device layers using ex situ processing allows chemical self-assembly techniques to be utilized to form interesting nanoscale semiconductor devices. This article will describe the surface and nanocontact characterization results, and will discuss device applications and novel techniques for patterning close-packed arrays of nanocontacts and for imaging the resulting structures.

Cross-sectional scanning tunneling microscopy of mixed-anion semiconductor heterostructures

The engineering of advanced heterostructure and nanoscale semiconductor devices has made essential a detailed understanding of, and control over, the structure and properties of semiconductor materials and devices at the atomic to nanometer scale. Cross-sectional scanning tunneling microscopy provides unique and powerful capabilities for characterization of structural morphology and electronic properties in semiconductor epitaxial and device structures with spatial resolution at or near the atomic scale. The basic technique of cross-sectional scanning tunneling microscopy, and key experimental considerations, are described in this article. Some representative applications of this technique drawn from recent investigations in our laboratory of atomic-scale alloy layer and interface structure in mixed-anion semiconductor heterostructures are presented. By combining the results of scanning tunneling microscopy studies with those of other, complementary characterization techniques, it is possible to develop a detailed understanding of atomic- to nanometer-scale properties of semiconductor materials and devices and to establish correlations between atomic-scale material properties and the behavior of actual devices.

Theory of electron transport through a periodic array of devices with transverse exit leads

We introduce a periodic array of nanoscale semiconductor devices, where each device contains a transverse lead into which conduction electrons can be deflected. These ``deflective'' arrays exhibit a unique resonance structure with respect to electrons traveling the length of the array: coefficients for reflection and transmission through the array can peak simultaneously at resonance, unlike the analogous case in superlattices. We focus in particular on an array of T-shaped devices, similar to those grown recently by epitaxial methods, and characterized by perfection of structure and extremely small size. The T-array's nonlinear $I$-$V$ characteristics, along with its multiple paths for electron flow, may lead to interesting switching applications.

In situ optical spectroscopy of surfaces and interfaces with submonolayer resolution

Major advances in semiconductor surface and interface characterisation are underway, with the introduction of new “epioptic” techniques which offer in situ characterisation and monitoring of semiconductor growth with submonolayer sensitivity. Conventional surface probes can only be applied in high vacuum environments like those of molecular beam epitaxy. Photons can be used in any growth environment, from atmospheric pressure to high vacuum, and offer the prospect of less damage, no charging, and greater penetration. Results are presented from the four main experimental techniques which have been used so far: reflectance anisotropy, spectroscopic ellipsometry, optical second harmonic generation, and Raman scattering. Prospects are excellent for the development of a variety of epioptic probes as monitoring and characterisation facilities for semiconductor growth, particularly in the area of sub-micron and nanoscale semiconductor devices and novel multilayer materials.

Quantum effects, thermal statistics and reliability of nanoscale molecular and semiconductor devices

The reliability of nanoscale molecular and semiconductor devices is analysed in terms of generalized error prediction algorithms. The authors statistical procedures predict the reliability of a device based on the assignment of three independent variables. The first variable, P(1) is the probability of determining the state of the device if only one molecule (or information carrier) is present. The second variable N is the number of molecules (or information carriers) operating to assign the state of the device (that is, the number of quantized entities within the ensemble). The third variable xi lim is the limiting logarithmic reliability factor which is a function of the entire system and the environment in which it must operate. Statistical procedures are also presented which allow one to determine the total system reliability based on the assignment of the desired mean-time-between-failures (DMTBF) and the individual reliabilities of the components. Sample reliability analyses are carried out on three devices to determine the minimum number of molecules N that must be included in the ensemble to achieve an error probability of less than 10-10.