N-type Thin Films Research Articles

Improvement of N-type carbon nanotube field effect transistor performance using the combination of yttrium diffusion layer in HfO2 dielectrics and metal contacts.

In this paper, we obtained n-type top-gate carbon nanotube thin film field effect transistors (CNTFET) with source/drain extensions structure through dielectrics optimization strategy, combining the yttrium layer with HfO2 dielectric argon annealing process and metal contacts. The mechanism for enhanced n-type conduction was explained as being due to the vertical diffusion of yttrium to the HfO2 dielectric during argon annealing. This diffusion causes abending of the energy band, which results in more positive fixed charges and a reduction in the electron injection barrier between the low work function source-drain Cr electrode and carbon nanotube. The optimized technology has great prospects for the low cost, large scale and high performance n-type CNTFET to be used in integrated electronic devices.&#xD.

Ultrahigh Power Factor of Sputtered Nanocrystalline N-Type Bi2Te3 Thin Film via Vacancy Defect Modulation and Ti Additives.

Magnetron-sputtered thermoelectric thin films have the potential for reproducibility and scalability. However, lattice mismatch during sputtering can lead to increased defects in the epitaxial layer, which poses a significant challenge to improving their thermoelectric performance. In this work, nanocrystalline n-type Bi2Te3 thin films with an average grain size of ≈110nm are prepared using high-temperature sputtering and post-annealing. Herein, it is demonstrated that high-temperature treatment exacerbates Te evaporation, creating Te vacancies and electron-like effects. Annealing improves crystallinity, increases grain size, and reduces defects, which significantly increases carrier mobility. Furthermore, the pre-deposited Ti additives are ionized at high temperatures and partially diffused into Bi2Te3, resulting in a Ti doping effect that increases the carrier concentration. Overall, the 1µm thick n-type Bi2Te3 thin film exhibits a room temperature resistivity as low as 3.56 × 10-6 Ω∙m. Notably, a 5µm thick Bi2Te3 thin film achieves a record power factor of 6.66mWmK-2 at room temperature, which is the highest value reported to date for n-type Bi2Te3 thin films using magnetron sputtering. This work demonstrates the potential for large-scale of high-quality Bi2Te3-based thin films and devices for room-temperature TE applications.

High-Performing Flexible Mg3Bi2 Thin-Film Thermoelectrics.

With the advances in bulk Mg3Bi2, there is increasing interest in pursuing whether Mg3Bi2 can be fabricated into flexible thin films for wearable electronics to expand the practical applications. However, the development of fabrication processes for flexible Mg3Bi2 thin films and the effective enhancement of their thermoelectric performance remain underexplored. Here, magnetron sputtering and ex-situ annealing techniques is used to fabricate flexible Mg3Bi2 thermoelectric thin films with a power factor of up to 1.59 µW cm-1 K-2 at 60°C, ranking as the top value among all reported n-type Mg3Bi2 thin films. Extensive characterizations show that ex-situ annealing, and optimized sputtering processes allow precise control over film thickness. These techniques ensure high adhesion of the films to various substrates, resulting in excellent flexibility, with <10% performance degradation after 500 bending cycles with a radius of 5mm. Furthermore, for the first time, flexible thermoelectric devices are fabricated with both p-type and n-type Mg3Bi2 legs, which achieve an output power of 0.17 nW and a power density of 1.67 µW cm-2 at a very low temperature difference of 2.5°C, highlighting the practical application potential of the device.

Investigating the properties of n-type Nb2O5 thin film semiconductor under pulsed laser deposition: number of laser pulses impact

Investigating the properties of n-type Nb2O5 thin film semiconductor under pulsed laser deposition: number of laser pulses impact

High thermoelectric power factor of SbPbTe thin alloy film grown by thermal evaporation and post-annealing treatment

Simple chemical compositions are frequently preferred in practical thermoelectric material applications due to their high growth success rates and increased stability. In this study, an n-type SbPbTe thin alloys film with equal amounts of all elements was grown, and the effect of equal contributions on thermoelectric properties and post-annealing treatment for 1–4 h was investigated. The as-grown SbPbTe thin alloys film and post annealed sample exhibited uniform composition distributions, single-phase microstructures, and non-uniform grain sizes at both micro- and nanoscales. The 4-h post annealed SbPbTe thin alloys film demonstrated maximum thermoelectric power factor of 21.2 μWcm−1K−2 at 500 K. This improvement was attributed to a decrease in electrical conductivity and the maintenance of a relatively maximum Seebeck coefficient achieved through the adjustment of carrier concentrations. The small grain size distribution over the surface contributed to strengthened grain boundary scattering, enhanced the charge carrier density and energy filtering effect. The thermoelectric power factor for the 4-h annealed sample peaks at 500 K, indicating optimal thermoelectric performance, as calculated from the Seebeck coefficient and electrical conductivity values. These findings provide insights into the structural and thermoelectric properties of SbPbTe thin alloy films, pointing to potential ways to improve their thermoelectric efficiency.

Thin film field-effect transistor with ZnO:Li ferroelectric channel

An n-type channel transparent thin film field-effect transistor (FET) using a top-gate configuration on a sapphire substrate is presented. ZnO:Li film was used as a channel, and MgF2 film as a gate insulator. Measurements showed that ZnO:Li films are ferroelectrics with spontaneous polarization [Formula: see text]–5[Formula: see text][Formula: see text]C/cm2 and coercive field [Formula: see text]–10[Formula: see text]kV/cm. The dependences of drain–source current on drain–source voltage at various gate–source voltages in two antiparallel [Formula: see text] states were measured and the values of field-effect mobility and threshold voltage were determined for two [Formula: see text] states are as follows: (a) [Formula: see text][Formula: see text]cm2/Vs, [Formula: see text][Formula: see text]V; (b) [Formula: see text][Formula: see text]cm2/Vs, [Formula: see text][Formula: see text]V. Thus, [Formula: see text] switching leads to a change in FET channel parameters. Results can be used to create a bistable or, more precisely, digital FET.

Role of ultrathin Ti3C2Tx MXene layer for developing solution-processed high-performance low voltage metal oxide transistors

Metal oxide transistors have garnered substantial attention for their potential in low-power electronics, yet challenges remain in achieving both high performance and low operating voltages through solution-based fabrication methods. Optimizing interfacial engineering at the dielectric/semiconductor interface is of utmost importance in the fabrication of high-performance thin film transistors (TFTs). In the present article, a bilayer Ti3C2Tx-MXene/SnO2–semiconductor (Tx stands for surface termination) configuration is used to fabricate a high-performance n-type thin film transistor by using an ion-conducting Li-Al2O3 gate dielectric on a p+-Si substrate, where electrical charges are formed and modulated at the Li-Al2O3/SnO2 interface, and Ti3C2Tx-MXene nanosheets serve as the primary electrical charge channel due to their long lateral size and high mobility. A comparative characterization of two distinct TFTs is conducted, one featuring Ti3C2Tx MXene and SnO2 semiconductor layer and the other with SnO2 only. Notably, the TFT with the Ti3C2Tx MXene layer has shown a significant boost in the carrier mobility (10.6 cm2/V s), leading to remarkable improvements in the on/off ratio (1.3 × 105) and subthreshold swing (194 mV/decade), whereas the SnO2 TFT without the Ti3C2Tx MXene layer shows a mobility of 1.17 cm2/V s with 8.1 × 102 on/off ratio and 387 mV/decade subthreshold swing. This investigation provides a possible way toward the development of high-performance, low-voltage TFT fabrication with the MXene/semiconductor combination.

Gate-Tunable Positive and Negative Photoconductance in Near-Infrared Organic Heterostructures for In-Sensor Computing.

The rapid growth of sensor data in the artificial intelligence often causes significant reductions in processing speed and power efficiency. Addressing this challenge, in-sensor computing is introduced as an advanced sensor architecture that simultaneously senses, memorizes, and processes images at the sensor level. However, this is rarely reported for organic semiconductors that possess inherent flexibility and tunable bandgap. Herein, an organic heterostructure that exhibits a robust photoresponse to near-infrared (NIR) light is introduced, making it ideal for in-sensor computing applications. This heterostructure, consisting of partially overlapping p-type and n-type organic thin films, is compatible with conventional photolithography techniques, allowing for high integration density of up to 520 devices cm-2 with a 5µm channel length. Importantly, by modulating gate voltage, both positive and negative photoresponses to NIR light (1050nm) are attained, which establishes a linear correlation between responsivity and gate voltage and consequently enables real-time matrix multiplication within the sensor. As a result, this organic heterostructure facilitates efficient and precise NIR in-sensor computing, including image processing and nondestructive reading and classification, achieving a recognition accuracy of 97.06%. This work serves as a foundation for the development of reconfigurable and multifunctional NIR neuromorphic vision systems.

Enhanced thermal stability and power factor in layered Bi2Se0.5Te2.5 Thin films across a broad temperature range

Bi2Te3-based n-type thin films with high thermoelectric performances are typically synthesised through the formation of dense structures, a process conventionally conducted at high temperatures. However, this method compromises thermal stability. In this study, structural design and multiple-step annealing were employed to enhance the thermal stability of high-performance Bi2Se0.5Te2.5 thin films. Post-annealing, the disparity in the values of the Seebeck coefficient over the entire test temperature range, was reduced to 20 μV K−1, which is approximately 32 % compared to pre-annealing measurements. The layered Bi2Se0.5Te2.5 thin film demonstrated an elevated power factor (28 × 10−4 W m−1K−2), which was maintained across a broad temperature spectrum. This multiple-step annealing approach not only refines the structural integrity by extending the atomic diffusion duration but also mitigates defects and augments compositional uniformity at reduced temperatures. Consequently, layered Bi2Se0.5Te2.5 films emerge as promising candidates for thermoelectric materials, offering enhanced long-term stability for diverse applications, including electric and hybrid electric vehicles, and portable electronic devices.

Low-field transport properties and scattering mechanisms of degenerate n-GaN by sputtering from a liquid Ga target

In this work, degenerate n-type GaN thin films prepared by co-sputtering from a liquid Ga-target were demonstrated and their low-field scattering mechanisms are described. Extremely high donor concentrations above 3 × 1020 cm−3 at low process temperatures (<800 °C) with specific resistivities below 0.5 mΩcm were achieved. The degenerate nature of the sputtered films was verified via temperature-dependent Hall measurements (300–550 K) revealing negligible change in electron mobility and donor concentration. Scattering at ionized impurities was determined to be the major limiting factor with a minor contribution of polar optical-phonon scattering at high temperatures.

Fabrication and Electrical Characterization of p/n PbSe Diodes

Lead selenide (PbSe) diodes were fabricated using a magnetron sputtering process system with a pulsed DC power supply and a 2-inch PbSe target with a purity of 5N. For p-type PbSe thin films, the process variable was the oxygen ratio in the mixed gas of argon and oxygen. The electrical characteristics of the thin films were observed after heat treatment. For the n-type PbSe, nickel (Ni) was used as a doping material. The deposition and doping were performed simultaneously using a co-sputtering method. During co-sputtering, the input power of the Ni sputter gun was adjusted as a process variable. Hall measurement experiments were performed to measure the doping concentration and resistivity of both the p-type and n-type PbSe semiconducting films. The maximum doping concentration was 2.33×10&lt;sup&gt;19&lt;/sup&gt; cm&lt;sup&gt;-3&lt;/sup&gt; for p-type PbSe and 7.55×10&lt;sup&gt;20&lt;/sup&gt; cm&lt;sup&gt;-3&lt;/sup&gt; for n-type PbSe thin films, respectively. The p-n junction IV curve showed that the lowest forward voltage generation point, V&lt;sub&gt;f&lt;/sub&gt;, was 1.5 V and the reverse breakdown voltage was -4.3 V. In the photocurrent measurement, the photo sensitivities of the heat-treated samples were higher than that of the non-treated sample, and the maximum value was 5.148. Photo responsivity was also higher in the heat-treated samples. Its maximum was 0.7306 mA / W.

Ultraflexible Monolithic Three-Dimensional Static Random Access Memory.

Flexible static random access memory (SRAM) plays an important role in flexible electronics and systems. However, achieving SRAM with a small footprint, high flexibility, and high thermal stability has always been a big challenge. In this work, an ultraflexible six-transistor SRAM with high integration density is realized based on a monolithic three-dimensional (M3D) design. In this design, vertical stacked n-type indium gallium zinc oxide thin film transistors and p-type carbon nanotube transistors share common gate and drain electrodes, respectively, saving interlayer vias used in traditional M3D designs. This compact architecture reduces the footprint of the SRAM cell from a six-transistor to a four-transistor area, saving 33% of the area, and significantly enables the SRAM to have the highest flexibility among the reported ones, withstanding a harsh deforming process (6000 cycles of bending at a radius of 500 μm) without performance degradation. Moreover, this design facilitates the thermal stability of the SRAM under high temperature (333 K). It also exhibits great static and dynamic performance, with the highest normalized hold noise margin of 73.6%, a maximum gain of 151.2, and a minimum static power consumption of 3.15 μW in hold operation among the reported flexible SRAMs. This demonstration provides possibilities for SRAMs to be used in advanced wearable system applications.

N-type and P-type SnOx thin films based MOX gas sensor testing

N-type and P-type SnOx thin films based MOX gas sensor testing

Electrical effect of CdSe layer thickness deposited on p- Si wafer

In this paper, the current-voltage characteristics of n-CdSe/p-Si heterostructures are analyzed using experimental data and electrical junction characteristics. To develop n-CdSe/p-Si heterojunctions, a wide band gap semiconducting layer of n-type CdSe thin film has been grown on a p-type Si (100) substrate at 100oC with different thickness by using the spray pyrolysis technique. The I-V characteristic of n-CdSe\ p-Si heterostructure has been measured in a room in the dark and under illumination (lamp/160 W). Also, the solar cell IV characteristics and efficiency were measured. The characteristic parameters of the structure such as barrier height, ideality factor, and series resistance were determined from the current-voltage measurement.&#x0D;

Controlled synthesis of SnSxSe2-x thin films for solar energy water splitting

Earth-abundant and ecofriendly minerals SnSxSe2–x can be promising candidates for photoelectrochemical (PEC) cells because of their tunable band gaps and high absorption efficiency in the visible light range. In this paper, p type SnS thin films with sheet-like morphologies were successfully prepared by CBD method and then n-type SnSxSe2-x thin films were achieved by selenization annealing of SnS thin films. The physical properties and PEC performances of SnSxSe2-x thin films influenced by the annealing process were detailed studied. The photocurrent densities and stability of SnSxSe2-x films were further improved by the deposition of p-type CdS:Cu buffer layer. And the fabrication of FTO/SnSxSe2-x/CdS:Cu/TiO2/Pt photocathode improved the PEC performance further and the photocurrent as high as 10.5 mA/cm2 had been achieved. IPCE tests indicated that the FTO/SnSxSe2-x/CdS:Cu/TiO2/Pt structure achieved a power conversion efficiency of 31.3 %.

High thermoelectric performance of n-type Mg3Bi2 films deposited by magnetron sputtering

Mg3Bi2 are of great interest for thermoelectric applications near room temperature. In this paper, A metastable cubic phase(c-Mg3Bi2) films were prepared on glass substrate using Mg and Bi elemental targets by magnetron sputtering. Investigations were done on the phase composition, microstructure and thermoelectric properties of films that were deposited with various atomic ratios of Bi to Mg. When the atomic ratio of Mg/Bi exceeded the stoichiometry of 3:2, the films displayed a metastable cubic phase (c-Mg3Bi2) with a highly (111) preferred orientation. The deposited (c-Mg3Bi2) films possess n-type conductivity characteristics with high carrier mobility. In the temperature range of 300–490 K, a state-of-the-art average PF of 3.11 μW cm−1K−2 is attained in a 23 at.% Bi film. A fully Mg3Bi2 thermoelectric device consisting of both n-type and p-type Mg3Bi2 thin films is fabricated. It demonstrates a maximum output power density of 239 μW cm−2 at a temperature difference of 20 K. This work offers an effective approach to development of thermoelectric devices based on Mg3Bi2 materials.

High-Performance Thermoelectric Flexible Ag2Se-Based Films with Wave-Shaped Buckling via a Thermal Diffusion Method.

Herein, an n-type Ag2Se thermoelectric flexible thin film has been fabricated on a polyimide (PI) substrate via a novel thermal diffusion method, and the thermoelectric performance is well-optimized by adjusting the pressure and temperature of thermal diffusion. All of the Ag2Se films are beneficial to grow (013) preferred orientations, which is conducive to performing a high Seebeck coefficient. By increasing the thermal diffusion temperature, the electrical conductivity can be rationally regulated while maintaining the independence of the Seebeck coefficient, which is mainly attributed to the increased electric mobility. As a result, the fabricated Ag2Se thin film achieves a high power factor of 18.25 μW cm-1 K-2 at room temperature and a maximum value of 21.7 μW cm-1 K-2 at 393 K. Additionally, the thermal diffusion method has resulted in a wave-shaped buckling, which is further verified as a promising structure to realize a larger temperature difference by the simulation results of finite element analysis (FEA). Additionally, this unique surface morphology of the Ag2Se thin film also exhibits outstanding mechanical properties, for which the elasticity modulus is only 0.42 GPa. Finally, a flexible round-shaped module assembled with Sb2Te3 has demonstrated an output power of 166 nW at a temperature difference of 50 K. This work not only introduces a new method of preparing Ag2Se thin films but also offers a convincing strategy of optimizing the microstructure to enhance low-grade heat utilization efficiency.

Enhanced the thermoelectric power factor of n-type Bi2Te3 thin film via energy filtering effect

In recent years, Bi2Te3 thin films have gained interest in the field of thermoelectric power generation due to their promising thermoelectric performance. However, the poor performance of Bi2Te3 has limited its widespread applicability. To address this, we deposited Bi2Te3 films on soda lime glass substrates via thermal evaporation and annealed them at different temperature ranges between 100 and 350 °C. Our X-ray diffraction analysis showed that the best quality film was produced at a post-annealing temperature of 350 °C, while the as-deposited sample yielded a low-quality film. We then analyzed the surface morphology of the prepared sample using scanning electron microscopy and found that the grains were highly intact with a uniformly aligned granular surface morphology and no porosity. By controlling the density and grain size, we were able to improve the Seebeck coefficient and electrical conductivity. Specifically, the Seebeck coefficient value increased up to 135 μV/°C due to the energy filtering effect at small grain boundaries, while the electrical conductivity improved by raising the charge carrier mobility and reducing grain size, thus increasing the conductivity of the tiny domain. Consequently, the Bi2Te3 thin film with a small grain size exhibited the highest thermoelectric power factor of 15.30 μW cm−1 C−2 at room temperature. Our findings suggest that the thermal evaporation technique is an effective method for growing Bi2Te3 thin films with improved thermoelectric properties.

Performance improvement of an all electrochemically constructed p-type Cu2O-based heterojunctions using high-quality n-type MZO thin films

Performance improvement of an all electrochemically constructed p-type Cu2O-based heterojunctions using high-quality n-type MZO thin films

Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and Retention-Centric Tiki-Taka Algorithm.

Analog in-memory computing synaptic devices are widely studied for efficient implementation of deep learning. However, synaptic devices based on resistive memory have difficulties implementing on-chip training due to the lack of means to control the amount of resistance change and large device variations. To overcome these shortcomings, silicon complementary metal-oxide semiconductor (Si-CMOS) and capacitor-based charge storage synapses are proposed, but it is difficult to obtain sufficient retention time due to Si-CMOS leakage currents, resulting in a deterioration of training accuracy. Here, a novel 6T1C synaptic device using only n-type indium gaIlium zinc oxide thin film transistor (IGZO TFT) with low leakage current and a capacitor is proposed, allowing not only linear and symmetric weight update but also sufficient retention time and parallel on-chip training operations. In addition, an efficient and realistic training algorithm to compensate for any remaining device non-idealities such as drifting references and long-term retention loss is proposed, demonstrating the importance of device-algorithm co-optimization.