Multiplying Digital-to-analog Converter Research Articles

A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μm CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply.

A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS

This paper proposed a pipelined analog-to-digital converter (ADC) that utilizes a high-linearity input buffer and a two-step input-split fully differential ring amplifier (ringamp). The implemented input buffer based on a gain-boost cascode current source, is optimized for linearity over a wider frequency range by suppressing fluctuations in tail current. To save power consumption without compromising common-mode and power-supply rejection, a fully differential ring amplifier is employed as the residue amplifier. Additionally, a correlation-based calibration is implemented, which involves injecting pseudo-random dither signals into each multiplying digital-to-analog converter (MDAC) stage to enhance linearity. Fabricated in a 28-nm CMOS process, the 1.25-GS/s 10-bit ADC achieves a spurious-free dynamic range (SFDR) of 70.7 dB and a signal-to-noise-and-distortion ratio (SNDR) of 50.3 dB at Nyquist input. The core conversion circuits of the ADC consume only 30.2 mW from a single 1-V supply. This translates to a Walden figure of merit (FoM) of 90 fJ/conversion-step and a Schreier FoM of 153.5 dB, respectively.

A 16-Bit 120 MS/s Pipelined ADC Using a Multi-Level Dither Technique

In wireless applications, such as radars, tens of MHz signals need to be quantized using an analog-to-digital converter (ADC) with a large dynamic range. The detected signal amplitude can be random, with a small or large amplitude. In addition, the dynamic performance is degraded by capacitor mismatches. A 16-bit 120 MS/s pipelined ADC implemented in a 180 nm complementary metal–oxide–semiconductor (CMOS) process is presented in this work. We propose a multi-level dither technique that can significantly enhance the ADC linearity. The injected dither also helps improve the linearity when the ADC handles an input signal with a small amplitude. Traditional dither injection leads to an increase in the amplifier output swing. A counteracting dither injection scheme, both in sub-flash ADC and the multiplying digital-to-analog converter (MDAC), is proposed to remedy this issue. Moreover, capacitor mismatches in the first three pipeline stages are calibrated in a foreground way. The inter-stage residue gain accuracy is guaranteed by a gain-boosting amplifier. To demonstrate the effectiveness of the dither scheme, we obtained the dynamic performance of the ADC with a small input signal (−12 dBFS). The proposed calibration and dither injection technique improved the spurious-free dynamic range (SFDR) from 77 dBc to 85 dBc with −12 dBFS input. With −1 dBFS input, the SFDR remained at over 85 dBc, reaching up to the Nyquist input frequency. Therefore, the dither scheme enhances the dynamic performance when the ADC handles a signal with small amplitude.

A parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC

This letter proposes a parasitic elimination bootstrapped switch and a fast settling residual amplifier to be used in multiplying digital-to-analog converter (MDAC) in order to improve the performance of pipelined ADC at high frequency. The parasitic elimination bootstrapped switch improves the sampling spurious free dynamic range (SFDR) by more than 6dB by shielding the nonlinear parasitic capacitance of the MOS transistor substrate. In addition, at high frequency, the negative zero point introduced by the later stage switch-capacitor circuit (which is easy to be ignored) will seriously deteriorates the settling time of residual amplifier in the former stage. A new zero-pole elimination technique is proposed, which greatly reduces the settling time of residual amplifier by nearly 11% and further improve the performance of MDAC. Simulated in 28nm CMOS technology, as the input signal is 1.38GHz, the former stage of the pipelined ADC implements high-speed high-resolution to obtain a SFDR of 75.77dB and a signal-to-noise-plus-distortion ratio (SNDR) of 68.05dB at a sampling frequency of 2.2GS/s.

A Self-Calibration Method of a Pipeline ADC Based on Dynamic Capacitance Allotment

This manuscript introduces a low-power mixed-signal foreground calibration algorithm of a pipeline analog-to-digital converter (ADC) using a digitally controlled reconfigurable switched-capacitor multiplying digital-to-analog converter (MDAC) gain controller. The proposed calibration technique forces the front-end stage MDAC gain toward its ideal value to achieve the ideal ADC output linearity. In this brief, a feedback mechanism has been employed to nullify the effect of change in MDAC gain from its ideal value by sensing a digital back-end unit response. The proposed method has been simulated using a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. An 11-bit pipeline ADC with a 1.5-bit stage followed by a ten bit linear back-end ADC (BE-ADC) has been used to calibrate the non-linearity of the said 1.5-bit stage. Using a low amplifier gain value of 28 dB, the signal-to-noise-and-distortion ratio (SNDR) of the ADC improves from 46.21-dB pre-calibration to 65.13-dB post-calibration.

A 16b 120MS/s Pipelined ADC Using an Auxiliary-Capacitor-Based Calibration Technique Achieving 90.5dB SFDR in 0.18 μm CMOS

A 16-bit 120 MS/s sample-hold-amplifier-less(SHA-less) pipelined analog-to-digital converter (ADC) with an on-chip calibration technique in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process is presented. A switched capacitor circuit with an auxiliary unit capacitor in the multiplying-digital-to-analog converter (MDAC) of the first stage is proposed. The auxiliary-capacitor based calibration technique eliminates the need for a dedicated reference buffer to generate the calibration voltages at all the comparator thresholds. By switching the auxiliary capacitor and doing some simple calculation work, all the capacitor mismatches in the first and second stages are corrected in the digital domain, thereby significantly improving the ADC performance. Measurement results show that, with 70.1 MHz input, the signal-to-noise-and-distortion-ratio (SNDR) is improved from 75.5 dB to 77.8 dB, and the spurious-free-dynamic-range (SFDR) is improved from 81.9 dBc to 90.5 dBc with the proposed calibration technique.

A digital background calibration technique for interstage gain nonlinearity in pipelined ADCs

This paper presents a digital background technique that intentionally exploits multiple dithers to calibrate conversion errors caused by interstage gain error and nonlinearity in high speed pipelined analog-to-digital converters (ADCs). Two independent, zero-mean pseudo-random signals are injected into the multiplying digital-to-analog converter (MDAC) alternately to estimate these errors. Least mean square (LMS) algorithms are adopted to quickly locate and track the calibration parameters. Simulation results are presented for a 800 MSps 12-bit pipelined ADC in a 40nm CMOS technology, similar to that described by Murmann and Boser [1], Keane et al. [2] and Nan Sun [3] using low-gain amplifiers. With calibration, the signal-to-noise-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 32.74dB and 43.61dB to 70.54dB and 89.8dB, respectively. The proposed calibration technique has the advantages of simple implementation, arbitrary amplitude pseudo-random signals, and no restriction on the input signal of the ADC.

A low-power column-parallel cyclic ADC for CMOS image sensor with capacitance and current scaling

This paper presents a power-optimized column-parallel cyclic ADC for CMOS image sensor readout circuits. By separating the capacitor and bias current source and floating them in the circuit, the multiplying digital-to-analog converter (MDAC)'s capacitive load and bias current can be significantly decreased during least significant bit (LSB) quantization, which allows the ADC to reduce power consumption while maintaining a constant conversion rate. The residual quantization characteristic of MDAC makes the input-referred noise produced in LSB quantization relatively small, so the additional noise generated by capacitance scaling can be compensated by increasing the capacitance load of the most significant bit (MSB). A 14-bit two-stage column-parallel cyclic ADC is designed using 0.13-μm technology. The simulation results show that the effective-number-of-bit (ENOB) is 13.54 bit under 0.96-μs sampling rate, and the power consumption of each column is 631 μW. Compared with the traditional structure, the power consumption of ADC is reduced by 35.1%, while the performance remains unchanged.

New Computer Controlled High Resolution Programmable Validation System for Research in Electronics Hardware

Conventional methods for validation of electronics hardware research are susceptible to manual measurement errors, and give limited accuracy of 8 to 10 bits. These methods are also time consuming and do not ensure accuracy in validation of performance parameters. Hence, a new computer controlled high resolution programmable hardware research validation system has been proposed here for testing the electronics hardware systems. The test signals with high resolution (16 bit) and high accuracy are generated using multiplying digital to analog converter (MDAC) with high reference bandwidth. The output signals are measured with the same resolution and accuracy using 16 bit analog to digital converter (ADC). The output data is transferred to the PC through USB interface for further analysis using Teensy 3.6 card. The signals can be generated in bandwidth of 0-10MHz in step size which can be as small as 10μV and as large as 600mv which is user programmable. This proposed system has been designed, constructed and tested. The experimental results of this system have been reported here which ascertain the performance of the system. With this system, manual errors in measurement are avoided and testing time is significantly reduced. The reported system is low cost economic solution for validating the electronic research work in academic institutes.

A 12-bit 10 MS/s 12 mW pipelined SAR ADC for CubeSat systems using [formula omitted]-based switching MDAC and unit capacitor array

This paper presents a 12-bit 10 MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) for a CubeSat system. A full differential architecture is adopted, and a single-ended-to-differential circuit is integrated in the ADC. The proposed ADC is divided into a first-stage 6-bit SAR-based multiplying digital–analog converter (MDAC) and a second-stage 8-bit SAR ADC. A new MDAC using a Vcm-based switching method is employed to reduce power dissipation and improve the linearity of the ADC. Moreover, a unit capacitor array is used to improve the conversion speed and linearity of the first-stage MDAC. In addition, several radiation-hardened-by-design techniques are adopted in the layout design to protect against space radiation effects. A prototype chip was fabricated in a 0.18μm mixed-signal 1.8 V/3.3 V process and operated with a 1.8 V supply. The chip occupies a core area of 1.35mm2. The proposed pipelined SAR ADC consumes 12 mW and achieves a peak signal-to-noise-and-distortion ratio of 65.8 dB and a peak spurious-free dynamic range of 78.5 dB at a sampling rate of 10 MS/s. The figure of merit of the proposed ADC is 0.75 pJ/conversion-step.

Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits

To realize high-resolution pipelined and pipelined-SAR analog-to-digital-converters (ADCs), an accurate residue amplifier is necessary. However, realizing such an amplifier in scaled CMOS is challenging due to the worsened transistor characteristics. Prior works focused on gain calibration techniques to mitigate the use of low-gain amplifiers, in return of system complexity and prolonged startups. In this paper, we introduce a digital amplifier (DA) technique to realize power-efficient and accurate amplification in scaled CMOS. DA cancels out all errors (i.e., gain error, nonlinearity, incomplete settling, power supply noise, and thermal noise) of the low-gain amplifier by feedback based on successive approximation. The DA accuracy can be arbitrary set by configuring the number of bits in the DA capacitor digital-to-analog-converter; the amplifier gain is decoupled from the transistor intrinsic gain which is suitable for scaled CMOS integration. We also show that the power efficiency can be enhanced over conventional opamp-based designs with relaxed settling error requirements of DA-based multiplying digital-to-analog-converters (MDACs). Moreover, the circuit design of DA-based MDACs is further discussed. Measurement results of the calibration-free 0.7-V 12-bit 160-MS/s pipelined-SAR ADC implemented in 28-nm CMOS are reported. Without calibration, the ADC achieves signal-to-noise-and-distortion-ratio = 61.1 dB, figure-of-merit = 12.8 fJ/conv., which is over $3\times $ improvement compared with conventional calibration-free high-speed pipelined ADCs. In addition, we evaluate the DA’s process scalability by comparing the measured results of the DA-based MDAC prototyped in 65- and 28-nm CMOS. We observe $2\times - 3\times $ improvement in speed, power, and area mainly resulting from the DA’s process scalability.

A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC

This article presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipeline architecture which breaks the speed bottleneck of the existing SAR or SAR-assisted-type NS analog-to-digital converters (ADCs). Rather than only for residue amplification and pipeline operation, the multiplying digital-to-analog converter (MDAC) is also reused as unity buffer and analog adder to realize the NS with error feedback (EF) structure in this design. While incorporating the proposed alternative loading capacitor (ALC) technique, an ideal first-order noise transfer function (NTF) is realized without additional feedback phase and only with a small analog circuit overhead. Unlike other NS SAR ADCs that involved amplification, the inter-stage gain attenuates the noise from the second-stage comparator, thus leading to both high speed and resolution. Fabricated in a 65-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 77.1 dB over 12.5-MHz bandwidth (BW) with only over-sampling ratio (OSR) of 8. Under a 1.2-V supply voltage, the ADC consumes 4.5 mW and exhibits a Scherier figure of merit (FoM) of 171.5 dB.

Errors of Multiplying D/A Converters Used for Precise AC Voltage Division

High-resolution multiplying digital-to-analog converters (MDACs) are often used as digitally controlled ac voltage dividers in precise instruments and measurement systems. Proper application of these converters requires knowledge of their parameters, especially amplitude and phase errors, which are usually not specified by MDAC manufacturers. This paper presents the results of investigations of voltage amplitude ratio errors and phase errors, as well as the time stability of voltage ratio and phase shift of selected commercial 16- and 18-bit MDACs. These parameters were measured with a dedicated high-resolution sampling system. The amplitude ratio and phase errors were determined as a function of the MDAC digital input word. Phase errors were also determined as a function of frequency.

A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs

A power-efficient pipeline analog-to-digital converter (ADC) architecture employing a current-mode (CM) multiplying digital-to-analog converter (MDAC) is implemented in this paper. A linear operational transconductance amplifier (OTA), a current steering DAC, and a transimpedance amplifier (TIA) work together as an error amplifier to implement the first stage of the pipeline ADC. The high output impedance displayed by both OTA and MDAC allow us to maximize the power efficiency of the residue amplifier. Compared with a conventional switched-capacitor (SC) MDAC architecture, the proposed CM MDAC reduces the architecture’s power consumption. The fabricated pipeline ADC achieves a 61.3-dB/60.2-dB signal-to-noise and distortion ratio (SNDR) and a 76-dB/74-dB spurious-free dynamic range (SFDR) for a sinusoidal input of 4.15 and 97.9 MHz, respectively. The ADC’s power consumption when operating at 200 MS/s is 8.4 mW, and the conversion figure of merit (FoM) is a 44 fJ/conversion step. The prototype occupies an active area of 0.23 mm2 in a mainstream low-power 40-nm CMOS technology.

Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager

This paper presents a 12-bit pipelined successive approximation register (SAR) ADC for CZT-based hard X-ray Imager. The proposed ADC is comprised of a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. A novel MDAC architecture using Vcm-based Switching method is employed to maximize the energy efficiency and improve the linearity of the ADC. Moreover, the unit-capacitor array instead of the binary-weighted capacitor array is adopted to improve the conversion speed and linearity of the ADC in the first-stage MDAC. In addition, a new layout design method for the binary-weighted capacitor array is proposed to reduce the capacitor mismatches and make the routing become easier and less-time-consuming. Finally, several radiation-hardened-by-design technologies are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and operated at 1.8 V supply. The chip occupies a core area of only 0.58 mm2. The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 66.7 dB and a peak spurious-free dynamic range (SFDR) of 78.6 dB at 10 MS/s sampling rate and consumes 10 mW. The figure of merit (FOM) of the proposed ADC is 0.56 pJ/conversion-step.

PN-assisted digital background calibration of two-step ADC to over 14-bit accuracy

A new non-binary multiplying digital-to-analog converter (MDAC) structure with signal-dependent dithering scaling technique is proposed in this paper. A full digital background calibration algorithm based on pseudo-random dithers injection is used to calibrate the nonlinear errors of MDAC. By measuring sampling capacitor mismatch and op-amp gain errors of the pipelined analog-to-digital converter (ADC) in background, the errors will be greatly reduced by the proposed calibration algorithm. At the same time, the signal-dependent dithering scaling technique provides a swing margin to the injected pseudo-random signal. By using this technique, the errors caused by the capacitor mismatch and op-amp gain errors can be calibrated at the same time. What’s more, this method greatly accelerates the convergence speed. A two-stage 14-bit pipelined ADC is used to simulate and verify the proposed algorithm. The simulation results indicate the effectiveness of the technique, in which the signal-to-noise plus distortion (SNDR) and the spurious-free dynamic range (SFDR) performance of a 14-bit two-step ADC are improved from 49.12 and 56.25 to 85.68 and 102.23 dB with the input frequency being 0.06 * f s , respectively. The SFDR is more than 98 dB. The SNDR reaches 84 dB in the whole Nyquist bandwidth after calibration. Integral nonlinearity is improved from 80 to 1.5 least significant bits after calibration.

Telescopic Op-Amp Optimization for MDAC Circuit Design

An 8-bit 40-MS/s low power Multiplying Digital-to-Analog Converter (MDAC) for a pipelined-to-Analog to Digital converter (ADC) is presented. The conventional dedicated operational amplifier (Op-Amp) is performed by using telescopic architecture that features low power and less-area. Further reduction of power and area is achieved by using multifunction 1.5bit/stage MDAC arch itecture. The design of the Op-Amp is performed by the elaboration of a program based on multi objective genetic algorithms to allow automated optimization. The proposed program is used to find the optimal transistors sizes (length and width) in order to obtain the best Op-Amp performances for the MDAC. In th is study, six performances are considered, direct current gain, unity-gain bandwidth, phase margin, power consumption, area, slew rate, thermal noise, and signal to noise ratio. The Matlab optimization toolbox is used to implement the program. Simulations were performed by using Cadence Virtuoso Spectre circuit simulator in standard AMS 0.18μm CMOS technology. A good agreement is observed between the results obtained by the program optimization and simulation, after that the Op-Amp is introduced in the MDAC circuit to extract its performances.

A 12-bit 200MS/s pipeline ADC with 91 mW power and 66 dB SNDR

A 12-bit 200MS/s pipeline analog-to-digital converter (ADC) with sample-and-hold amplifier (SHA) is proposed in this paper. An innovative timing control technology is applied to the SHA in order to eliminate its nonlinear kickback, while the SHA eliminates bandwidth and timing mismatches between the input networks of the flash (sub-ADC) and of the multiplying DAC (MDAC) in the first stage, to improve the analog input bandwidth and to meet the requirements of a high-IF sampling ADC. A novel full complementary op-amp is utilized to reduce the overall power consumption of the ADC, which makes the power consumption of the SHA and of the first stage less than 20mW. A new fully differential reference buffer and a clock receiver with duty-cycle stabilizer (DCS) are applied in the prototype ADC. The jitter of the clock receiver is less than 150 fs to avoid the SNR degradation. The ADC is implemented in 0.18µm CMOS process and consumes 91mW from a 1.8V supply. The ADC achieves an SNDR of 66.10dB and an SFDR of 84.45dB with 10MHz input signal, while maintaining an SNDR >65dB and SFDR >80dB up in the entire Nyquist band. Its input signal frequency is up to 500MHz.

Design of a 10-bit 1 MS/s pipelined SAR ADC for CZT-based imaging system

A 10-bit 1 MS/s pipelined SAR ADC for CZT-based imaging system is presented. The ADC is composed of three pipeline stages which are two 4-bit SAR-based Multiplying Digital Analog Converters (MDACs) and a 4-bit SAR ADC. In order to improve the performances of the proposed ADC, several techniques were proposed. Firstly, a novel 4-bit MDAC circuit which can eliminate the offset voltage of residue amplifier is proposed here. Secondly, digital correction technique is adopted for eliminating the error induced by offset voltage of comparator. As long as the offset voltage is less than 1/16 Vref, the offset voltage can be corrected. Thirdly, digital calibration technique is used to calibrate the gain errors due to capacitor mismatch, finite open-loop gain and finite gain band width (GBW) of residue amplifier and so on. The prototype chip was fabricated in a 0.35µm CMOS process and occupies a core area of 960×1260µm2. The proposed pipleined SAR ADC achieves 55.6dB SNDR at 1MS/s sampling rate and consumes 8.2mW power. The FOM of the proposed ADC is 17.2pJ/conversion-step.

Design of a 12-bit 2 MS/s 12 mW pipelined SAR ADC in CMOS 0.18 μm technology for CZT-based imaging system

This paper presents a 12-bit 2 MS/s pipelined successive approximation register (SAR) ADC for CZT-based imaging system. The proposed ADC is divided into a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. The first-stage MDAC has a gain of 16 instead of the usual gain of 64, which considerably minimizes the power dissipation of residue amplifier. The second-stage 8-bit SAR ADC employs unit bridge capacitor split-capacitor architecture aiming to reduce the load capacitance of residue amplifier so as to minimize the power dissipation of the proposed ADC. Moreover, a code-randomized calibration algorithm is proposed to improve the linearity of the second-stage 8-bit split-capacitor SAR ADC. In addition, several radiation-hardened-by-design techniques are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μ m mixed-signal 1.8 V/3.3 V process and occupied a core area of 0.71 mm2. The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 63.2 dB at 2 MS/s sampling rate and consumes 12 mW power in total. The figure of merit (FoM) of the proposed ADC is 5.06 pJ/conversion-step.