Multiple Terms Research Articles

Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications

Approximate computing is an innovative design methodology to reduce the design complexity with an improvement in power efficiency, performance and area by compromising on the requirement of accuracy. In this paper, 8-bit approximate Booth multipliers have been proposed based on the approximate Radix-4 modified Booth encoding algorithm and approximate compressors for partial product accumulation to produce the final products are proposed. Two approximate Probability Based Booth Encoders (PBBE-1 and PBBE-2) have been proposed and used in the Booth multipliers. Error parameters have been measured and compared with the existing approximate booth multipliers. Exact booth multiplier of novel design existing in the literature has also been implemented for comparison purpose. The proposed approximate multipliers are then used in applications like image multiplication and IIR bi-quad filtering to prove their performance. Simulation results prove that the proposed booth multipliers outperform the existing approximate booth multipliers in terms of power and area with better accuracy. Synthesis results prove that the proposed Multiplier 6 was found to be the most efficient with a 56 % power consumption improvement and a 47 % area improvement when compared to the exact multiplier. All the simulations are carried out using Cadence® Genus with 180 nm CMOS process technology.

An optimized FPGA architecture for machine learning applications

FPGAs are currently the most suitable hardware accelerators to implement and accommodate the non-stop growth of machine learning applications. This paper presents an FPGA architecture with added posit multipliers that outweigh the current IEEE-754 multipliers in terms of delay and area. Since machine learning algorithms involve a lot of expensive mathematical operations, having such powerful multipliers in the proposed FPGA architecture will execute the needed operations with high efficiency, which will stand out for machine learning applications without compromising other FPGA applications. Experimental results using Verilog to Routing (VTR) on both machine learning and non-machine learning benchmarks have demonstrated that our proposed architecture consumes 10% less area than the Stratix IV FPGA. Furthermore, it consumes less power compared to both the Stratix IV and Stratix 10 FPGAs, with reductions of 22% and 10%, respectively. Additionally, our architecture outperforms the Stratix IV and Stratix 10 FPGAs in terms of critical path delay, with improvements of 25.5% and 43%, respectively.

Design and Implementation of Area Efficient Low Latency Radix-8 Multiplier on FPGA

Abstract: Electronic systems are widely used by humans nowadays in all aspects of daily life. Today, there is no living for humans on Earth without any electronic products. High Speed, Low Power, and Low Area Electronic Systems are what the current generation needs. In digital systems, a variety of arithmetic circuits are employed. Adder, multiplier, divider, and other arithmetic circuits are some examples. To acquire Products from Multiplier and Multiplicand, there are various multipliers with various methods. One of the multipliers is Radix-4 Multiplier. The Radix-4 Multiplier produces n/2 partial products, where n is the multiplier's bit count. This multiplier has a high operating speed, power dissipation, and surface area. Area, power dissipation, and propagation delay can all be reduced by reducing the number of partial products of the n-bit multiplier. Radix-8 uses n-bit multiplier integers that are n/3 for partial products. The Area, Delay, and Power Dissipation are reduced as a result. 8- bit booth multipliers for Radix-4 and Radix-8 are designed and implemented using FPGA. For both multipliers, delay, power dissipation, and area are compared. According to the comparison, Radix8 Booth Multiplier performs better than Radix-4 Booth Multiplier in terms of delay, power dissipation, and area. Therefore, the Radix-4 Booth Multiplier can be swapped out for the Radix-8 Booth Multiplier.

Why Economic Growth Stimulates More Growth in Some Countries Rather than Others

Leontief multipliers are an important component of economic growth. However, input–output analysis is generally treated as a methodological tool for studying other questions in development. The size of multipliers themselves is of interest, as they determine how much nations benefit economically from the growth of base industries. Of the three types of multipliers—industrial supply purchases by firms, consumer goods purchases by workers, and growth derived from all sources—only the first has attracted attention in the global value chain literature; the other two have been neglected. We use OECD data on a large sample of nations in 2005, 2010, and 2015 to show that significant cross-national and inter-industrial differences exist in the size of multipliers. Contrary to expectations, higher-income countries can sometimes have lower multipliers than lower-income countries. The largest multipliers tend to be in the global South. We then provide a model explaining the differences in multipliers in terms of the domesticity of purchases, the wage intensity of production, the geographical size of the country, and the changing roles of GDP per capita and education as societies develop. The significance of these findings for development policy is discussed.

Multipliers and covers of perfect diassociative algebras

The paper concerns perfect diassociative algebras and their implications to the theory of central extensions. It is first established that perfect diassociative algebras have strong ties with universal central extensions. Then, using a known characterization of the multiplier in terms of a free presentation, we obtain a special cover for perfect diassociative algebras, as well as some of its properties. The subsequent results connect and build on the previous topics. For the final theorem, we invoke an extended Hochschild–Serre-type spectral sequence to show that, for a perfect diassociative algebra, its cover is perfect and has trivial multiplier. As an important consequence, we obtain the entire theory for associative algebras as a special case of diassociative algebras. We conclude with a concrete example.

Linear Peridynamics Fourier Multipliers and Eigenvalues

A characterization for the Fourier multipliers and eigenvalues of linear peridynamic operators is provided. The analysis is presented for state-based peridynamic operators for isotropic homogeneous media in any spatial dimension. We provide explicit formulas for the eigenvalues in terms of the space dimension, the nonlocal parameters, and the material properties. The approach we follow is based on the Fourier multiplier analysis developed by Alali and Albin (Applicable Analysis 2526–2546, 1). The Fourier multipliers of linear peridynamic operators are second-order tensor fields, which are given through integral representations. It is shown that the eigenvalues of the peridynamic operators can be derived directly from the eigenvalues of the Fourier multiplier tensors. We reveal a simple structure for the Fourier multipliers in terms of hypergeometric functions, which allows for providing integral representations as well as hypergeometric representations of the eigenvalues. These representations are utilized to show the convergence of the eigenvalues of linear peridynamics to the eigenvalues of the Navier operator of linear elasticity in the limit of vanishing nonlocality. Moreover, the hypergeometric representation of the eigenvalues is utilized to compute the spectrum of linear peridynamic operators.

VLSI Design of Approximate Baugh-Wooley Multiplier for Image Edge Computing

A sort of digital circuit used to multiply two binary values is called a Baugh-Wooley multiplier. It is renowned for being more effective than other kinds of multipliers in terms of speed and gate count. You would normally start by creating a simple version of the circuit utilizing logic gates like AND gates, XOR gates, and half adders to simulate the Baugh-Wooley multiplier. The design would then be optimized utilizing methods like parallel processing, pipelining, and optimization algorithms to lower the overall gate count and boost the functionality of the circuit. Because of this, estimating a Baugh-Wooley multiplier would require a thorough knowledge of these elements as well as the specifications of the application. Verilog HDL is used to implement this design, and Modelsim 6.4 c is used to simulate it. The synthesis process tool from Xilinx measures performance.

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

AbstractReversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.

Efficient approximate multipliers with adjustable accuracy

ABSTRACT The number of smart devices grows rapidly, and the main leakage of many of these devices is their limited batteries, in addition to the need for a fast and low-power computing system. Approximate calculations are an excellent method for such systems to achieve higher speed and less area and power consumption at the cost of lower accuracy. Furthermore, in many applications with inherent tolerance for insignificant inaccuracies such as image processing, approximate computing can be used to achieve acceptable performance with higher speed, lower power or area consumption. In this work, approximate multiplier structures are proposed based on working on the partial product trees with the aim of reducing area consumption and increasing accuracy. Comprehensive experimental analysis is performed to evaluate the performance of the proposed multiplier in terms of area, delay, power consumption, and accuracy. The results show that our suggested design improves at most 29% of power consumption, 11% of delay, and 55% of the area rather than an exact multiplier. Moreover, the performance of our multipliers is investigated based on the peak signal noise ratio (PSNR) for processing two images, which lead to 56.65 and 23.6 dB.

Exact and approximate multiplications for signal processing applications

Approximate computing is an emerging technique that can be used for developing power, area and delay efficient circuits at the cost of loss of accuracy. This paper investigates the possibility of efficient exact multipliers through the use of improved compressors and counters and thereafter deriving approximate multiplier structures to achieve a higher percentage of logic optimization at the expense of the lowest possible error. NAND gate based array structure with reduced complexity is used for generating the partial products for both the exact and approximate multipliers. Two variants of the efficient exact multiplier are proposed. The proposed exact multiplier EM-1 is area and power efficient, whereas EM-2 is delay and energy efficient. Two variants of 4:2 compressors are introduced for developing approximate multipliers. The proposed multipliers excel most of the state-of-the-art existing multipliers in terms of the important performance metrics. The proposed exact and approximate multiplier designs are employed for developing ECG denoising FIR filter for the elimination of power line interference and the corresponding performance improvement is illustrated. Cadence RTL compiler v11.10 with GPDK 45 nm standard cell library is used for the synthesis. The simulation of all the multipliers is done by running a test bench program using modelsim.

Sharp Bernstein-type inequalities for Fourier-Dunkl multipliers

A method for the proof of analogues of the classical Bernstein, Riesz and Boas inequalities for differentiation and difference operators defined by means of multipliers in terms of the Fourier-Dunkl transform is developed. This method is based on Civin-type interpolation formulae. Some of the inequalities obtained are sharp in the uniform norm. Bibliography: 42 titles.

Design and Analysis of Multipliers for DNN application using approximate 4:2 Compressors

The demand for Deep Learning applications in resource constrained devices is booming in recent years. Theuse of Deep Neural Network (DNN) is the leading method in these applications which has error resilient nature.This allows the use of Approximate Computing for efficient computation to leverage efficiency accuracy tradeoff by replacing Approximate Multiplier in place of exact multipliers. In this paper we proposed ApproximateCompressors and compared them in different cases of 8 bit integer dadda multipliers in terms of the Error metricsand accuracy in real life object classification applications. The approximate multipliers are designed using differentcompressors and used to perform multiplication in ResNet. We have proposed two approximate compressorsdesigns Design 1 and Design 2.The proposed 4:2 compressors design shows the more correct outputs and lessWorst Case Relative Error (WCRE) in the range of 2-16. Our proposed 4:2 compressor Design1 is utilized in themodified Reduction circuitry of dadda multiplier and shows the accuracy of 81.6 % for DNN application

Area efficient and high-speed Galois field multiplier for mobile edge computing devices

Mobile Edge Computing is one of the prominent technologies in 5G communication to improve throughput, scalability and reliability. In this work, area efficient and high-speed multipliers are implemented using finite field (Galois field) arithmetic which are widely utilised by edge computing devices. The performance of finite field multiplication operation is closely related to finite field elements representation. The proposed polynomial-based finite field bit parallel systolic array multiplier is able to achieve almost double the speed of existing multipliers. There is a considerable reduction in area and power for the proposed word-level normal basis finite field multiplier compared to the existing multipliers. The results clearly indicate that the proposed method improves the efficiency of finite field multipliers in terms of area, delay or power consumption. In order to process the real-time data efficiently, both the local computing and data offloading are carried out in developing a joint computation algorithm. The trade-off analysis between local computing and data offloading shows that local computing plays a more important role when the data size is small, but data offloading is preferred when the data size increases.

Multipliers and Duality for Group Actions

We define operator-valued Schur and Herz–Schur multipliers in terms of module actions, and show that the standard properties of these multipliers follow from well-known facts about these module actions and duality theory for group actions. These results are applied to study the Herz–Schur multipliers of an abelian group acting on its Pontryagin dual: it is shown that a natural subset of these Herz–Schur multipliers can be identified with the classical Herz–Schur multipliers of the direct product of the group with its dual group.

Multipliers and unicentral Leibniz algebras

In this paper, we prove Leibniz analogues of results found in Peggy Batten’s 1993 dissertation. We first construct a Hochschild–Serre-type spectral sequence of low dimension, which is used to characterize the multiplier in terms of the second cohomology group with coefficients in the field. The sequence is then extended by a term and a Ganea sequence is constructed for Leibniz algebras. The maps involved with these exact sequences, as well as a characterization of the multiplier, are used to establish criteria for when a central ideal is contained in a certain set seen in the definition of unicentral Leibniz algebras. These criteria are then specialized, and we obtain conditions for when the center of the cover maps onto the center of the algebra.

The nuclear trace of periodic vector‐valued pseudo‐differential operators with applications to index theory

AbstractIn this paper we investigate the nuclear trace of vector‐valued Fourier multipliers on the torus and its applications to the index theory of periodic pseudo‐differential operators. First we characterise the nuclearity of pseudo‐differential operators acting on Bochner integrable functions. In this regards, we consider the periodic and the discrete cases. We go on to address the problem of finding sharp sufficient conditions for the nuclearity of vector‐valued Fourier multipliers on the torus. We end our investigation with two index formulae. First, we express the index of a vector‐valued Fourier multiplier in terms of its operator‐valued symbol and then we use this formula for expressing the index of certain elliptic operators belonging to periodic Hörmander classes.

High accurate multipliers using new set of approximate compressors

Approximate multipliers play vital role in the error-resilience applications by balancing accuracy and power efficiency. In this article, we improved the accuracy of approximate multipliers using a set of proposed approximate compressors which are able to compress any number of inputs to arbitrary numbers of output bits. To achieve better accuracy, probability of being one in the input bits is used to determine the compression ratio. Also, a novel scheme for allocating approximate and exact compressors in PPM is proposed to decrease column reduction stages. Error metrics namely PE, MED, MRED, and NED are calculated to evaluate accuracy of our approximate compressors. Experimental results show an average of 35% accuracy improvement, in comparison with the previous approximate compressors. We implemented four different multipliers including 8-bit, 12-bit, 16-bit, and 24-bit multipliers to prove goodness of our proposed algorithm. The multipliers are designed by Verilog and synthesized in a 45-nm standard CMOS technology. The experimental results demonstrate major accuracy superiority of our proposed multipliers in comparison with the state of the art approximate multipliers in terms of MED, MRED, and NED. According to the experimental results, the delay is improved 22%, on average, compared with exact multipliers.

Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach

With the advancement in technology, various designs of multipliers offering low power consumption, high speed and less area have been proposed by many researchers. The main concern of electronic system designers is the energy minimization with the minimum penalty in speed and area for designing portable devices. Recent development focuses on the design of low-power multiplier for applications like biomedical signal processing requiring the least power consumption and delay-tolerant multiplier. This paper proposes a power-efficient design of the Wallace tree multiplier using a power-efficient 7:3 counter consisting of multiplexer and ex-or gates. The maximum power of the multiplier is consumed in the partial product tree reduction, and hence, in the proposed counter-based modular Wallace tree (CBMW) multiplier partial products are reduced using sequential 7:3 counter and the multi-bit addition in a single column reduces the complexity of the multiplier due to improvement in the locality. These proposed changes make design low power and scalable. The hardware utilization is minimum when a single 7:3 counter is used in partial product tree reduction per stage. The proposed multiplier is implemented in the Xilinx ISE design suite 14.7 using Verilog language on Spartan 3E FPGA. The design is also synthesized in Synopsys Design Compiler using 180 nm CMOS technology cell library. The corner analysis of the proposed design is performed in Synopsys PrimeTime, and the design meets all timing specifications. Also, the multiply and accumulate (MAC) unit is designed using the proposed multiplier to demonstrate an application of it. The detailed comparison is performed for 8-bit as well as 16-bit operands, and it shows that the CBMW multiplier gives better delay performance and consumes the least power compared to existing multipliers. It is proved to be an efficient multiplier in terms of Power-Delay Product (PDP). The power consumption of the proposed 16 $$\times $$ 16 multiplier is 88.16 mW and 87.7 $$\mu $$ W for Spartan 3E FPGA and ASIC design for 180 nm technology, respectively. It provides a promising performance for FPGA as well as for the ASIC platform.

Approximate Karatsuba multiplier for error-resilient applications

Approximate computing is one of the most trending topics for research since the introduction of error-resilient applications. Approximate arithmetic helps reduce the power consumption, hardware utilization and delay time at the expense of accuracy. Out of all arithmetic operations, multiplication is the most widely used and it forms the crucial section in many applications. Therefore, it is necessary to optimize it as per the requirement of a system. This paper proposes an algorithm for approximate multiplication based on Karatsuba multiplication method which is compared with an existing approximate hybrid Wallace tree multiplier and it is found that the proposed approximate Karatsuba multiplier is better than existing approximate hybrid Wallace Tree multiplier in terms of hardware, latency as well as accuracy. The performance of proposed multiplier is also evaluated with the help of a application of image processing and it is found that proposed multiplier gives similar results as exact multiplier unit. Both the multipliers are implemented in Verilog HDL using Vivado 2018.3.

A Distributed Active Set Method for Model Predictive Control

Abstract This paper presents a novel distributed active set method for model predictive control of linear systems. The method combines a primal active set strategy with a decentralized conjugate gradient method to solve convex quadratic programs. An advantage of the proposed method compared to existing distributed model predictive algorithms is the primal feasibility of the iterates. Numerical results show that the proposed method can compete with the alternating direction method of multipliers in terms of communication requirements for a chain of masses example.