Multiple Small Arrays Research Articles

Binaural rendering from microphone array signals of arbitrary geometry.

A method of binaural rendering from microphone array signals of arbitrary geometry is proposed. To reproduce binaural signals from microphone array recordings at a remote location, a spherical microphone array is generally used for capturing a soundfield. However, owing to the lack of flexibility in the microphone arrangement, the single spherical array is sometimes impractical for estimating a large region of a soundfield. We propose a method based on harmonic analysis of infinite order, which allows the use of arbitrarily placed microphones. In the synthesis of the estimated soundfield, a spherical-wave-decomposition-based binaural rendering is also formulated to take into consideration the distance in measuring head-related transfer functions. We develop and evaluate a composite microphone array consisting of multiple small arrays. Experimental results including those of listening tests indicate that our proposed method is robust against change in listening position in the recording area.

Wave-body interactions among energy absorbers in a wave farm

A semi-analytical method is developed to investigate surface-wave interactions among an array of wave-energy converters, each modeled as a truncated cylinder, and the interaction effects on power absorption from the array is studied. Each cylinder can have independent movements with six degrees of freedom. The method of matched eigen-function expansions is applied to solve the wave radiation problem. To achieve fast computation, effects of evanescent modes of local scattering waves from one cylinder is neglected in the near fields of neighboring cylinders, but the far-field radiated waves are retained. Wave-exciting forces and moments on an individual cylinder or a group of cylinders, situated among an array, are evaluated by a new, generalized form of the “Haskind relation” applicable to an array of arbitrary configuration, which only requires the solution to the radiation problem. Hydrodynamic properties and wave-exciting loads are presented for arrays of different configurations. This efficient computation facilitates investigating wave-interaction effects on the optimal power output of a cylinder array. Effects of the cylinder numbers, their spacing, and the layout geometry on power extraction are discussed. The interaction factor for a large wave farm consisting of multiple small arrays was evaluated by the current method combined with the point-absorber approximation.

MT-ADRES: multi-threading on coarse-grained reconfigurable architecture

The coarse-grained reconfigurable architecture ADRES (architecture for dynamically reconfigurable embedded systems) and its compiler offer high instruction-level parallelism (ILP) to applications by means of a sparsely interconnected array of functional units and register files. As high-ILP architectures achieve only low parallelism when executing partially sequential code segments, which is also known as Amdahl's law, this article proposes to extend ADRES to MT-ADRES (multi-threaded ADRES) to also exploit thread-level parallelism. On MT-ADRES architectures, the array can be partitioned in multiple smaller arrays that can execute threads in parallel. Because the partition can be changed dynamically, this extension provides more flexibility than a multi-core approach. This article presents details of the enhanced architecture and results obtained from an MPEG-2 decoder implementation that exploits a mix of thread-level parallelism and instruction-level parallelism.

Optimal static 2-dimensional screen subdivision for parallel rasterization architectures

Designers of computer graphics hardware have used increasing device counts available from IC manufacturers to increase parallelism using techniques such as putting a longer pipeline of data path elements on integrated circuits, or developing designs which use an array of processors. Pixel-Planes 1–5 and PixelFlow ‡ ‡ Pixel-Planes 1–5 and PixelFlow were developed at the University of North Carolina. are examples of architectures which use an array of pixel processors for rasterization. Early generations of Pixel-Planes attempted to make these arrays as large as the display providing one processor for each display pixel. Later generations improved performance by grouping processors into multiple smaller arrays, subdividing the screen into sections of a corresponding size and having the arrays independently process the screen subdivisions. This paper describes simulations which were performed to determine the optimum size subdivision for a graphics computer which uses Pixel-Planes type parallelism, i.e. static two dimensional screen subdivision parallel polygon rasterization. We then develop a mathematical approach to determining the optimal subdivision size and show that it agrees well with the experimental data. For special purpose architectures we show that the optimal size depends not only on the polygon size but also on the silicon area consumed by the rasterizer overhead. The mathematical approach can be directly applied to special purpose architectures, and we show how it can be modified for use in analyzing algorithms developed for general purpose architectures such as the Intel Touchstone or Paragon, or the Thinking Machines CM-5.