Multiple-gated Transistor Research Articles

A power amplifier with bandwidth expansion and linearity enhancement in 130 nmcomplementary metal‐oxide‐semiconductorprocess

A power amplifier with bandwidth expansion and linearity enhancement in 130 nm complementary metal-oxide-semiconductor (CMOS) process is presented. A LC connected dual-resonant network is proposed to achieve good broadband performance and high out-band rejection capability simultaneously. Furthermore, the advanced multiple-gated transistor technique is employed to cancel out odd-order intermodulation and harmonic distortions. The PA is implemented in 130 nm CMOS process with an area of 1.17 mm × 0.92 mm. Measurement results demonstrate that the PA exhibits a peak power gain of 8 dB with a relative bandwidth of 38% while maintaining a low reflection coefficient of −23.2 dB, maximum saturation output power of 15.6 dBm, maximum OP1dB and OIP3 of 14.3 dBm and 19 dBm, and a peak power added efficiency of 21.3%, respectively. In addition, an out-band rejection of 20 dB and 23.2 dB at 6.1 GHz and 14 GHz are measured.

A New Tune-Dependent Multiple-Gated Transistor Linearization Technique

In this paper, a new multiple-gated transistor (MGTR) linearization technique is presented. To simultaneously keep linearity and tuning capability of proposed operational transconductance amplifier (OTA), the auxiliary transistors which are employed for [Formula: see text] cancellation of differential pair (DP) stage are body-driven through a tune-dependent voltage. By this way, the third-order nonlinearity of DP is reduced for a wide range of transconductance values from 5.1 to 35.6[Formula: see text][Formula: see text]A/V. The OTA works with 1.2[Formula: see text]V supply voltage and its power consumption changes between 137.4 and 156[Formula: see text][Formula: see text]W at the entire tuning range. For [Formula: see text][Formula: see text][Formula: see text]A/V ([Formula: see text][Formula: see text]V) and for 0.6[Formula: see text][Formula: see text] input voltage, the simulation results show 6[Formula: see text]dB reduction in the total harmonic distortion (THD) of proposed OTA when the MGTR linearization technique is used and 15[Formula: see text]dB reduction when the tune-dependent body driving is also utilized. The proposed OTA is employed in a third-order low-pass Butterworth filter which is tunable from 2 to 18[Formula: see text]MHz. The in-band IIP3 of filter is 16.9 and 12.4[Formula: see text]dBm, respectively, for 2 and 18[Formula: see text]MHz cutoff frequencies while the two-tone input voltage is applied at 1[Formula: see text]MHz.

Linearized CMOS Darlington Feedback Amplifier for Wireless Communications

In this paper, the design of a fully-integrated CMOS Darlington feedback amplifier incorporating multiple-gated transistor linearization is presented. Simulation results have yielded a peak S21 power gain of 10.3 dB and a unity gain bandwidth of 16 GHz with better than -10 dB S11. The simulation results show a 7 dB IIP3 improvement and IM3 improvement of 18 dBc at output power of -10 dBm. The proposed linearized Darlington feedback amplifier was designed using the 0.13μm CMOS technology.

A HIGH GAIN AND LOW NOISE CMOS GILBERT MIXER WITH IMPROVED LINEARITY BASED ON MGTR AND SWITCHED BIASING TECHNIQUE

This brief presents the design of an improved linear Gilbert mixer with high conversion gain and low noise figure by using multiple gated transistor (MGTR) and switched biasing technique. This mixer operates at a radio frequency (RF) of 2.4GHz with a local oscillator (LO) power of 5dBm in UMC 180nm process. The MGTR method is used to increase the linearity of the proposed mixer by the parallel combination of transconductance stage transistors and auxiliary transistors. The switched biasing technique is adopted for a current source instead of static biasing which lowers the noise figure. The integration of two techniques result in a conversion gain (CG) of 10.9dB and a noise figure (NF) of 7.2dB with the third order input intercept point (IIP3) of 10.79dBm. This proposed mixer circuit consumes 4.2mW power from a supply voltage of 1.8V.

Linearity improvement of gm-boosted common gate LNA: Analysis to design

This paper proposes a highly linear low noise amplifier (LNA) for ultra-wideband applications. It focuses on linearization of the basic active gm-boosted common gate (CG) LNA circuit by exploring the nonlinearity coefficients using the generalized nonlinearity model. Mathematical analysis shows that in active gm-boosted CG LNA, the third input intercept point (IIP3) of LNA depends on interaction between main and auxiliary amplifiers. The multiple gated transistor (MGTR) technique, which was previously developed, is applied to an active gm-boosted CG amplifier based on linearity analysis. Also an improved shunt peaking bandwidth (BW) extension technique is proposed in this paper that extends the flat BW up to 200%. Post-layout simulation results of the proposed LNA circuit in a 180nm RF CMOS process show +11dBm of IIP3 that indicates 12dB improvement comparing with conventional structures. The proposed wideband LNA has a voltage gain of 16dB,−3dB bandwidth from 1GHz to 10.3GHz, and minimum noise figure (NF) of 4.1dB. The simulated S11 is better than −10dB in whole frequency range while the LNA core draws 6mA from a single 1.8V DC voltage supply.

A 0.6-V $+$4 dBm IIP3 $LC$ Folded Cascode CMOS LNA With $g_{m}$ Linearization

This brief presents the design guidelines of LNAs under low-supply-voltage condition with respect to linearity and demonstrates an LNA that has excellent performance even with an extremely low supply voltage. Under a low supply voltage, the drain conductance nonlinearity, which can be ignored in a high supply voltage, is important, as well as the transconductance nonlinearity. Therefore, this brief linearizes transconductance using the multiple-gated transistor (MGTR) technique and tries to obtain high drain conductance linearity with the folded cascode configuration. The proposed 900-MHz LNA is designed with a 130-nm CMOS process. The measurement results show a gain of 15.4 dB, a noise figure of 1.74 dB, and an IIP3 of 4.09 dBm, which is the result of the 4.94-dB improvement over a conventional folded cascode LNA at 5.16-mW power consumption with a 0.6-V supply voltage.

Design and analysis of a WLAN CMOS power amplifier using multiple-gated transistor technique

This article focused on 5.2 GHz highly integrated power amplifier for IEEE 802.11a WLAN application. Multiple-gated transistor technique was used to improve linearity. A new approach for choosing the bias voltage of auxiliary transistor by analyzing the shift of gate bias is used in the design. The simulated results of the proposed two-stage differential power amplifier indicate 25.28 dBm P1-dB, 32.87% PAE, and 26.18 dBm saturated output power with a 5.2 dB P1-dB improvement compared to conventional single transistor amplifier. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011. © 2011 Wiley Periodicals, Inc.

High linearity 23–33 GHz SOI CMOS downconversion double balanced mixer

A highly linear downconversion mixer is demonstrated in a digital 45 nm silicon on insulator (SOI) CMOS process. The mixer downconverts the radio frequency signal from 23–33 GHz to 12 GHz intermediate frequency. By using a multiple gated transistor (MGTR) technique and suppressing the large signals at twice of the LO frequency at the drain nodes of transconductors, the mixer achieves an input referred third-order intercept point (IIP3) of 17 dBm, a conversion power gain of −0.5 dB, and a single side band noise figure of 12.1 dB at the radio frequency of 28 GHz. This is the first CMOS MGTR Gilbert mixer operating near millimetre-wave frequencies and fabricated using SOI MOS transistors with a floating body.

A Common-Gate Amplifier With Transconductance Nonlinearity Cancellation and Its High-Frequency Analysis Using the Volterra Series

A common-gate (CG) amplifier employing a transconductance nonlinearity cancellation technique is designed for transmitter circuitry. The major contributor to the third-order nonlinearity in the CG amplifier is the second derivative of the transconductor ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">''</sup> ), which is the same case with a common-source (CS) amplifier. The multiple gated transistor (MGTR) technique, which was developed in the CS amplifier for transconductor nonlinearity cancellation, is applied to a CG amplifier. However, in the CG amplifier, the input driving impedance of a CG amplifier comprises a voltage-current feedback loop. Thus, a second-order interaction with feedback components generates a third-order distortion that limits input-referred third-order intercept point (IIP3) enhancement. This feedback influence on IIP3 can be relaxed by eliminating harmonic feedback components. Based on high-frequency analysis on a CG amplifier using the Volterra series, an RF current source is proposed to replace the conventional current source in the CG amplifier to eliminate harmonic feedback components at 2omega and Deltaomega. By adapting the CG MGTR technique combined with the RF current source, a 2.4-GHz driver amplifier for Wibro/Wimax applications was implemented using a 0.18-mum 1P 6M CMOS process. Measurement results show a 9-dB output third-order intercept point improvement at an output power of -3 dBm.

0.7 V supply highly linear subthreshold low‐noise amplifier design for 2.4 GHz wireless sensor network applications

AbstractA low supply voltage and highly linear subthreshold CMOS low noise amplifier (LNA) for 2.4 GHz wireless sensor network applications is presented in this letter. We applied multiple gated transistor (MGTR) technique in subthreshold region to compensate the linearity degradation of low supply cascode topology. Moreover, the feedback capacitor, Cf is used to enhance the power gain of amplifier without additional dc‐power dissipation. The proposed LNA has gain of 13.1 dB, noise figure (NF) of 3.8 dB, and −2.5 dBm IIP3 while dissipating only 0.49 mW from 0.7 V supply. The LNA has been designed using a 0.13 μm 1P8M standard CMOS process with top metal thickness of 3.3 μm. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1316–1320, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24333

Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration

In this study, a novel multiple-gated (MG) thin-film transistor (TFT) with poly-Sinanowire (NW) channels is fabricated using a simple process flow. In the proposed newtransistors, poly-Si NWs were formed in a self-aligned manner and were preciselypositioned with respect to the source/drain, and the side-gate. Moreover, the NW channelsare surrounded by three gates, i.e., top-gate, side-gate and bottom-gate, resulting in muchstronger gate controllability over the NW channels, and greatly enhanced deviceperformance over the conventional single-gated TFTs. Furthermore, the independentlyapplied top-gate and/or bottom-gate biases could be utilized to adjust the thresholdvoltage of NW channels in a reliable manner, making the scheme suitable for practicalapplications.

A low-power highly linear cascoded multiple-gated transistor CMOS RF amplifier with 10 dB IP3 improvement (Revised)

A low-power highly linear CMOS RF amplifier circuit composed of a Multiple-Gated common-source FET TRansistor (MGTR) in cascode configuration is reported. In an MGTR amplifier, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/ of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output. IP3 improvement as large as 10 dB has been obtained from an experimental RF amplifier designed at 900 MHz and fabricated using 0.35 /spl mu/m BiCMOS technology using only CMOS at a similar power consumption and gain as those obtainable from conventional cascode single gate transistor amplifiers.