Multiphase Switched-capacitor Research Articles

A low output ripple and high security on‐chip voltage regulation based on Fourier transform

SummaryIn modern integrated circuits (ICs), integrating workload‐agnostic multiphase switched‐capacitor (SC) voltage converters on‐chip is an effective way to reduce the transient response time, improve the security, and boost the power efficiency. However, a stochastic and unbalanced active sequence within the multiphase SC converter may undermine the corresponding output voltage ripple significantly. In this paper, a novel algorithm that is based on Fourier transform is capable of efficiently mitigating the amplitude of output ripple without compromising its security drastically. To achieve this objective, firstly, the output ripple of a single‐phase SC converter needs to be approximated with a Fourier expansion. Then the relationship between the output ripple and active phase sequence of a multiphase SC converter can be modeled precisely under the assistance of Fourier transform. After maximizing the randomness of the active sequences of the multiphase SC converter under different workload conditions and filtering a certain number of phase sequences with unsatisfied output ripples, the optimum control algorithm is generated. As shown in the result, the amplitude of output ripple of a multiphase SC converter can be reduced by 69.5% with negligible security loss and less than 29% power and area overhead under the 55 nm process design kits (PDK).

Analysis and Design of Multiphase, Reconfigurable Switched-Capacitor Converters

A comprehensive framework for the analysis and design of multiphase, reconfigurable switched-capacitor (SC) dc-dc converters is presented. A generalized method, utilizing graph theory and network analysis, is first proposed, which enumerates all attainable ideal conversion ratios for a given SC converter structure. From this analysis, the performance limits of multiphase SC converters are expanded, and a reconfigurable, multiphase SC dc-dc converter is proposed. The converter utilizes a programmable and optimized switching configuration that can generate an increased number of attainable ideal conversion ratios for the given number of capacitors and switching states. This property allows the converter to maintain high efficiency across a wide range of operating conditions and achieve very high step-up and step-down conversion ratios. A set of sample switching sequences are provided to generate any attainable ideal conversion ratio, for up to four capacitors, using a minimal number of switching states. An experimental prototype of the converter has been designed and fabricated as an integrated circuit using 0.35-μm CMOS technology to validate the performance.

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Analysis of switched-capacitor circuits using driving-point signal-flow graphs

This paper extends the driving-point signal-flow graphs to switched-capacitor (SC) circuits by introducing a new theoretical element: an auxiliary voltage source that transfers no charge. In contrast to existing SFG methods, our method has no restrictions as to what types of SC circuits can be analysed, it requires no equivalent circuits or tables, and it works with two-phase as well as multi-phase SC circuits of any complexity. Compared to charge-equation matrix methods, it requires more effort, but is better suited for hand analysis because it makes causal relationships visible. Three illustrative examples are given to show the efficiency of the method and present a few application hints: a voltage doubler, the standard SC integrator, and a four-phase circuit simulating an inductor.

A Family of Dual-Phase-Combined Zero-Current Switching Switched-Capacitor Converters

A family of dual-phase-combined resonant switched-capacitor (SC) converters with a similar structure is presented in this paper. Comparing with their conventional single-phase version, each of the proposed dual-phase converters is more than just a switched capacitor but also provides the service of two phases operated in the fully complementary manner. This design provides a more stable output voltage with low ripple and significantly reduces the quantity of switches. These converters therefore have the common features of smaller size, lower cost, and higher power density than the conventional multiphase SC converters. With the zero-current switching technique, the proposed converters also possess high-power conversion efficiency. The detailed analysis of the circuit operation and voltage ripples is presented. Experimental results are also provided to confirm the performance of the new family of converters.

Design and Analysis of Multistage Multiphase Switched-Capacitor Boost DC–AC Inverter

A closed-loop multistage ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$n$</tex> </formula> -stage) multiphase ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$p$</tex> </formula> -phase) switched-capacitor boost dc–ac inverter (MPSCI) is proposed by combining a variable-phase control (VPC) and sinusoidal pulsewidth-modulation (SPWM) technique for low-power step-up inversion/regulation. Its power stage contains two parts: an MPSC booster (front) and an H-bridge (rear). An <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$n$</tex></formula> -stage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$p$</tex></formula> -phase MPSC is for an inductor-less boost dc–dc conversion, where <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$n$</tex></formula> voltage doublers are in series for boosting voltage gain up to <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$2^{n}$</tex> </formula> at most. For improving efficiency, VPC is suggested to realize a variable multiphase operation by changing phase number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$p$</tex></formula> and topological path for more suitable gain level. An H-bridge is employed for dc–ac conversion, where four switches are controlled by SPWM not only for full-wave operation, but also for enhancing output regulation as well as robustness to source/loading variation. The analysis and design include an MPSCI model, steady-state/dynamic analysis, conversion ratio, power efficiency, stability, capacitance selection, total harmonic distortion (THD), filter, and control design. Finally, the closed-loop MPSCI is simulated, and the hardware is implemented and tested. All results are illustrated to show the efficacy of the proposed scheme.

HIGH-EFFICIENCY 2-STAGE MULTIPHASE SWITCHED-CAPACITOR CONVERTER VIA VARIABLE-PHASE AND PWM CONTROL

A closed-loop scheme of 2-stage multiphase switched-capacitor (MPSC) converter is proposed by combining variable-phase control (VPC) and pulse-width-modulation (PWM) technique for low-power DC-DC step-up conversion and high-efficiency output regulation. In this MPSC, there are 2 voltage doublers in series for boosting voltage gain up to 4 at most. Here, VPC is suggested to improve power efficiency, especially for the lower output voltage. It realizes a variable multiphase operation by changing MPSC topological path for more suitable level of voltage gain (4x/3x/2x/1x) according to the desired output. Besides, PWM is adopted for better output regulation not only to compensate dynamic error, but also to reinforce robustness against source/loading variation. Further, the theoretical analysis and design include: MPSC model, steady-state analysis, power efficiency, conversion ratio, ripple percentage, capacitance selection, stability, and control design. Finally, the closed-loop MPSC is simulated, and the hardware implementation is realized and tested. All the results are illustrated to show the efficacy of the proposed scheme.

Analogue realisation of integrated FIR filters

The paper presents a unified approach to the design of analogue finite impulse response (FIR) filters. As an analogue realisation the multiphase switched-capacitor technique was chosen owing to its high precision and high packing density in CMOS technology. The proposed design method allows different structures of the filters containing different number of amplifiers to be controlled by different clock signals, providing the best solution taking into account the maximum frequency range and the cost of the chip. Four prototypes of the filters were designed as one integrated circuit using 2 µm double-poly CMOS technology. Measurements made on the test chip confirm the computer simulations. Implementation of interpolation units for analogue FIR filters derived from transversal direct diagram of digital FIR filters is discussed. The linear interpolator provides an improvement to the frequency characteristic of the prototype analogue FIR filter. Computer simulation of the resulting filter has been performed.

Analysis of multiphase switched-capacitor networks using the node method

Switched-capacitor networks (SC networks) deserve attention, since they provide an optimum method for implementing precision filters in a monolithic integrated circuit. Classical SC networks contain capacitors and two- phase switches (see [1–4]). In certain applications it is preferable to use multiphase networks (see [5]), but the methods for analyzing them are complex (see [1]). The present paper proposes a comparatively simple method for the mathematical description of multiphase SC networks. It is a generalization of the method of analysis developed in [2]. Moreover, the present work emphasizes the fact that SC networks belong to a more general class of discrete time-varying networks.

Direct analysis of multiphase switched-capacitor networks using signal-flow graphs

A by-inspection analysis method for multiphase switched-capacitor (SC) networks using signal-flow-graph (SFG) techniques is presented. The method is quite general; no restrictions on the networks are required. It is also very simple and direct in the sense that it allows an immediate, by-inspection derivation of the SFG merely on the basis of a given SC network. The method is primarily useful for the hand analysis and design of small and medium-size SC networks (e.g. building blocks of modular SC system). It may also serve as a tool for symbolic computer analysis and for the synthesis of general multiphase SC networks. Illustrative examples demonstrate the simplicity and efficiency of the method.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Direct by-inspection derivation of signal-flow graphs for multiphase stray-insensitive switched-capacitor filters

A direct by-inspection method for the derivation of signal-flow graphs (SFGs) for multiphase stray-insensitive switched-capacitor (SC) networks is presented. Compared to this method, others are relatively complicated and not direct in the sense that they require intermediate steps. The multiphase analysis presented in the paper is a generalisation of the method shown previously (see A. Dabrowski, 1987), where a by-inspection signal-flow graph analysis of biphase SC networks is described. Whereas only a brief summary of the derivation rules and an example are given here, the underlying theory will be published elsewhere.< >

Explicit formulas for analyzing general switched-capacitor networks

Explicit formulas are derived for analyzing switched-capacitor (SC) networks of the most general type. Using these formulae a simple analysis method is obtained to compute the frequency-domain responses of multiphase SC networks containing real resistors. The formulas presented in this paper make it possible to specify arbitrary switch timing waveforms and to insert arbitrary built-in input and/or output sampling functions. Most of the practical linear SC analysis problems can be solved efficiently by these formulas without special knowledge of the lengthy derivations.

On robustness of the stability of multiphase switched-capacitor two-ports

For any prescribed rational transfer function H(z) every pole of which is inside the unit circle |z| = 1 , a set of multiphase switched-capacitor (MSC) two-ports denoted by K_{H} is defined. The main theorem proved in this paper states that any MSC two-port belonging to K_{H} does not have the robust stability under small perturbation of the capacitors. The presented set of MSC two-ports is so general as to include various types of SC filters designed such that they simulate the nodal equations of the analog reference ladders. In order to show the significance of the main theorem the robustness of the stability of two types of high-pass SC filters is examined. These examples show that an impedance-scaling technique does not always provide a solution to the problem of the high-pass filter realization based on the exact simulation of reactance ladders by the bilinear s-z transformation. In the Appendix, a theorem which gives a sufficient condition for an MSC two-port to be stable in a robust sense is presented.

Poles, zeros, and their sensitivities in switched-capacitor networks

This paper provides theoretical steps to obtain pole and zero sensitivities of multiphase switched-capacitor networks having equal time slots in all phases. Both sampled and held or full signals can be used. Only approximate values of the poles and zeros are needed for initial estimates. Exact values are obtained by Newton-Raphson iteration.

Compact matrix scheme for use in computer analysis of switched-capacitor networks

The matrices that normally occur in the analysis of multiphase switched-capacitor networks are quite large and very sparse. A technique is presented which reduces the matrix order and increases the fill. Storage requirements are minimised and the arithmetic handling of large arrays is reduced without recourse to sparse matrix procedures.

Time, frequency, and z-domain modified nodal analysis of switched-capacitor networks

A rigorous and general derivation of the modified nodal equations needed for a time, frequency and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">z</tex> -domain analysis of multiphase switched-capacitor networks is given. Also a general equivalent circuit for switched-capacitor networks is derived. This technique allows to handle continuous coupling, piecewise-constant inputs as well as continuous inputs. These results can be used to adapt existing circuit analysis programs, based on modified nodal analysis, for efficient simulation of switched-capacitor networks.

Analysis of multiphase switched-capacitor (m.s.c) networks using the indefinite admittance matrix (i.q.m.)

In this paper, the indefinite admittance matrix (i.a.m.) method for the analysis of switched-capacitor (s.c.) networks1 will be expanded for the analysis of multiphase switched-capacitor (m.s.c.) networks. Such networks comprise active gain elements, capacitors, and switches operated by an arbitrary number of nonoverlapping clockphases. Included as part of this analysis is the derivation of an equivalent-circuit representation of m.s.c. networks which is compatible with classical-circuit theoretical considerations. The analysis method lends itself well to computer processing. A computer algorithm and examples of the proposed method are given.