Multimedia Card Research Articles

Exploiting RPMB authentication in a closed source TEE implementation

Embedded Multimedia Cards (eMMCs) provide a protected memory area called the Replay Protected Memory Block (RPMB). eMMCs are commonly used as storage media in modern smartphones. In order to protect these devices from unauthorized access, important data is stored in the RPMB area in an authenticated manner. Modification of the RPMB data requires a pre-shared authentication key. An unauthorized user cannot change the stored data.On modern devices, this pre-shared key is generated and used exclusively within a Trusted Execution Environment (TEE) preventing attackers from access. In this paper, we investigate how the authentication key for RPMB is programmed on the eMMC. We found that this key can be extracted directly from the target memory chip. Once obtained, the authentication key can be used to manipulate stored data. In addition, poor implementation of certain security features, aimed at preventing replay attacks using RPMB on the host system can be broken by an attacker. We show how the authentication key can be extracted and how it can be used to break the anti-rollback protection to enable data restoration even after a data wipe operation has been completed.Our findings show that non-secure RPMB implementations can enable forensic investigators to break security features implemented on modern smartphones.

Assessing the Role of Program Suspend Operation in 3D NAND Flash Based Solid State Drives

3D NAND Flash is the preferred storage medium for dense mass storage applications, including Solid State Drives and multimedia cards. Improving the latency of these systems is a mandatory task to narrow the gap between computing elements, such as CPUs and GPUs, and the storage environment. To this extent, relatively time-consuming operations in the storage media, such as data programming and data erasing, need to be prioritized and be potentially suspendable by shorter operations, like data reading, in order to improve the overall system quality of service. However, such benefits are strongly dependent on the storage characteristics and on the timing of the single operations. In this work, we investigate, through an extensive characterization, the impacts of suspending the data programming operation in a 3D NAND Flash device. System-level simulations proved that such operations must be carefully characterized before exercising them on Solid State Drives to eventually understand the performance benefits introduced and to disclose all the potential shortcomings.

Command queue-aware host I/O stack for mobile flash storage

Abstract Recently, mobile storage devices such as an embedded multimedia card (eMMC) and universal flash storage (UFS) support command queuing. However, the current Linux I/O stack is not designed considering flash memory devices that support command queuing. In this paper, we observe the I/O performance at a command queue-supporting device and introduce several pitfalls of the current host I/O stack. First, although the latency of synchronous I/O requests can be increased due to the priority inversion in the command queue, the Linux I/O scheduler has no concern about the issue. Second, although the I/O bandwidth is determined by the total size of pending I/O requests rather than the total number of them in the command queue, the current I/O scheduler does not have a size-based scheduling scheme. Third, there can be interference between different types of requests in the command queue degrading the overall I/O performance. To resolve these problems, we introduce a novel command queue-aware host I/O stack, which consists of three techniques, latency-aware throttling, aggressive readahead, and interference-preventive scheduling. The experiments show that the command queue-aware techniques can improve both the foreground synchronous request latency and the background sequential I/O bandwidth when the two different types of tasks run concurrently.

A Novel B-Tree Index with Cascade Memory Nodes for Improving Sequential Write Performance on Flash Storage Devices

Flash storage devices such as solid-state drives and multimedia cards have been widely used in various applications because of their fast access speed, low power consumption, and high reliability. They consist of NAND flash memories that perform slow block erasures before overwriting data on a prewritten page. This characteristic can lead to performance degradation when applying the original B-tree on the flash storage device without any changes. Although various B-trees have been proposed for flash memory, they still require many flash operations that degrade overall performance. To address the problem, we propose a novel B-tree index structure that reduces the number of write operations and improves the sequential writes by employing cascade memory nodes. The proposed B-tree index structure delays the updates for the modified B-tree nodes and later performs batch writes in a cascade manner. Also, when records with continuous key values are sequentially inserted, the proposed B-tree index structure does not split the leaf node so that it improves write throughput and page utilization. Through mathematical analysis and experimental results, we show that the proposed B-tree index structure always yields better performance than existing techniques.

Design and development of multi media cards as a motorized vehicle speed data recorders

The purpose of this study is to design and make a prototype of a motorized vehicle speed data recorder by utilizing MMC (Multi Media Card) as a data recording media so that there will be factual evidence in the form of a motor vehicle track record as long as the vehicle is running. The research method uses the Research and Development (R & D) approach, with stages: hardware design and firmware creation, hardware testing, GUI application creation, GUI application testing, data retrieval testing, and data analysis. The entire system of this tool is controlled by the ATmega328 microcontroller, the RTC module is used to generate timer signals in real time and Infrared Sensors (IR Sensors) as wheel rotation detectors that are used as car speed sensors when driving. Data is recorded in the form of real time speed, accelerator (acceleration) and the distance stored in a Secure Digital Card (SD Card) or MMC (multimedia card) within the specified time interval. The results of hardware testing show that the design works through all the test scenarios performed. GUI applications and firmware are tested by blackbox testing, and show that the system is running smoothly. In addition, testing is also focused on speed data recording segmentation algorithms, with the result that the algorithm can mark the phase of each speed change with 100% accuracy. Product testing with data retrieval is done in 10 (ten) data by comparing the actual distance indicated by the speedometer with the system measurement value. The test results show that the system can accurately estimate activity parameters for each change in speed, with an accuracy rate of 98.91%. In addition, the standard deviation value of 0.02625 km / h indicates that this system is considered consistent in measurement.

Lifespan Analysis for Redundant Array of Independent Module Based Solid State Drives

Solid state drives (SSD) are usually built using a NAND flash memory array. An SSD controller manages datastreams stripped to multiple flash memory channels. The device could be regarded as a level-0 structure of redundant array of independent disk (RAID), the technical term for a disk array system. This typical SSD controller architecture is called an intrinsic RAID (iRAID). An iRAID-based SSD controller has to execute sophisticated wear-leveling algorithms and dynamically calculate the lifespan of each flash memory chip as well as run error correction coding. redundant array of independent module (RAIM) was proposed to simplify the SSD controller by applying a group of standardized memory modules instead of raw flash memory chips. One of the widely recognized memory modules is the embedded multi-media card (eMMC) module, which is a small component, typically with a ball grid array package, and is found in consumer applications. In the paper, we have described the methods needed to optimize wear-leveling in an array of eMMC modules and deduced a formula to evaluate and optimize the lifespan of an RAIM-based SSD. A silicon SSD controller was implemented to verify the analysis. The positive result revealed that the lifespan of the RAIM-based SSD could be improved in consumer-grade eMMC modules.

(Invited) Smartphones: Driving Technology to More than Moore 3-D Stacked Devices/Chips and More Moore FinFET 3-D Doping with High Mobility Channel Materials from 20/22nm Production to 5/7nm Exploratory Research

Today smartphone ICs are driving technology to More Moore 3-D device scaling and More Than Moore 3-D stacked devices with >1.24B smartphones sold in 2014 accounting for >27% of all ICs. The expected increase in smartphone application processor (AP) demand in 2015 (Samsung Exynos 7 for Galaxy S6 and Apple A9 for iPhone 6s/7) is driving the rapid ramp to 14/16nm technology node 3-D FinFET devices at foundries, 3-D memory devices such as 128Gb NAND Flash memory devices with 32-layers and 3-D stacked chips for form factor with >40% package area saving. Intel was first to production with 3-D bulk-FinFET devices at the 22nm technology node in 2011 and reported their SOC version for Chinese low-end smartphone market. Intel’s 2nd generation bulk-FinFET devices at 14nm node was introduced in Aug 2014 with their SOC version to follow. In Sept 2012 iPhone 5 was first to incorporate Sony’s 8M pixel 3-D stacked backside CMOS image sensor for rear-facing camera. In April 2015 Samsung Galaxy S6 incorporated 14nm technology node 3-D FinFET devices in the Exynos 7 Octa application processor and first 3-D ePOP (embedded package on package) which stacks AP+DRAM (3Gb LPDDR3)+Flash(128/64/32Gb)+eMMC (embedded multi-media card)+controller saving 40% area and use Sony’s 16M pixel 3-D stacked back-side CMOS image sensor for rear-facing camera and 5M pixel RWB image sensor for front-facing camera. Apple will introduce the iPhone 6s/7 in Sept 2015 with A9 application processor using 3-D FinFET devices with Samsung/Foundry 14nm technology node and TSMC 16FF+. 10nm technology node is expected in 2016 with higher mobility SiGe or Ge channel material then 7nm node in 2018 and gate-all-around nano-wire by 5nm node in 2020. To understand 3-D FinFET doping and high mobility channel material this paper will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET. 3-D 8o tapered FinFET S/D extension conformal doping was achieved with high tilt ion implantation at >45 degree. Highest retained dose and improved Fin sidewall line-edge-roughness (LER) on the atomic level can be realized with Hydrogen annealing surface passivation. High dopant activation is also achieved with advanced annealing SPE techniques of amorphous implanted junctions. Other 3-D dopant methods such as plasma implantation, knock-in dopant and deposition doping with diffusion including monolayer doping were not successful due to poor dopant activation and severe surface dopant loss. FinFET channel mobility enhancement at 22nm node used (511) plane taper Fin with 55% eSiGe S/D compressive strain for PMOS and amorphous implant SPE residual stacking fault defect S/D tensile stressor for NMOS. For 14nm node taller vertical Fins without the (511) taper and still 55% eSiGe S/D for PMOS and now eS/D for NMOS which is full of stacking fault defects. At the 10nm or 7nm node direct higher mobility Fin/channel material (SiGe, Ge or III-V) is expected to be introduced followed by exploratory research of gate-all-around nanowire for 5nm technology node. 25% SiGe to 100% Ge high mobility Fin-channel material on Si wafers will be realized by traditional gas/vapor phase epitaxial growth techniques by chemical vapor deposition (CVD) in blanket, selective growth including aspect ratio trapping, Ge condensation or an alternative liquid phase epitaxial (LPE) regrowth of an amorphous material layer by melt solidification. At 5nm node Si, SiGe or Ge nano-wire gate-all-around devices. Finally a discussion on dopant activation in high mobility Ge and SiGe material with low junction leakage.

Design of a High-Speed Serial Programming Interface Compatible with Bluetooth Embedded Systems

In this paper, we designed a serial programming interface (SPI) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. The 8-bit design of the SPI module is in charge of transferring the data and the instructions between the external devices and the coprocessors. We adopted the cyclic redundancy check method for the error correction. Also, we provided the interface for multimedia cards. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency.

Self-adaptive testing to determine sample size for flash memory solutions

Embedded system testing, especially long-term reliability testing, of flash memory solutions such as embedded multi-media card, secure digital card and solid-state drive involves strategic decision making related to test sample size to achieve high test coverage. The test sample size is the number of flash memory devices used in a test. Earlier, there were physical limitations on the testing period and the number of test devices that could be used. Hence, decisions regarding the sample size depended on the experience of human testers owing to the absence of well-defined standards. Moreover, a lack of understanding of the importance of the sample size resulted in field defects due to unexpected user scenarios. In worst cases, users finally detected these defects after several years. In this paper, we propose that a large number of potential field defects can be detected if an adequately large test sample size is used to target weak features during long-term reliability testing of flash memory solutions. In general, a larger test sample size yields better results. However, owing to the limited availability of physical resources, there is a limit on the test sample size that can be used. In this paper, we address this problem by proposing a self-adaptive reliability testing scheme to decide the sample size for effective long-term reliability testing.

Methodologies for Geotagging in FAT and ExFAT File Systems for Smart Phones

Methodologies for Geotagging in FAT and ExFAT File Systems for Smart Phones

ARM 내장 임베디드 시스템용 멀티미디어카드를 위한 SPI 인터페이스 설계

In this contribution, we design and implement an SPI hardware interface for the microprocessor to communicate with the MMC (Multi-Media Card) in an embedded system. Proposed architecture is compatible with the APB in AMBA bus architecture. Embedding OS in an embedded system means a big burden in terms of hardware and software ending up with performance decline. In this paper, we adopt the concept of SPI communication without using OS in the embedded system and implement in a form of FPGA chip. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency, which satisfied our target speed.

Evaluating mobile game prospects – perspective of a game publisher

The mobile gaming industry is undergoing a transformation from SMS based games to downloadable and multi media card (MMC) games. The game developers do not have the same financial resources for developing new services as a few years ago. Current development budgets are much lower and mobile game developers have to concentrate development activities to games which can generate revenue. In this paper, we examine the key decision making criteria for new game selection of a mobile game publisher and propose a tentative framework for the evaluation of new mobile product prospects in the game and entertainment industry. The preferences for the criteria are derived by applying the principles of the analytic hierarchy process method. We took the results of the chief executive officer's interview as the basis for the analysis on how the company chooses between competing new game initiatives, but we also interviewed the chief technology officer and a producer in the company to achieve a better understanding on why some criteria are more important than others. The results show that the case company emphasises expected profit and volume more than risk factors in decision making, although they also search for proven game concepts and rely on seasonal products with low risk of not having enough sales volume.

A NAND Flash Memory Controller for SD/MMC Flash Memory Card

In this paper, a novel NAND flash memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the flash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type flash memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the flash memory chip during the card production stage, the function for supporting various kinds of NAND flash memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) flash memory card controller chip was designed and implemented with UMC 0.18 mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances

A multi-functional, portable device with wireless transmission for home monitoring of children with a learning disability

A portable monitoring device was developed to assist in the management of children with a learning disability. The device was designed for continuous home monitoring of blood oxygen saturation, heart and respiration rates, and patient activity. It could be worn on a belt, while the patient continued normal activities. Data were stored on a multimedia card and automatically transmitted to a PC at prescribed intervals via a Bluetooth wireless link. From the PC the data were transmitted to a Web server, where the information was made available to the staff involved in the patient's care. Preliminary clinical studies were performed with nine patients (four with Down's syndrome, three with cerebral palsy and two with mental retardation). Patients and families considered the device easy to use and to wear. The monitoring device identified events of possible clinical interest. Although it was designed for monitoring children with a learning disability, it may also be useful with other groups, such as elderly people.

Development of a digital ambulatory recording system for electrodermal activity

A digital ambulatory recording system of electrodermal activity (D-EDA) that uses a multimedia card (MMC) as a compact data storage device was developed. Low power consumption allows 24 h simultaneous recording of skin conductance and/or skin potential. A reduction in weight and size of the system provided a more natural environment for ambulatory recording. Direct A/D conversion and storage to MMC remarkably simplified data processing. Improvement in time and amplitude resolution allowed observation during sleep of even fine fluctuations in skin potential and skin conductance, which had been buried in the rolling noise generated by our former analog cassette data recorder.