Multi-level Cache Research Articles

Research of spatial data cache index of electricity GIS

This paper studies the application of present situation of the GIS platform in the power industry, in view of the existing problems, putting forward a kind of spatial data model of the power facilities for power industry, and putting forward clustering indexing method based on semantic meaning, and accelerating the response speed of the multi-level cache mechanism. And finally the article is presented the possible problems, and the future outlook of the development of electric power GIS platform.

Multi-level Cache Prediction and Partitioning Mechanism in CMP

Multi-level Cache Prediction and Partitioning Mechanism in CMP

A Power-Aware Multi-Level Cache Organization Effective for Multi-Core Embedded Systems

Recent system design trends suggest multicore architecture for all computing platforms including distributed and embedded systems running real-time applications. Multilevel caches in a multicore system pose serious challenges as cache requires huge amount of energy to be operated and cache increases unpredictability due to its dynamic behavior. Bandwidth and synchronization problems are also critical design factors for distributed and embedded systems. In this work, we propose a based cache memory organization which is very effective for real-time distributed and embedded systems. Cache-level miss table holds information about the memory blocks that cause most level-1 cache (CL1) misses under normal execution. Proposed cache organization also includes private victim caches (VCs) to hold level-1 victim blocks and shared level-2 cache (CL2) to help synchronization. Proposed cache organization improves CL1 cache hits that decrease memory latency and total power consumption and improve predictability and bandwidth. We simulate an 4-core system with two-level caches using MPEG4, H.264/AVC, FFT, MI, and DFT workload. Experimental results show that the proposed miss table based cache organization helps reduce average memory latency and total power consumption by 31% and 38%, respectively, when compared with cache organization without miss table and victim caches.

A Multi-Level Cache Approach for Realtime Visualization of Massive 3D GIS Data

The real-time visualization of 3D GIS at a whole city scale always faces the challenge of dynamic data loading with high-efficiency. Based on the multi-tier distributed 3D GIS framework, this paper presents a multi-level cache approach for dynamic data loading. It aims to establish in 3D GIS spatial database engine (3DGIS-SDE) the unified management mechanism of caches on three levels, including: the client memory cache (CMC) oriented to sharing application, the client file cache (CFC) organized by index, as well as the application server memory cache (ASMC) of structural consistency. With the help of the proposed optimized cache replacement policy, multi-level cache consistency maintenance as well as multithread loading model designed in the paper, the engine is able to adaptively make full use of each-level caches according to their own application properties and achieve effective coordination between them. Finally, a practical 3D GIS database based on Oracle 11g is employed for test. The experimental results prove this approach could satisfy multi-user concurrent applications of 3D visual exploration.

Multi-dimension and Multi-level Associated Cache Partitioning Mechanism in CMP

Multi-dimension and Multi-level Associated Cache Partitioning Mechanism in CMP

Scalable parallel computing on clouds using Twister4Azure iterative MapReduce

Recent advances in data-intensive computing for science discovery are fueling a dramatic growth in the use of data-intensive iterative computations. The utility computing model introduced by cloud computing, combined with the rich set of cloud infrastructure and storage services, offers a very attractive environment in which scientists can perform data analytics. The challenges to large-scale distributed computations on cloud environments demand innovative computational frameworks that are specifically tailored for cloud characteristics to easily and effectively harness the power of clouds. Twister4Azure is a distributed decentralized iterative MapReduce runtime for Windows Azure Cloud. Twister4Azure extends the familiar, easy-to-use MapReduce programming model with iterative extensions, enabling a fault-tolerance execution of a wide array of data mining and data analysis applications on the Azure cloud. Twister4Azure utilizes the scalable, distributed and highly available Azure cloud services as the underlying building blocks, and employs a decentralized control architecture that avoids single point failures. Twister4Azure optimizes the iterative computations using a multi-level caching of data, a cache-aware decentralized task scheduling, hybrid tree-based data broadcasting and hybrid intermediate data communication. This paper presents the Twister4Azure iterative MapReduce runtime and a study of four real world data-intensive scientific applications implemented using Twister4Azure–two iterative applications, Multi-Dimensional Scaling and KMeans Clustering; and two pleasingly parallel applications, BLAST+ sequence searching and SmithWaterman sequence alignment. Performance measurements show comparable or a factor of 2 to 4 better results than the traditional MapReduce runtimes deployed on up to 256 instances and for jobs with tens of thousands of tasks. We also study and present solutions to several factors that affect the performance of iterative MapReduce applications on Windows Azure Cloud.

Research of Real-time Data Warehouse Storage Strategy Based on Multi-level Caches

Abstract Real-time data warehouse extend the application of traditional data warehouse. It can not only support tactical queries for enterprise but also provide much variable tactical decision support effectively. For these reasons, it is very meaningful to research on the structure of real-time data warehouses. This paper introduced the background of real-time data warehouse and proposed the strategy of real-time data warehouse which is based on double mirror replication mechanism. The strategy is composed of double steps. First we used double mirror replication mechanism to enable continuous loading data in the real-time data warehouse with minimum impact in query execution time. Second we proposed incorporating multi-level caches into the data warehouse structure which is based on real-time partition and gave the process of design and implementation with details. We differentiated between queries with various data freshness requirements, and used multi-level caches to satisfy these different requirements.

Performance innovation in the IBM zEnterprise 196 processor

The IBM zEnterprise® 196 achieves substantial performance gains over prior designs across the full spectrum of workloads being run on today's enterprise information technology systems, ranging from large data-intensive transaction processing workloads to central processing unit-intensive business applications. Each of these required innovations in the design of the hardware, software, and instruction-set architecture (ISA) with performance gains coming from several sources: the out-of-order microprocessor core design, the multilevel cache structure, new ISA facilities, and additional ISA extensions to enable efficient scaling of large multiprocessor operating system images. These enhancements were achieved through collaborative development among hardware, software, compiler, architecture, and performance analysis teams. This paper describes the performance contributions from these sources, with particular focus on the new architectural facilities.

Energy efficiency of on-demand video caching systems and user behavior

Energy-efficient video distribution systems have become an important tool to deal with the rapid growth in Internet video traffic and to maintain the environmental sustainability of the Internet. Due to the limitations in terms of energy-efficiency of the conventional server centric method for delivering video services to the end users, storing video contents closer to the end users could potentially achieve significant improvements in energy-efficiency. Because of dissimilarities in user behavior and limited cache sizes, caching systems should be designed according to the behavior of user communities. In this paper, several energy consumption models are presented to evaluate the energy savings of single-level caching and multi-level caching systems that support varying levels of similarity in user behavior. The results show that single level caching systems can achieve high energy savings for communities with high similarity in user behavior. In contrast, when user behavior is dissimilar, multi-level caching systems should be used to increase the energy efficiency.

Management of Multilevel, Multiclient Cache Hierarchies with Application Hints

Multilevel caching, common in many storage configurations, introduces new challenges to traditional cache management: data must be kept in the appropriate cache and replication avoided across the various cache levels. Additional challenges are introduced when the lower levels of the hierarchy are shared by multiple clients. Sharing can have both positive and negative effects. While data fetched by one client can be used by another client without incurring additional delays, clients competing for cache buffers can evict each other’s blocks and interfere with exclusive caching schemes. We present a global noncentralized, dynamic and informed management policy for multiple levels of cache, accessed by multiple clients. Our algorithm, MC 2 , combines local, per client management with a global, system-wide scheme, to emphasize the positive effects of sharing and reduce the negative ones. Our local management scheme, Karma , uses readily available information about the client’s future access profile to save the most valuable blocks, and to choose the best replacement policy for them. The global scheme uses the same information to divide the shared cache space between clients, and to manage this space. Exclusive caching is maintained for nonshared data and is disabled when sharing is identified. Previous studies have partially addressed these challenges through minor changes to the storage interface. We show that all these challenges can in fact be addressed by combining minor interface changes with smart allocation and replacement policies. We show the superiority of our approach through comparison to existing solutions, including LRU, ARC, MultiQ, LRU-SP, and Demote, as well as a lower bound on optimal I/O response times. Our simulation results demonstrate better cache performance than all other solutions and up to 87% better performance than LRU on representative workloads.

A Content-Based Multilevel Caching Policy for Super-Peer Networks

We propose a novel scheme, called Content-based Multilevel Caching Policy (CMCP) for super-peer networks that support hierarchical P2P architecture. Peers share information according the content between peers and between shared files to self-organise into clustered groups. Simulation experiments show that the CMCP policy achieves significant improvements in terms of access latency and global cache hit ratio.

Active Queue Management for Flow Fairness and Stable Queue Length

Two major goals of queue management are flow fairness and queue-length stability However, most prior works dealt with these goals independently. In this paper, we show that both goals can be effectively achieved at the same time. We propose a novel scheme that realizes flow fairness and queue-length stability. In the proposed scheme, high-bandwidth flows are identified via a multilevel caching technique. Then, we calculate the base drop probability for resolving congestion with a stable queue, and apply it to individual flows differently depending on their sending rates. Via extensive simulations, we show that the proposed scheme effectively realizes flow fairness between unresponsive and TCP flows, and among heterogeneous TCP flows, while maintaining a stable queue.

Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems

System optimization techniques based on efficient dynamic reconfiguration have been widely adopted in recent years. Cache reconfiguration is a promising optimization technique for reducing memory hierarchy energy consumption with little or no impact on overall system performance. While cache reconfiguration is successful in desktop-based and embedded systems, it is not directly applicable in real-time systems due to timing constraints. Existing scheduling-aware cache reconfiguration techniques consider only one-level cache. It is a major challenge to dynamically tune multi-level caches since the exploration space is prohibitively large. This paper efficiently integrates cache reconfiguration in real-time systems with a unified two-level cache hierarchy. We propose a set of exploration heuristics for our static analysis which effectively reduces the exploration time while keeps the generated profile results beneficial to be leveraged during runtime. Our experimental results have demonstrated 40-58% energy savings with minor impact on performance.

Can models of scientific software-hardware interactions be predictive?

Abstract Sparse scientific codes face grave performance challenges as memory bandwidth limitations grow on multi-core architectures. We investigate the memory behavior of a key sparse scientific kernel and study model-driven performance evaluation in this scope. We propose the Coupled Reuse-Cache Model (CRC Model), to enable multilevel cache performance analysis of parallel sparse codes. Our approach builds separate probabilistic application and hardware models, which are coupled to discover unprecedented insight into software-hardware interactions in the cache hierarchy. We evaluate our model's predictive performance with the pervasive sparse matrix-vector product kernel, using 1 to 16 cores and multiple cache configurations. For multi-core setups, average L1 and L2 prediction errors are within 3% and 6% respectively.

A Cache Architecture for Counting Bloom Filters: Theory and Application

Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, for example, utilizing multilevel memory hierarchies, special hardware architectures, and hardware threading. In this paper, we introduce a multilevel memory architecture for counting Bloom filters. Based on the probabilities of incrementing of the counters in the counting Bloom filter, a multi-level cache architecture called the cached counting Bloom filter (CCBF) is presented, where each cache level stores the items with the same counters. To test the CCBF architecture, we implement a software packet classifier that utilizes basic tuple space search using a 3-level CCBF. The results of mathematical analysis and implementation of the CCBF for packet classification show that the proposed cache architecture decreases the number of memory accesses when compared to a standard Bloom filter. Based on the mathematical analysis of CCBF, the number of accesses is decreased by at least 53%. The implementation results of the software packet classifier are at most 7.8% (3.5% in average) less than corresponding mathematical analysis results. This difference is due to some parameters in the packet classification application such as number of tuples, distribution of rules through the tuples, and utilized hashing functions.

An Evaluation of an OS-Based Coherence Scheme for Tiled CMPs

The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling to a larger number of cores. Tiled CMPs offer better scalability by integrating relatively simple cores with a lightweight point-to-point interconnect. However, such interconnects make snooping impractical and, thus, require alternative solutions to cache coherence. In this article, we investigate a novel, cost-effective mechanism to support shared-memory parallel applications that forgoes hardware maintained cache coherence. This mechanism is based on the key ideas that mapping of lines to physical caches is done at the page level with OS support and that hardware supports remote cache accesses. We extend our previous work by investigating in detail the impact of system design parameters and extending the system to support multi-level cache hierarchies. Results show that the choice of implementation of multi-level cache hierarchies can have a significant impact on performance.

Performance Enhancement of Soap Via Multi Level Caching

Due to complex infrastructure of web application response time for different service request by client requires significantly larger time. Simple Object Access Protocol (SOAP) is a recent and emerging technology in the field of web services, which aims at replacing traditional methods of remote communications. Basic aim of designing SOAP was to increase interoperability among broad range of programs and environment, SOAP allows applications from different languages, installed on different platforms to communicate with each other over the network. Web services demand security, high performance and extensibility. SOAP provides various benefits for interoperability but we need to pay price of performance degradation and security for that. This formulates SOAP a poor preference for high performance web services. In this paper we present a new approach by enabling multi-level caching at client side as well as server side. Reference describes implementation based on the Apache Java SOAP client, which gives radically enhanced performance.

WCET analysis of instruction cache hierarchies

With the advent of increasingly complex hardware in real-time embedded systems (processors with performance enhancing features such as pipelines, caches, multiple cores), most embedded processors use a hierarchy of caches. While much research has been devoted to the prediction of Worst-Case Execution Times (WCETs) in the presence of a single level of cache (instruction caches, data caches, impact of cache replacement policies), very little research has focused on WCET estimations in the presence of cache hierarchies. In this paper, we propose a safe static instruction cache analysis method for multi-level caches. Variations of the method are presented to model different cache hierarchy management policies between cache levels: non-inclusive, inclusive and exclusive cache hierarchies. The method supports multiple replacement policies. The proposed method is experimented on medium-size benchmarks and a larger application. We show that the method is tight in the case of non-inclusive caches hierarchies and exclusive caches hierarchies, provided that all cache levels use the Least Recently Used (LRU) replacement policy. We further evaluate the additional pessimism when inclusion is enforced or when a non-LRU replacement policy is used.

Cache-Based Aggregate Query Shipping: An Efficient Scheme of Distributed OLAP Query Processing

Our study introduces a novel distributed query plan refinement phase in an enhanced architecture of distributed query processing engine (DQPE). Query plan refinement generates potentially efficient distributed query plan by reusable aggregate query shipping (RAQS) approach. The approach improves response time at the cost of pre-processing time. If the overheads could not be compensated by query results reusage, RAQS is no more favorable. Therefore a global cost estimation model is employed to get proper operators: RR_Agg, R_Agg, or R_Scan. For the purpose of reusing results of queries with aggregate function in distributed query processing, a multi-level hybrid view caching (HVC) scheme is introduced. The scheme retains the advantages of partial match and aggregate query results caching. By our solution, evaluations with distributed. TPC-H queries show significant improvement on average response time.

Caches for Multimedia Workloads: Power and Energy Tradeoffs

One of the significant workloads in current generation desktop processors and mobile devices is multimedia processing. Large on-chip caches are common in modern processors, but large caches will result in increased power consumption and increased access delays. Regular data access patterns in streaming multimedia applications and video processing applications can provide high hit-rates, but due to issues associated with access time, power and energy, caches cannot be made very large. Characterizing and optimizing the memory system is conducive for designing power and performance efficient multimedia application processors. Performance tradeoffs for multimedia applications have been studied in the past, however, power and energy tradeoffs for caches for multimedia processing have not been adequately studied in the past. In this paper, we characterize multimedia applications for I-cache and D-cache power and energy using a multilevel cache hierarchy. Both dynamic and static power increase with increasing cache sizes, however, the increase in dynamic power is small. The increase in static power is significant, and becomes increasingly relevant for smaller feature sizes. There is significant static power dissipation, ~ 45%, in L1 & L2 caches at 70 nm technology sizes, emphasizing the fact that future multimedia systems must be designed by taking leakage power reduction techniques into account. The energy consumption of on-chip L2 caches is seen to be very sensitive to cache size variations. Sizes larger than 16 k for I-caches and 32 k for D-caches will not be efficient choices to maintain power and performance balance. Since multimedia applications spend significant amounts of time in integer operations, to improve the performance, we propose implementing low power full adders and hybrid multipliers in the data path, which results in 9% to 21% savings in the overall power consumption.