Multilayer Gate Research Articles

Improving Retention Properties of ALD-AlxOy Charge Trapping Layer for Non-Volatile Memory Application

In this work, the charge retention properties of the thermal ALD-Al2O3 trapping layer with metal-oxide-oxide-oxide-silicon (MOOOS) gate stack have been investigated for non-volatile memory application. The precursor gas concentrations were changed to engineer the band gap of the AlxOy trapping layer and the effect of AlxOy post-deposition annealing on charge retention properties was studied. The Al2O3 layer with trimethyl aluminum (TMA): H2O gas flow ratio of 1:1 and deposition pulse time of 1 s per each cycle showed the band gap of 4.49 eV , which is suitable for charge trapping layer. The memory retention properties of the ALD-Al2O3 MOOOS device was investigated by performing high-frequency capacitance-voltage measurement and compared to the device having a SiNx charge trapping layer. The 10 nm AlxOy trapping layer showed the improvement in charge retention properties after low-temperature post-deposition annealing in N2 ambient as compared to that of SiNx trapping layer with relatively large flat band voltage shift of 2.79 V. The multilayer Al2O3-MOOOS gate stack is suitable for the non-volatile memory application with good retention properties as compared to different oxides non-volatile memory devices.

Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack

The amorphous indium gallium zinc oxide thin-film transistors (TFTs) with a multilayer high-k gate stack are investigated in this research. In order to achieve a high quality gate insulator for plastic flexible display application, the multilayer high-k gate stacks (SiO2/TiO2/HfO2) are deposited by a low-temperature physical vapor deposition (PVD) process. On the other hands, an interfacial layer between the high-k stack and metal oxide channel is important for the device performance. The effects of interfacial layer material (SiO2 or Ga2O3) are also discussed in this report. The devices with SiO2 interfacial layer show a high on/off current ratio of ~7 × 107 for its low gate leakage current, a small sub-threshold swing of 0.093 V/decade and a high field-effect mobility of ∼37.8 cm2/Vs for its good interface condition and low interface defeats. This research shows that the interface engineering of multilayer PVD gate stacks is necessary for oxide TFT fabrication.

Electrical and ferroelectric properties of RF sputtered PZT/SBN on silicon for non-volatile memory applications

We report the integration of multilayer ferroelectric film deposited by RF magnetron sputtering and explore the electrical characteristics for its application as the gate of ferroelectric field effect transistor for non-volatile memories. PZT (Pb[Zr0.35Ti0.65]O3) and SBN (SrBi2Nb2O9) ferroelectric materials were selected for the stack fabrication due to their large polarization and fatigue free properties respectively. Electrical characterization has been carried out to obtain memory window, leakage current density, PUND and endurance characteristics. Fabricated multilayer ferroelectric film capacitor structure shows large memory window of 17.73 V and leakage current density of the order 10−6 A cm−2 for the voltage sweep of −30 to +30 V. This multilayer gate stack of PZT/SBN shows promising endurance property with no degradation in the remnant polarization for the read/write iteration cycles upto 108.

Surface Oxidation Doping to Enhance Photogenerated Carrier Separation Efficiency for Ultrahigh Gain Indium Selenide Photodetector

This work presents an ultrahigh gain InSe-based photodetector by using a novel approach called the surface oxidation doping (SOD) technique. The carrier concentration of multilayered two-dimensional (2D) InSe semiconductor surface has been modulated by controlling the formation of a surface oxide layer. The SOD through surface charge transfer at the interface of the oxide/2D InSe semiconductor heterostructure can lead to the creation of a vertical built-in potential and band bending as a result of the carrier concentration distribution gradient. The internal electric field caused by the formation of a carrier concentration gradient in InSe layers can facilitate charge separation of photogenerated electron–hole pairs under light illumination. Consequently, the record high photoresponsivities of InSe-based photodetector with ∼5 × 106 A/W at the excitation wavelength of 365 nm and 5 × 105 A/W at the wavelength of 530 nm can be obtained, outperforming the majority of photodetectors based on other 2D materials, such as graphene, MoS2, and even highly sensitive multilayer GaTe and In2Se3 flakes. The approach based on SOD induced efficient photogenerated charge separation can be also applied to other 2D layered semiconductors.

Improved interfacial and electrical properties of Ge MOS capacitor with ZrON/TaON multilayer composite gate dielectric by using fluorinated Si passivation layer

A Ge metal-oxide-semiconductor capacitor with a composite gate dielectric composed of a ZrON/TaON multilayer and a Si passivation layer treated with fluorine plasma is fabricated. Its interfacial and electrical properties are compared with those of its counterparts without the Si passivation layer or the fluorine-plasma treatment. Experimental results show that the device with the fluorinated Si passivation layer exhibits excellent interfacial and electrical performances: low interface-state density (2.0 × 1011 cm2 eV−1 at midgap), small flatband voltage (0.17 V), low gate leakage current (2.04 × 10−6 A/cm2 at Vg = Vfb + 1 V), and high equivalent dielectric constant (22.6). The involved mechanism lies in the fact that the TaSiON interlayer formed by mixing of TaON and Si passivation layers can effectively suppress the growth of unstable Ge oxides to reduce the defective states at/near the TaSiON/Ge interface. Moreover, the fluorine-plasma treatment can passivate the oxygen vacancies and conduce to the blocking of elemental inter-diffusions, thus largely improving the interfacial quality to achieve excellent electrical properties for the device.

Low-voltage-drive and high output current InGaZnO thin-film transistors with novel SiO2/HfO2/SiO2 structure

ABSTRACTLow-voltage-drive InGaZnO (IGZO) thin-film transistor (TFT) with SiO2/HfO2/SiO2 (SHS) multilayer gate insulator is deposited by radio frequency sputtering at room temperature. The fabricated device performed a threshold voltage of 1.4 V, a field effect mobility of 8.6 cm2/VS, an Ion/Ioff ratio of 2.9 × 105, and a sub-threshold voltage swing of 0.67 V/dec. The drain current was 260 µA with both gate and drain voltage of 10 V. SHS multilayer has a high capacitance to increase the high mobility and decrease the drive voltage for TFT.

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm2), insulating property (leakage current densities <10-7 A/cm2), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

Low-Resistive High-Work-Function Gate Electrode for Transparent a-IGZO TFTs

Highly transparent and low-resistive multilayered gate electrodes, MoO3/indium–tin oxide (ITO)/Ag/ZnS (MIAZ) playing as the high-work-function layer, the nonreactive interface layer, the lateral conduction layer, and the index-matching layer, respectively, have been investigated for the application to the transparent oxide thin-film transistors (TFTs). The transmittance of the optimized MIAZ electrode is 92.46% and the sheet resistance is $7.77~\Omega / \Box $ . The top gate InGaZnO TFT with this gate electrode shows the mobility of 11.57 cm2/( $\text {V}\cdot ~\text {s}$ ) and positive $V_{\text {th}}$ of 0.210 V compared with that with single ITO gate electrode of which $V_{\text {th}}$ is −0.086 V.

In-Plane Optical Anisotropy of Layered Gallium Telluride.

Layered gallium telluride (GaTe) has attracted much attention recently, due to its extremely high photoresponsivity, short response time, and promising thermoelectric performance. Different from most commonly studied two-dimensional (2D) materials, GaTe has in-plane anisotropy and a low symmetry with the C2h(3) space group. Investigating the in-plane optical anisotropy, including the electron-photon and electron-phonon interactions of GaTe is essential in realizing its applications in optoelectronics and thermoelectrics. In this work, the anisotropic light-matter interactions in the low-symmetry material GaTe are studied using anisotropic optical extinction and Raman spectroscopies as probes. Our polarized optical extinction spectroscopy reveals the weak anisotropy in optical extinction spectra for visible light of multilayer GaTe. Polarized Raman spectroscopy proves to be sensitive to the crystalline orientation of GaTe, and shows the intricate dependences of Raman anisotropy on flake thickness, photon and phonon energies. Such intricate dependences can be explained by theoretical analyses employing first-principles calculations and group theory. These studies are a crucial step toward the applications of GaTe especially in optoelectronics and thermoelectrics, and provide a general methodology for the study of the anisotropy of light-matter interactions in 2D layered materials with in-plane anisotropy.

Oxygen vacancy defect engineering using atomic layer deposited HfAlOx in multi-layered gate stack

This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlOx with extremely low Al (&amp;lt;3% Al/(Al + Hf)) incorporation in the Hf based high-k dielectrics. The defect activation energy estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V+/V2+, are the primary source of defects in these dielectrics. When Al is added in HfO2, the V+ type defects with a defect activation energy of Ea ∼ 0.2 eV modify to V2+ type to Ea ∼ 0.1 eV with reference to the Si conduction band. When devices were stressed in the gate injection mode for 1000 s, more V+ type defects are generated and Ea reverts back to ∼0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO2 contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.

Analysis of the Retention Characteristic in Three dimensional Junction-less Charge Trapping Memory

To meet the storage requirement of big data, charge trap concept-based three dimensional charge trapping memory (3D-CTM) becomes the main trend of flash technology development. With the multi-layer gate stacking, the equivalent technology node can be scaled down to 10nm without the serious reliability problems from cell-to-cell coupling and SILC-inducing charge loss in conventional flash memory. Specially, the cylindrical junction-less structures such as BICS and TCAT have attracted extensive attention from academia and industry due to their merits of relatively simple procedure and full compatibility with the CMOS process. Moreover, the vertical channel and the ring shape gate stack of memory cell make the 3D memory show superior program/erase performance comparing with the conventional planar flash. However, the shape of charge trap layer is also an important factor affecting the device reliability. The uneven electrical field distribution in tunnel and block layer and the non-separated charge trapping layer of the cylindrical junction-less geometry bring some problems about charge lose in program or erase state. The retention is a critical issue for high density and reliability of 3D integration. In this work, the retention characteristic of 3D cylindrical junction-less charge trapping memory has been investigated. The trapped charge and electron concentration distribution after programming/erasing 10 years have been simulated by sentaurus 3D device simulator. The lateral and vertical charge migrations also have been discussed during the charge losing process. Furthermore, the dominant loss path at the vertical direction has been considered. Figure 1(a) shows schematic birds-eye view of typical 3D-CTM array structure. In order to study the retention properties of 3D vertical memory cell, a string with one cell and two select transistors is used in simulation, as shown in Figure 1(b). Sentaurus 3D device simulator was used for the simulation. The barrier tunneling model contains Fowler–Nordheim tunneling and direct tunneling components, which depends on the energy barrier and band bending calculated self-consistently. From the simulate result of trapped charge at the initial programmed state (initial state) and 10 years after programming state under 85°C condition (10 years state), it can be found that the lateral charge migration happened at 10 years state with respect to the initial state. And the lateral extention distance will be longer if the vertical charge loss is unconsidered. Also,the simulate result shows there is a competition between vertical and lateral charge loss and the vertical charge loss weaken the lateral charge migration during the retention time. Then, the dominant loss path at the vertical direction has been studied. We find that charge loss toward block layer is more serious than tunnel layer. The retention at erase state is also be investigated.Comparing with electron loss, the trapped hole nearly doesn’t loss even after 10 years. This simulation result coincides with the experiment data from Toshiba and Samsung. It’s can be attributed to the larger effective mass and deeper trap energy level of the hole, making it harder to occur tunneling and migration. In this article, retention of 3D cylindrical junction-less CTM has been studied. For the programmed device, lateral charge migration is obvious after 10 years. Vertical charge loss also occurs and lose more seriously toward block layer than tunnel layer. For the erased device, there is nearly no trapped hole loss even after 10 years. This work was supported by the National Natural Science Foundation of China (Grant No. 61474137, No. 61306107, No. 61404168, No. 61404160), China Postdoctoral Science Foundation funded project (No.2014M550866), and the Scientific Research Foundation of CUIT (KYTZ201318, J201404). Figure 1

Charge characteristics of MOS structure with thermal SiO2 films doped with phosphorus under high-field electron injection

The processes of changing the charge state of metal–oxide–semiconductor (MOS) structures that contain a multilayer gate dielectric on the basis of a thermal SiO2 film doped with phosphorus under the influence of high-field electron injection are investigated. It is determined that a negative charge accumulating in a thin phosphosilicate glass (PSG) film of MOS structures containing a SiO2–PSG two-layer gate dielectric under high-field tunneling injection of electrons can be used for the correction of the threshold voltage, for the enhancement of the charge stability, and for an increase in the breakdown voltage of devices with MOS structure. It is shown that the density of electron traps increases with an increase in the thickness of the PSG film containing them, while their capture cross section remains unchanged. The method for the modification of the electrophysical characteristics of MOS structures by the high-field tunneling injection of electrons into a dielectric under a controlled current load is proposed. The method allows one to control changes in the parameters of MOS structures directly in the process of their modification. It is established that a MOS structure with a high thermal field stability can be obtained by its annealing at 200°C after the modification of its charge state by the electron injection.

Modification of thin oxide films of MOS structure by high-field injection and irradiation

We have investigated processes of modification and changing of the charge state of MOS structures having a multilayer gate dielectric based on a thermal SiO2 film doped with phosphorus under conditions of different modes of high-field electron injection and an electron irradiation. We have determined that negative charge, accumulating in the phosphosilicate glass (PSG) ultra thin film of the MOS structures having the two-layer gate dielectric SiO2-PSG under conditions of both high-field tunneling injection of electrons and electron beam, could be used for a modification of devices having the same structure (e.g. correction of threshold voltage, increase of charge stability and breakdown voltage of MOS structure). We have shown that when thickness of PSG film increased, a raising of the electron traps density occurred, but the value of the cross-section of electron traps was the same. It was established that in order to obtain MOS structures with high thermal stability, one has to anneal them at 200° C after performing irradiation treatment.

Adder design using a 5-input majority gate in a novel “multilayer gate design paradigm” for quantum dot cellular automata circuits

This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input–output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact.

Interfacial and electrical properties of InGaAs metal-oxide-semiconductor capacitor with TiON/TaON multilayer composite gate dielectric

InGaAs metal-oxide-semiconductor (MOS) capacitors with composite gate dielectric consisting of Ti-based oxynitride (TiON)/Ta-based oxynitride (TaON) multilayer are fabricated by RF sputtering. The interfacial and electrical properties of the TiON/TaON/InGaAs and TaON/TiON/InGaAs MOS structures are investigated and compared. Experimental results show that the former exhibits lower interface-state density (1.0 × 1012 cm−2 eV−1 at midgap), smaller gate leakage current (9.5 × 10−5 A/cm2 at a gate voltage of 2 V), larger equivalent dielectric constant (19.8), and higher reliability under electrical stress than the latter. The involved mechanism lies in the fact that the ultrathin TaON interlayer deposited on the sulfur-passivated InGaAs surface can effectively reduce the defective states and thus unpin the Femi level at the TaON/InGaAs interface, improving the electrical properties of the device.

Role of Ga Vacancy on a Multilayer GaTe Phototransistor

We report a high-performance field-effect transistor (FET) and phototransistor based on back-gated multilayer GaTe nanosheets. Through both electrical transport measurements at variable temperatures and first-principles calculations, we find Ga ion vacancy is the critical factor that causes high off-state current, low on/off ratio, and large hysteresis of GaTe FET at room temperature. By suppressing thermally activated Ga vacancy defects at liquid nitrogen temperature, a GaTe nanosheet FET with on/off ratio of ∼10(5), off-state current of ∼10(-12) A, and negligible gate hysteresis is successfully demonstrated. Furthermore, a GaTe phototransistor with high photogain above 2000 and high responsivity over 800 AW(-1) is achieved, as well. Our findings are of scientific importance to understand the physical nature of intrinsic GaTe transistor performance degradation and also technical significance to unlock the hurdle for practical applications of GaTe transistors in the future.

Hybrid Gate Dielectric Materials for Unconventional Electronic Circuitry

Recent advances in semiconductor performance made possible by organic π-electron molecules, carbon-based nanomaterials, and metal oxides have been a central scientific and technological research focus over the past decade in the quest for flexible and transparent electronic products. However, advances in semiconductor materials require corresponding advances in compatible gate dielectric materials, which must exhibit excellent electrical properties such as large capacitance, high breakdown strength, low leakage current density, and mechanical flexibility on arbitrary substrates. Historically, conventional silicon dioxide (SiO2) has dominated electronics as the preferred gate dielectric material in complementary metal oxide semiconductor (CMOS) integrated transistor circuitry. However, it does not satisfy many of the performance requirements for the aforementioned semiconductors due to its relatively low dielectric constant and intransigent processability. High-k inorganics such as hafnium dioxide (HfO2) or zirconium dioxide (ZrO2) offer some increases in performance, but scientists have great difficulty depositing these materials as smooth films at temperatures compatible with flexible plastic substrates. While various organic polymers are accessible via chemical synthesis and readily form films from solution, they typically exhibit low capacitances, and the corresponding transistors operate at unacceptably high voltages. More recently, researchers have combined the favorable properties of high-k metal oxides and π-electron organics to form processable, structurally well-defined, and robust self-assembled multilayer nanodielectrics, which enable high-performance transistors with a wide variety of unconventional semiconductors. In this Account, we review recent advances in organic-inorganic hybrid gate dielectrics, fabricated by multilayer self-assembly, and their remarkable synergy with unconventional semiconductors. We first discuss the principals and functional importance of gate dielectric materials in thin-film transistor (TFT) operation. Next, we describe the design, fabrication, properties, and applications of solution-deposited multilayer organic-inorganic hybrid gate dielectrics, using self-assembly techniques, which provide bonding between the organic and inorganic layers. Finally, we discuss approaches for preparing analogous hybrid multilayers by vapor-phase growth and discuss the properties of these materials.

High-Sensitivity Photodetectors Based on Multilayer GaTe Flakes

Optoelectronic devices based on layered materials such as graphene have resulted in significant interest due to their unique properties and potential technological applications. The electric and optoelectronic properties of nano GaTe flakes as layered materials are described in this article. The transistor fabricated from multilayer GaTe shows a p-type action with a hole mobility of about 0.2 cm(2) V(-1) s(-1). The gate transistor exhibits a high photoresponsivity of 10(4) A/W, which is greatly better than that of graphene, MoS2, and other layered compounds. Meanwhile, the response speed of 6 ms is also very fast. Both the high photoresponsivity and the fast response time described in the present study strongly suggest that multilayer GaTe is a promising candidate for future optoelectronic and photosensitive device applications.

The Effect of Multiple Interfaces on the Electrical Properties of MgO/Al2O3 Multilayer Gate Stacks on Si Grown by MBE

ABSTRACTHigh-κ and metal gate structures have been used to improve the performance of CMOS devices. By changing the materials and structures of the gate dielectric stacks, the flatband voltage (VFB) and the leakage can be changed. We used bilayers and multilayer structures composed of MgO and Al2O3 to verify their influence on the overall electrical properties. Films with an MgO bottom layer generally are found with less flatband voltage shift and lower leakage than with an Al2O3 bottom layer. Also, the frequency dispersion and the interface state density (Dit) are higher for those with MgO bottom layers. MgO films thicker than 0.5 nm effectively shields the positive charges present in the Al2O3.

Single hole transport in a silicon metal-oxide-semiconductor quantum dot

We describe a planar silicon metal-oxide-semiconductor (MOS) based single hole transistor, which is compatible with conventional Si complementary MOS fabrication. A multi-layer gate design gives independent control of the carrier density in the dot and reservoirs. Clear Coulomb blockade oscillations are observed, and source-drain biasing measurements show that it is possible to deplete the dot down to the few hole regime, with excited states clearly visible. The architecture is sufficiently versatile that a second hole dot could be induced adjacent to the first one.