Multichip Module Design Research Articles

Investigation of design and performance of multichip modules including electromagnetic compatibility

Investigation of design and performance of multichip modules including electromagnetic compatibility

Economics modeling of multichip modules testing strategies

To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply design for test (DFT) and built-in self test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this paper we explore the tradeoffs between various test and rework strategies for multichip module designs. Some of these strategies incorporate various DFT options at both the MCM and IC levels. We will analyze the impact of various cost, yield, and test effectiveness parameters on the final cost and quality of multichip modules. Experimental tradeoff analysis data generated for some leading-edge multichip designs will also be presented. The results clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable and results in cost reduction as well as quality improvement. The results also indicates that the MCM cost could vary by about 10–20% depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, requires an evaluation of the economics of the various solutions and the payback. That process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environment(s). Hence, one has to be careful about generalizing the lessons learned from specific cases, since it could lead to non optimal solutions. A careful economic modeling of the various design, test and manufacturing parameters is clearly necessary for producing cost-effective high-quality products.

The Effects of Material Properties on Heat Dissipation in High Power Electronics

The role of the substrate in determining heat dissipation in high power electronics is calculated, subject to convective cooling in the small Biot number regime. Analytical models that exploit the large aspect ratio of the substrate to justify approximations are shown to predict the behavior with good accuracy over a wide range of configurations. The solutions distinguish heat spreading effects’ that enable high chip-level power densities from insulation effects that arise at large chip densities. In the former, the attributes of high thermal conductivity are apparent, especially when the substrate dimensions are optimized. Additional benefits that derive from a thin layer of a high thermal conductivity material (such as diamond) are demonstrated. In the insulating region, which arises at high overall power densities, the substrate thermal conductivity has essentially no effect on the heat dissipation. Similarly, for compact multichip module designs, with chips placed on both sides of the substrate, heat dissipation is insensitive to the choice of the substrate material, unless advanced cooling mechanisms are used to remove heat around the module perimeter.

Modeling and simulation of asymmetric stripline for multichip module applications

Modeling and simulation of interconnect materials has become critical to the success of high performance ULSI, packaging, and multilayer schemes for multichip modules. Computer simulation of the characteristic impedance Z (Ohms), capacitance C (pF), working frequency f (MHz) of Al asymmetric stripline filled with anodic Al oxide with dielectric constants 4 and 6.6 for multilayer schemes in a hybrid multichip module were conducted. A RLC-model of the frequency of Al transmission lines was successfully used. Using conformal mapping, the functional dependence of the characteristic impedance and working frequency on the capacitance of the Al stripline filled by anodic Al oxide can be determined. The results are valid for high frequencies. To evaluate this model and characterize its performance with high speed electrical multichip module design, a test cell using a multilayer interconnect structure Al/anodic al oxide on an Al substrate was developed.

Fast simulation of lossy transmission lines by themodified method of characteristics

A set of recursive formulations based on the method of characteristics (MC) are derived to simulate lossy transmission lines in VLSI and multichip modules (MCMs) design.

Design and evaluation of an epoxy three-dimensional multichip module : Jon M. Sternet al. IEEE Transactions on Components, Packaging and Manufacturing Technology—Part B, 19 (1), 188 (1996)

Design and evaluation of an epoxy three-dimensional multichip module : Jon M. Sternet al. IEEE Transactions on Components, Packaging and Manufacturing Technology—Part B, 19 (1), 188 (1996)

Design and evaluation of an epoxy three-dimensional multichip module

A low-cost, three-dimensional multichip module (MCM) technology provides greatly improved system density and reduced mass over planar packaging technologies. The technology offers a high degree of testability that negates the need for known good die (KGD) procurement. Testing is achieved with very low cost overheads and with no increase in the volume of the module. The technology allows complete, heterogeneous systems to be packaged and interconnected in a single, ultra-dense module. The electrical characteristics of the technology are comparable to standard chip packages. However, the parasitics due to package-to-package interconnects are eliminated. This removes the dominant cause of parasitics, dramatically improving the electrical characteristics. A programmable integrated camera and image processing system has been developed which incorporates a grayscale camera, analog-to-digital conversion, four programmable processors and memory. Utilizing the three-dimensional multichip module technology, the system, which consists of nine chips and 36 discrete components, has an overall volume of 4.77 ml. This is approximately six times more dense than an advanced PCB implementation. The system forms the first stage in the design and manufacture of a portable video communications device. For such applications, low system volume and mass are key attributes. The system demonstrates the potential of the packaging technique for the integration of complete mixed signal systems incorporating sensors and processing. Further developments to the technology will provide increased module density, improved routing capacity, and electrical performance.

Measurements of the novel thermal conduction of a porphoritic heat sink paste

The thermal conduction of a solid/liquid porphoritic heat sink material having a specific geometry is reported. This new material consists of submicron-size diamond particles dispersed in n-decane at high packing fractions. Although each constituent has a measured decrease in thermal conduction with increasing temperature, the thermal conduction of the mixture shows a unique and significant increase with increasing temperature. This novel increase in thermal conduction has particular relevance to the thermal management of die that have uneven heat dissipation requirements. The material also has particular application in the construction and thermal design of multichip modules (MCM's).

A NEW LAYOUT DESIGN SYSTEM FOR MULTICHIP MODULES

A new layout design system for multichip modules (MCMs) consisting of three components is described. It includes a k-way partitioning approach, an algorithm for pin assignment, and a placement package. For partitioning, we propose an analytical technique combined with a problem-specific multi-way ratio cut method. This method considers fixed module-level pad positions and assigns the cells to regularly arranged chips on the MCM substrate. In the subsequent pin assignment step the chip-level pads resulting from cut nets are positioned on the chip borders. Pin assignment is performed by an efficient algorithm, which profits from the cell coordinates generated by the analytical technique. Global and final placement for each chip is computed by the state-of-the-art placement tools GORDIANL and DOMINO. For the first time, results for MCM layout designs of benchmark circuits with up to 100,000 cells are presented. They show a small number of required chip-level pads, which is the most restricted resource in MCM design, and short total wire lengths.

MCM-L technology: a systems cost analysis for a high volume automotive electronics application

Cost concerns related to the development and manufacturability of multichip modules have limited the widespread use of MCMs for high-volume low-cost applications. This paper discusses the many elements necessary to evaluate fully the financial effects of MCM programs. In particular, this paper evaluates a development program for a multichip module design targeted for a high volume automotive electronics control module. Often the added material costs associated with multichip modules prohibit MCM usage for low cost applications. This paper deals with the overall costs and savings associated with MCM development. While each decision to incorporate MCMs within a product design must be made individually, the analysis detailed below provides considerable insight into the overall systems cost involved with MCMs. >

Microwave photonic multichip modules packaged on a glass-silicon substrate

A hybrid microwave photonic integration technology known as optoelectronic glass microwave integrated circuit (opto-GMIC) has been developed. It is a multichip module approach that uses a glass substrate on a silicon carrier to interconnect both discrete and monolithic microwave and optoelectronic devices. The glass substrate can support both lumped and distributed elements, thus reducing the number of parts in assembly. In addition, a wide variety of microwave photonic multichip module designs can be produced from the same production line. This has been demonstrated by the fabrication of prototype fiber-optic repeaters, transmitters, and receivers designed for synchronous optical network applications at a bit rate of 622.08 Mb/s and a wavelength of 1.3 /spl mu/m. >

A knowledge-based simulation environment for the early design of multichip modules

Abstract A knowledge-based simulation environment is developed to facilitate the early design of Multichip Modules (MCMs). Electrical system performance measures such as module clock frequency, etc. are predicted and analyzed for different interconnect and packaging technologies. Performance-limiting factors such as power dissipation, coupled noise, and simultaneous switching noise are also included in this work. CMOS based MCMs for workstation applications are used to demonstrate the feasibility of the system in development.

Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for multichip module interconnects

Decreasing the system volume for optoelectronic (OE) planar systems is achieved by advancing computer-aided design of OE multichip modules (MCM's). It is shown that in order to minimize the volume in an OE MCM, it is necessary to minimize the maximum interconnect distance. To achieve this, we have developed placement algorithms based on the constraints of a given irregular interconnect pattern. Results are given for a twin-butterfly network for two general physical models: a transmissive MCM and a reflective MCM. We then show three different types of hologram design that can be used to implement the interconnect array. These elements are for reconstruction in the near field and are fabricated by direct-write electron-beam lithography. Both simulated and experimental reconstructions are demonstrated.

A structured testability approach for multi-chip modules based on BIST and boundary-scan

Products motivated by performance-driven and/or density-driven goals have started to use multi-chip module (MCM) technology, even though this technology still has several challenging problems, that need to be resolved before it becomes a widely adopted solution. Among the most challenging problems are achieving acceptable MCM assembly yields and meeting product quality requirements. Both of these problems can be significantly reduced by adopting adequate testing. Approaches which guarantee the quality of incoming bare (unpackaged) dies prior to module assembly, ensure the structural integrity and performance of the assembled MCMs, and help isolating defective parts prior to the repair process. This paper presents a structured testability approach that helps resolve the above problems. The approach can be adopted during MCM design and utilized during the manufacturing process. It is based on adopting Built-In-Self-Test (BIST) and boundary-scan and is in general independent of silicon, substrate or attachment technologies, hence it can be considered a generic solution.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The signal transmission characteristics of embedded microstrip transmission lines over a meshed ground plane in copper/polyimide multichip module

The high-speed digital signal transmission characteristics of a microstrip transmission line in a meshed ground plane environment were studied. It is found that ground plane geometry significantly affects the degree of crosstalk noise between two adjacent signal lines and the characteristic impedance of a transmission line. A signal conductor over a meshed ground plane exhibits less degradation in rise time and voltage amplitude, compared to a line over a solid ground plane, due to the lower line capacitance and lower conductor loss. However, the longer current path in the case of a meshed ground plane increases the overall line inductance which results in a slower propagation velocity. A ground plane with optimum geometric configuration, in mesh pitch and aperture, is chosen that meets system level performance requirements while still being compatible with processing constraints. The impact of transmission lines with meshed ground plane on multichip module design for digital applications is also discussed. >

Thermal design for high-speed high-density multichip module

The boundary conditions of models for finite element analysis of the thermal design of high-speed high-density multichip modules are examined, principally the thermal via and heat sink, and a model that improves the accuracy of heat transfer analysis simulation is investigated. It is found that in evaluating the effectiveness of thermal vias in heat loss, simulation can be made to yield results close to observed values by considering the substrate a compound material with a uniform thermal conductivity coefficient determined by the ratio of thermal via cross section area to substrate area. A thermal via area ratio of 10% is satisfactory both from the standpoint of manufacturing and for effectiveness in decreasing thermal resistance. Also, in the present model the heat transfer coefficient of the heat sink can be determined by using air speeds and comparison with observed results. It is concluded that the model is capable of highly accurate simulation of thermal via and heat sink conditions and can be effective in the thermal design of high-speed, high-density multichip modules.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Development of a multichip module DSP

The signal processor packaging design (SPPD) general-purpose digital signal processor (DSP) architecture is discussed. SPPD is a highly modular processor architecture that is based on off-the-shelf components and that supports a multichip module (MCM) design implementation that delivers 400 million floating-point operations per second in a 75-g package. The interconnect-substrate design, MCM package assembly, MCM testing, and tradeoffs in size, weight, and cost of the SPPD packaging are described. >

Multichip module using multilayer YBa2Cu3O7−δ interconnects

We report the first use of high temperature superconductors for multilayer interconnection of bare semiconductor die to form multichip modules. Ten die with a total of 160 pads were interconnected on a 3.4 cm2 substrate. The interconnections were a combination of YBa2Cu3O7−δ lines and vias on two wiring levels separated by an epitaxial insulating layer. Connection between the two YBa2Cu3O7−δ wiring layers was accomplished by the use of superconducting vias through the insulator. Two similar multilayer multichip module designs, with 30- and 10-μm-wide YBa2Cu3Oδ−7 lines, were constructed.

A feasibility study for the fabrication of planar silicon multichip modules using electron beam lithography for precise location and interconnection of chips : Andy Hopperet al. IEEE Trans. Compon. Hybrids mfg Technol.15, 97 (1992)

The study attempts to seek the optimal thermal design of planar multichip module (MCMs) under natural convection through optimal chip placement design. To attain the goal, a sequential metamodeling-based optimization approach is introduced. This approach incorporates a response surface methodology (RSM)-based design of experiment (DOE), three-dimensional (3D) thermal finite element analysis (FEA) and an updating scheme. Essentially, the RSM is used to construct, via quadratic polynomial approximation, the global RS of the chip junction temperature in terms of design variables. For speeding up the DOE and the solution of the optimization, several dynamic experimental design strategies using move limits and different proposed sampling techniques are introduced. The feasibility of the strategies is demonstrated, and their solution accuracy and efficiency are also compared with each other. By the explicit RS-based performance function together with geometry constraints, a constrained thermal optimization subproblem is formed. The optimum of the subspace optimization is sought, which is considered as the nominal starting point of next iteration. The iterative process continues with a new defined design subspace and factorial design plan until convergence is attained. The applicability of the proposed design optimization technique is demonstrated through several design case studies involving various planar MCMs.

Design of multichip modules

The process and pitfalls of multichip module (MCM) design, including the constraints, tradeoffs, figures of merit, and considerations which make MCM design a unique interdisciplinary challenge are discussed. The MCM must provide the proper operating environment for the chips it contains. It must also fit the constraints of the system in which it is contained. It must be manufacturable, testable, and repairable. The many aspects of MCM design are described, starting with system benefits, then system and MCM partitioning, chip environment, system constraints, and infrastructure/manufacturing issues.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>