Multichip Module Design Research Articles

Packaging of GaAs signal processors on multichip modules

The extensions that must be made to the deposited multichip module (MCM-D) fabrication technology and to the design and layout of these structures in order to accommodate high clock rate ECL and GaAs digital integrated circuits are discussed. Techniques for attachment of the high clock rate chips to the MCM-Ds are discussed, including wire bond, tape automated bond (TAB), flip-chip solder attachment, and flip adhesives. The tradeoffs between these different approaches are noted. Electrical issues are addressed. The problem of launching fast rise time, wide bandwidth signals onto and retrieving such signals from the MCM-Ds are noted. The thermal problems associated with the packing of 10-50 high power dissipation chips onto such small structures are discussed, along with methods of removing such high levels of heat by changes in materials incorporated into the stacked structures. Several MCM-D design and fabrication projects under way which attempt to address and solve some of the problems are described, along with some of the initial results of these studies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

DESIGN AUTOMATION FOR MULTICHIP MODULE — ISSUES AND STATUS

In this paper we will review the current state of commercial electronic design automation (EDA) tools for the design of multichip modules. MCM can be classified in terms of its substrate technology. The choice of substrate technology has important implications for the selection of design automation tools. A PCB EDA system seems more appropriate for MCMs with stacked via substrate which closely resembles the through-hole printed circuit board (PCB). A chip layout system may be more appropriate for MCMs with low-cost thin-film silicon substrate which typically uses staircase vias. The cofired ceramic substrate MCM which evolved from the hybrid integrated circuit technology may use the specialized hybrid EDA software packages available for the designing of hybrid integrated circuits. Historically, printed circuit board and integrated circuit design automation software evolved separately. There exists a boundary between the printed circuit board and integrated circuit design automation tools in the physical design hierarchy. This boundary can be an important limitation for the repartitioning of the physical design hierarchy within the MCM. We shall discuss in detail the impact of MCM on various aspects of EDA. In the area of physical design, we must face the traditional placement and routing problem for any high speed design. Problems such as system clock skew and tight timing requirements must be considered. As one push clock frequency higher, one also must consider discontinuities due to vias and bends besides the classical transmission line effect due to long wires. Other traditional physical design problems such as ground and power plane generation, physical design verification and mask tooling must be revisited in the context of various MCM substrate technologies. The thermal aspects of MCM design are strongly influenced by the placement of chips on the MCM substrate. Thermal design is especially important for high density MCMs using the flip-chip mounting technology. Here, the heat must be dissipated through the back of the substrate via thermal pillars or bumps. We still need to deal with the traditional coupled transmission line problems. Due to the small cross section, high performance MCM substrate interconnects are resistive and the transmission lines they form are lossy. Noise is another main problem for MCM design. For high speed MCM with many CMOS buffers, the ground bouncing noise resulting from simultaneous switching of a large number of CMOS drivers must be controlled through proper substrate and package design. We will conclude the paper by comparing existing VLSI and PCB EDA tools for MCM design.

ICs on film strip lend themselves to automatic handling by manufacturer and user too : S. E. Scrupski, Electronics, 1 February (1971), p. 44

Modeling and simulation of interconnect materials has become critical to the success of high performance ULSI, packaging, and multilayer schemes for multichip modules. Computer simulation of the characteristic impedance Z (Ohms), capacitance C (pF), working frequency f (MHz) of Al asymmetric stripline filled with anodic Al oxide with dielectric constants 4 and 6.6 for multilayer schemes in a hybrid multichip module were conducted. A RLC-model of the frequency of Al transmission lines was successfully used. Using conformal mapping, the functional dependence of the characteristic impedance and working frequency on the capacitance of the Al stripline filled by anodic Al oxide can be determined. The results are valid for high frequencies. To evaluate this model and characterize its performance with high speed electrical multichip module design, a test cell using a multilayer interconnect structure Al/anodic al oxide on an Al substrate was developed.

Computer Aided Design And Reliability Assessment Of Microelectronic Packages

Software tools which implement the physics-of-failure approach have been developed for design and reliability assessment of multichip modules based on device architecture, environmental and test loads, and device mission life. The physics-of-failure approach addresses the damage physics of the failure phenomena in microelectronic devices, and is an alternative to empirical handbooks which involve the collection of field failure data and extrapolation of such data to obtain reliability estimates. The software tools developed, address the shortcomings of empirical methods. The structure of the software tools has been devised to address generic package architecture and materials. Some of the features of these software tools are discussed.