Multi-valued Memory Research Articles

Thermally Oxidized Memristor and 1T1R Integration for Selector Function and Low-Power Memory.

Resistive switching memories have garnered significant attention due to their high-density integration and rapid in-memory computing beyond von Neumann's architecture. However, significant challenges are posed in practical applications with respect to their manufacturing process complexity, a leakage current of high resistance state (HRS), and the sneak-path current problem that limits their scalability. Here, a mild-temperature thermal oxidation technique for the fabrication of low-power and ultra-steep memristor based on Ag/TiOx/SnOx/SnSe2/Au architecture is developed. Benefiting from a self-assembled oxidation layer and the formation/rupture of oxygen vacancy conductive filaments, the device exhibits an exceptional threshold switching behavior with high switch ratio exceeding 106, low threshold voltage of ≈1V, long-term retention of >104s, an ultra-small subthreshold swing of 2.5mVdecade-1 and high air-stability surpassing 4 months. By decreasing temperature, the device undergoes a transition from unipolar volatile to bipolar nonvolatile characteristics, elucidating the role of oxygen vacancies migration on the resistive switching process. Further, the 1T1R structure is established between a memristor and a 2H-MoTe2 transistor by the van der Waals (vdW) stacking approach, achieving the functionality of selector and multi-value memory with lower power consumption. This work provides a mild-thermal oxidation technology for the low-cost production of high-performance memristors toward future in-memory computing applications.

Multivalued Memory via Freezing of Super-Hard Magnetic Domains in a Quasi 2D-Magnet.

The design of high-density non-volatile memories is a long-standing dream, limited by conventional storage "0" or "1" bits. An alternative paradigm exists in which regions within candidate materials can be magnetized to intermediate values between the saturation limits. In principle, this paves the way to multivalued bits, vastly increasing storage density. Single-molecule magnets, are good examples offering transitions between intramolecular quantum levels, but require ultra-low temperatures and limited relaxation time between magnetization states. It is showed here that the quasi 2D-Ising compound BaFe2 (PO4 )2 overcomes these limitations. The combination of giant magneto-crystalline anisotropy, strong ferromagnetic exchange, and strong intrinsic pinning creates remarkably narrow magnetic domain walls, collectively freezing under Tf ≈15K. This results in a transition from a soft to a super-hard magnet (coercive force > 14T). Any magnetization can then be printed and robustly protected from external fields with an energy barrier >9T at 2K.

Correction to: Multi-valued neural networks I: a multi-valued associative memory

Here we provide a corrigendum on Theorem 2 to Article Title: Multi-Valued Neural Networks I: A Multi-Valued Associative Memory. https://doi.org/10.1007/s00521-021-05781-6.

Test Optimization in Memristor Crossbars Based on Path Selection

Memristors have recently shown significant promise in designing memory and logic subsystems. A 2D-crossbar architecture built with memristor arrays provides a convenient platform for storing multivalued memory states by utilizing the analog variation of current-induced resistance through these cells. The integration of CMOS components with non-CMOS memristor cells further enhances the scope of their applications to various complex system designs. However, present-day memristors by virtue of their inherent structure are prone to various manufacturing defects and sensitive to operational modalities. Existing techniques for testing memristor arrays are either ad hoc in nature or suited for application-specific designs with little concern for optimizing test time. In this work, we envisage a 2-D memristor crossbar as a network and identify certain paths that are suitable for fault sensitization. For full-size square and rectangular memristive crossbars, the proposed method optimizes test time using a path-based technique guided by maximum matching in bipartite graphs. An integer linear programming (ILP) formulation is then used to solve the problem for a general crossbar, either full or incomplete. Simulation results with LTspice demonstrate the effectiveness and superiority of the method to the prior art in terms of test time and fault coverage.

Analysis and Design of Multivalued High-Capacity Associative Memories Based on Delayed Recurrent Neural Networks.

This article aims at analyzing and designing the multivalued high-capacity-associative memories based on recurrent neural networks with both asynchronous and distributed delays. In order to increase storage capacities, multivalued activation functions are introduced into associative memories. The stored patterns are retrieved by external input vectors instead of initial conditions, which can guarantee accurate associative memories by avoiding spurious equilibrium points. Some sufficient conditions are proposed to ensure the existence, uniqueness, and global exponential stability of the equilibrium point of neural networks with mixed delays. For neural networks with n neurons, m -dimensional input vectors, and 2k -valued activation functions, the autoassociative memories have (2k)n storage capacities and heteroassociative memories have min {(2k)n,(2k)m} storage capacities. That is, the storage capacities of designed associative memories in this article are obviously higher than the 2n and min {2n,2m} storage capacities of the conventional ones. Three examples are given to support the theoretical results.

Transparent Floating Gate Memory Based on ZnO Thin Film Transistor With Controllable Memory Window

The transparent floating gate memory based on zinc oxide (ZnO) thin film transistors (TFTs) was fabricated by using one-step atom layer deposition of aluminia tunneling and ZnO charge-trap layers. Free electrons trapping mechanism of this memory device is proposed after systematical investigation of gate voltage scanning and thickness of the trapping layer. Furthermore, the relationship between the geometrical size of the charge-trapping layer and the memory window is explored. The devices with different memory windows can be controlled simply by designing the area of their trapping layer without any external process, which is much beneficial to the low cost process fabrication of the memory array and driving circuits, since the memory and switch/digital transistors can be fabricated at the same time. Finally, the presented TFT memory exhibits a maximum memory window of 15 V, excellent fatigue and retention properties more than 30,000 s without any charge loss. The transparent floating gate memory with the ZnO charge-trap layer has great potential for application of 3D, transparent or multi-value memory.

Multi-valued neural networks I: a multi-valued associative memory

A new concept of a multi-valued associative memory is introduced, generalizing a similar one in fuzzy neural networks. We expand the results on fuzzy associative memory with thresholds, to the case of a multi-valued one: we introduce the novel concept of such a network without number representation of weights and data, investigate its properties, and give a learning algorithm in the multi-valued case. We discovered conditions under which it is possible to store given pairs of network variable patterns in such a multi-valued associative memory. In the multi-valued neural network, not all variables are numbers, but elements or subsets of a lattice, i.e., they are all only partially ordered. Lattice operations are used to build the network output by inputs. In this paper, the lattice is assumed to be Brouwer and determines the implication used, together with other lattice operations, to determine the neural network output. We give the example of the network use to classify aircraft/spacecraft trajectories.

Multi-Valued Neural Networks II: A Robot Group Control

For the new concept of a multi-valued neural network introduced earlier, an analogue of the T-norm in fuzzy mathematics is considered. In the multi-valued neural network, all variables are elements of the lattice of linguistic variables, i.e., they are all only partially-ordered. The lattice operations are used to build the network output by inputs. However, a lattice elements' multiplication may also be used to determine such operations in the case when not all of them are allowed by the lattice construction. In this paper, the lattice is assumed to be residuated, and the residual construction gives the analogue of a T-norm. The lattice elements' multiplication determines the implication which is used, together with other lattice operations, in output determining of the neural network. Though, such a construction determines a multi-valued associative memory similar to the Brouwer lattice case considered earlier, this variant is more natural to use in the Kohonen-like networks that we demonstrate with the example of a robot group management.

Nanoscale Magnetization Reversal by Magnetoelectric Coupling Effect in Ga0.6Fe1.4O3 Multiferroic Thin Films.

The control of magnetism by electric means in single-phase multiferroic materials is highly desirable for the realization of next-generation magnetoelectric (ME) multifunctional devices. Nevertheless, most of these materials reveal either low working temperature or antiferromagnetic nature, which severely limits the practical applications. Herein, we selected room-temperature multiferroic Ga0.6Fe1.4O3 (GFO) with ferrimagnetism to study electric-field-induced nanoscale magnetic domain reversal. The GFO thin film fabricated on the (111)-orientated Nb-doped SrTiO3 single-crystal substrate was obtained through the pulsed laser deposition method. The test results indicate that the thin film not only exhibits ferroelectricity but also ferrimagnetism at room temperature. More importantly, reversible and nonvolatile nanoscale magnetic domains reversal under pure electrical fields is further demonstrated by taking advantage of its ME coupling effect with dependent origins based on iron ions. When providing an appropriate applied voltage, clear magnetic domain structures with large size can be easily manipulated. Meanwhile, the change ratio of the electrically induced magnetizations in the defined areas can reach up to 72%. These considerable merits of the GFO thin film may provide a huge potential in the ME multifunctional devices, such as the multi-value, low-energy-consuming, and nonvolatile memory and beyond.

An SBT-memristor-based crossbar memory circuit* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61703246 and 61703247), the Qingdao Science and Technology Plan Project (Grant No. 19-6-2-2-cg), and the Elite Project of Shandong University of Science and Technology.

Implementing memory using nonvolatile, low power, and nano-structure memristors has elicited widespread interest. In this paper, the SPICE model of Sr0.95Ba0.05TiO3 (SBT)-memristor was established and the corresponding characteristic was analyzed. Based on an SBT-memristor, the process of writing, reading, and rewriting of the binary and multi-value memory circuit was analyzed. Moreover, we verified the SBT-memristor-based 4 × 4 crossbar binary and multi-value memory circuits through comprehensive simulations, and analyzed the sneak-path current and memory density. Finally, we apply the 8 × 8 crossbar multi-value memory circuits to the images memory.

Percolation with plasticity for neuromorphic systems

We develop a theory of percolation with plasticity media (PWPs) rendering properties of interest for neuromorphic computing. Unlike the standard percolation, they have multiple (N ≫ 1) interfaces and exponentially large number (N!) of conductive pathways between them. These pathways consist of non-ohmic random resistors that can undergo bias induced nonvolatile modifications (plasticity). The neuromorphic properties of PWPs include: multi-valued memory, high dimensionality and nonlinearity capable of transforming input data into spatiotemporal patterns, tunably fading memory ensuring outputs that depend more on recent inputs, and no need for massive interconnects. A few conceptual examples of functionality here are random number generation, matrix-vector multiplication, and associative memory. Understanding PWP topology, statistics, and operations opens a field of its own calling upon further theoretical and experimental insights.

Pulse percolation conduction and multi-valued memory

We develop a theory of pulse conduction in percolation type materials such as noncrystalline semiconductors and nano-metal compounds. For short voltage pulses, the corresponding electric currents are inversely proportional to the pulse length and exhibit significant nonohmicity due to strong local fields in resistive regions of the percolation bonds. These fields can trigger local switching events incrementally changing bond resistances in response to pulse trains. Our prediction opens a venue to a class of multi-valued nonvolatile memories implementable with a variety of materials.

In-Memory Digital Comparator Based on a Single Multivalued One-Transistor-One-Resistor Memristor

In-memory computing based on multivalued memristive device opens the vision of building computing system with less resource and high performance. In this article, we achieved three distinguishable resistance states in mature one-transistor-one-resistor (1T1R) memristor. Furthermore, based on a single multivalued 1T1R device, for the first time, we successfully demonstrated an area-efficient in-memory digital comparator, which will cost five logic gates in complementary metal oxide semiconductor (CMOS) approach. The method is also easily expanded to multibit. Our work could be a representative of using multivalued nonvolatile memory device in digital information processing with improved performance.

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array

Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

Multi-valued charge trapping memory based on amorphous-indium-gallium-zinc oxide thin film transistor with designed Ga2O3/Al2O3 stack insulator

Multi-valued charge trapping memory is demonstrated based on an amorphous-indium-gallium-zinc oxide thin-film transistor (a-IGZO-TFT) with a Ga2O3/Al2O3 stack gate insulator. The memory device shows a positive shift of threshold voltage as large as 12.6 V after +20 V/1 s programming. The erasing process can be divided into two stages. Vertical electrical field erases the trapped electrons partially, resulting in negative threshold voltage shift with hump current in sub-threshold region. It is defined as a first erasing stage. Furthermore, the memory can be erased by UV-light effectively due to the generated electron-hole pairs in a-IGZO channel. It is defined as second erasing stage. The good retention characteristics are confirmed for various storage states. The storage mechanism is analyzed according to the energy band alignment obtained by XPS narrow scans and valence band spectra.

The Poole-Frenkel laws and a pathway to multi-valued memory

We revisit the mechanism of Poole-Frenkel nonohmic conduction in materials of nonvolatile memory. Percolation theory is shown to explain both the Poole and Frenkel dependencies corresponding to the cases of small and large samples compared to the correlation radii of their percolation clusters, respectively. The applied bias modifies a limited number of microscopic resistances forming the percolation pathways. That understanding opens a pathway to multivalued nonvolatile memory and related neural network applications.

Synthesization of Multi-valued Associative High-Capacity Memory Based on Continuous Networks with a Class of Non-smooth Linear Nondecreasing Activation Functions

This paper presents a novel design method for multi-valued auto-associative and hetero-associative memories based on a continuous neural network (CNN) with a class of non-smooth linear nondecreasing activation functions. The proposed CNN is robust in terms of the design parameter selection, which is dependent on a set of inequalities rather than the learning procedure. Some globally exponentially stable criteria are obtained to ensure multi-valued associative patterns to be retrieved accurately. The methodology, by generating CNN where the input data are fed via external inputs, avoids spurious memory patterns and achieves $$(2r)^n$$ storage capacity. These analytic results are applied to the associative memory of images. The fault-tolerant capability and the effectiveness are validated by illustrative experiments.

Influence of the Dzyaloshinskii–Moriya interaction on the topological Hall effect in crossed nanowires

We used micromagnetic simulations to investigate the influence of the Dzyaloshinskii–Moriya interaction (DMI) on the topological Hall effect (THE) in crossed nanowires with two characteristic magnetic structures, including radiated-shape and antivortex states. We show that the topological Hall resistivities separate into four values in the crossed nanowires, depending on both polarity and vorticity, even in the absence of a magnetic field. Therefore, by measuring the THE, we can simultaneously detect the polarity and vorticity under the influence of the DMI. This approach might be useful as a basic technique for study and development of next-generation multi-value memory.

Multi-valued static memory with resonant tunneling diodes as natural source of chaos

This paper brings deep study focused on dynamical behavior associated with a multi-valued static memory (MVSM) cell composed by a pair of the resonant tunneling diodes. Ampere–voltage characteristic of these diodes is approximated by the piecewise-linear scalar function with two positive breakpoints. Initial linear analysis supposes separation of a state space into nine affine segments, while local vector field geometry and dynamical flow in each region are graphically visualized. It is shown that discovered chaotic solution is not a numerical artifact, is robust and can generate various dense structurally stable strange attractors. For numerical investigations concepts of the largest Lyapunov exponent, the basins of attraction and a conventional signal analysis are adopted. MVSM dynamics is then implemented as the lumped electronic circuits using different but universal analog design approaches. Proposed oscillators are optimized with respect to the simple one-to-one relations between the mathematical model parameters and adjustable-by-hand circuit components. The constructed chaotic oscillators strictly utilize only commercially available active devices. This makes true experimental verification of idea that chaos exists inside narrow regions of a hyperspace of the internal MVSM system parameters possible and easy task.