Multiple-valued Logic Research Articles

Design of CNTFET-based Ternary Ring and Up–Down Counter Cells

In recent times, the multi-valued logic (MVL) design has been widely explored in the designing of digital computing circuits as the goals of enhanced processing capability with reduced interconnect complexity and small chip area are achieved. Hence, this work describes the design methodology of ternary logic-based asynchronous and synchronous up-counter, down-counter, and ring-counter designs using D-flip-flops in carbon nanotube technology. Carbon nanotube-field-effect transistors (CNTFETs)’ unique feature of altering the device threshold voltage by making variations in CNT diameter is exploited for the realization of multiple voltages in ternary logic design. Here the principle of the master-slave scheme is adopted for the designing of Dual shift-single shift and Single shift-dual shift-D-flip-flop circuits using the cyclic property of shifting operators. These flip-flop designs are further extended to construct multiple-digit counter structures which are suitable for realizing the logic functionality of up-counter, down-counter, and ring-counter designs. To exploit ternary logic increased computation capability benefit, a mode control up/down counter circuit is designed in which a single module is generating up and down-counting sequence based on applied mode input. To investigate the performance of the proposed designs, the simulations are performed using the Synopsys HSPICE simulator considering the 32 nm Stanford CNTFET model. According to the simulation results, a maximum energy consumption reduction up to 55% is obtained compared to the counterpart. Hence, the increased computational capability of three-valued logic is exploited in the presented work to achieve energy enhancements in designing ternary sequential circuits.

Towards Nonvolatile Spintronic Quaternary Flip-Flop and Register Design

The exciting properties of multi-valued logic (MVL) in overcoming the limitations of binary systems have led to widespread research on this topic. Considering various types of MVL, quaternary logic is more compatible with the existing binary systems. This paper proposes a nonvolatile quaternary flip-flop (NQFF) based on the unique features of the carbon nanotube field-effect transistors (CNTFETs) and magnetic tunnel junctions (MTJs). The proposed NQFF utilizes Spin-Hall effect (SHE)-assisted spin-transfer torque (STT) MTJs to provide nonvolatility with lower write energy, and multi-Vt gate-all-around (GAA) CNTFETs offer higher performance. On the other side, due to the usage of a shadow latch and the design of the proposed circuit, the delay of MTJ switching does not affect the delay of the whole circuit. The simulation results show that the proposed NQFF offers 50% lower PDP when the system is idle for only 25% of its total operational time.

Arthur N. Prior on the Labours of Ł3 Conjunctions

ABSTRACT In ‘Many-valued Logics’, a lecture broadcast over New Zealand's public radio in 1957, Arthur N. Prior (1914–1969) complained that conjunctions are put ‘to something like forced labour’ in Łukasiewicz's three-valued semantics, Ł3. In this paper, we discuss what Prior might have meant by this.

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

SummaryInternet‐of‐Things (IoTs)‐based embedded systems require energy‐efficient designs for long‐term operation. To achieve energy‐efficient designs, multiple‐valued logic (MVL) circuits and graphene nanoribbon field‐effect transistors (GNRFETs) are used instead of binary logic circuits and complementary metal‐oxide‐semiconductor (CMOS), respectively. This paper presents a novel ultra‐low power and energy‐efficient ternary Half‐Adder (THA) circuit based on unary operators, two power supplies (dual‐VDD), VDD and VDD/2, and two ternary 3:1 multiplexers in 32 nm GNRFET technology. The superiority of the proposed design are improvements between 2.86% and 60% in transistor count, between 86.12% and 97.15% in power consumption, and between 58.14% and 98.39% in power‐delay‐product (PDP) compared to existing THA circuits. Moreover, the proposed THA circuit is also implemented with 32 nm carbon nanotube field‐effect transistors (CNTFETs). Simulation results indicate that the proposed GNRFET‐based THA circuit increases delay by 1.74 × and reduces power/PDP by 89.41%/81.63% compared to its CNTFET‐based counterpart.

Multifunctional van der Waals heterostructures enabled by femtosecond laser-controlled band alignment engineering

Tailoring the band alignment of van der Waals (vdW) heterostructures is essential for regulating the electronic and optoelectronic performance of devices with superior functions. However, current band alignment engineering methods suffer from complexity, inflexibility, and limited tuning range, which hinders further applications. In this study, we demonstrate a novel strategy for tailoring the band alignment of BP/MoS2 heterostructures using femtosecond (fs) laser-controlled band alignment engineering. Although this approach compromises the rectification ratio of heterostructures, it dramatically expands the tuning range of the band alignment and improves optoelectronic response by localized doping and healing effect at heterojunctions. We also present a new physical model to describe carrier transport behavior for m-n-p structures and investigate the effect of fs laser irradiation. Finally, two conceptual devices are demonstrated to show the advanced applications of this post-processing technique. In optoelectronic applications, we utilized this strategy to improve photoresponsivity (> 8 times), detectivity (∼1.48 ×1011 Jones), and fill the response gap in the NIR region of photodetectors. In multivalued logic applications, site-specific engineering was used to transform the inverter operating mode from binary to ternary with a wide output swing (∼90%) by creating a unique NDT region. Our study demonstrates the potential of fs laser irradiation as a high-spatial-accuracy, air-stable, and versatile band alignment engineering method for electronic and optoelectronic applications in the future.

A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

The Conventional Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) design techniques have limitations in designing the Integrated Circuit (ICs), especially with memories of multiple valued logic (MVL) in nanotechnologies. FinFET technologies provide the possibilities of low logic gates and small chip areas with high speed. Memories play an essential role in all types of devices. This paper aims to optimize the power and increase the speed of the SRAM Cell and Array using different techniques in 18nm FinFET technology. The presence of a ternary input provides an additional degree of freedom for the operation of the memory cell. The SRAM cells are also implemented at a Quantum level to improve the results in terms of area, energy, and speed. Simulation and Analysis of the design is done using Cadence Virtuoso Analog Design Environment Tool and Quantum Dot Cellular Automata Designer Tool. The proposed Multi-Threshold Complementary MOS (MTCMOS) based SRAM Array design exhibits an improvement of 4.56% in power consumption and 19.29% in speed as compared to a Conventional CMOS SRAM Array. The proposed ternary implementation of the MTCMOS-based SRAM cell is found to have a 24.9% reduction in power consumption and a 39% improvement in speed as compared to the proposed conventional ternary CMOS SRAM array while SRAM cell latency is 1 clock cycle. It occupies an area of 0.04 µm2 and consists of 33 quantum cells. The average energy dissipation of this SRAM cell is found to be 40% better than the latest existing literature for the design.

Modulating the Function of GeAs/ReS2 van der Waals Heterojunction with its Potential Application for Short-Wave Infrared and Polarization-Sensitive Photodetection.

Van der Waals heterojunction (vdWs) of 2D materials with integrated or extended superior characteristics, opening up new opportunities in functional electronic and optoelectric device applications. Exploring methods to achieve multifunctional vdWs heterojunction devices is one of the most promising prospects in this area. Herein, a diverse function of forward rectifying diode, Zener tunneling diode, and backward rectifying diodes are realized in GeAs/ReS2 heterojunction by modulating the doping level of GeAs. The tunneling diode presents an interesting trend forward negative differential resistance (NDR) behavior which may facilitate the application of multi-value logic. More importantly, the GeAs/ReS2 forward rectifying diode exhibits highly sensitive photodetection in the wide-spectrum range up to 1550nm corresponding to a short-wave infrared (SWIR) region. In addition, as two strong anisotropic 2D materials of GeAs and ReS2 , the heterojunction exhibits strong polarization-sensitive photodetection behavior with a dichroic photocurrent ratio of 1.7. This work provides an effective strategy to achieve multifunctional 2D vdW heterojunction devices and develops more possibilities to broaden their functionalities and applications.

MULTIBIT MEMORY CELL DESIGN USING MULTIPLE VALUED LOGIC

The semiconductor market has been growing gradually over the long term, despite periodic troughs and peaks, and it is projected that this trend will continue in the years to come. The NAND Flash, which is designed for the data storage market, and the NOR Flash, which is addressing both the code and data storage segments due to its versatility, are the only types of Flash cells and architectures that can currently be considered industry standards. In this paper, a novel multibit flash memory cell is proposed. Multi valued logic allows for the storage of many bits in a single cell. The multilevel approach, where two bits are stored at the same level, should also be understood. The MultipleValued Logic system is one of the most promising approaches for achieving future beyond-binary electronics and systems. Multiple-valued logic can improve circuit connectivity, reduce chip space, and improve bus efficiency because more logic levels are used per line than in conventional binary logic. Mentor graphics software is used to assess the performance measures.

BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars

Logic-in-memory with memristive crossbars is an attractive approach for realizing beyond von Neumann architectures. Multi-valued logic (MVL) containing more than two logic levels can enhance the computing speed with reduced number of logic operations. In this paper, a binary-compatible multi-valued logic-in-memory (BC-MVLiM) scheme is proposed with memristive dual-crossbars where both inputs and outputs are represented by the multi-level cells of memristors. Both of the binary and multiple-valued logic operations can be implemented in the proposed BC-MVLiM scheme depending on the radix of inputs. The proposed BC-MVLiM circuitry supports multiple row-wise and column-wise logic gates with multiple fan-ins and fan-outs for binary and ternary systems by leveraging both inter-and intra-crossbar operations. Experimental results show that the proposed BC-MVLiM-based multi-digit adder enhances the computation speed by up to 76.10% and 83.82%, for binary and ternary systems, respectively, as compared with the previously published memristive logic designs. By preventing the errors from propagating across multiple stages, the error rate of proposed BC-MVLiM is also reduced by up to 98.20% compared to the previous memristive logic designs in the presence of device variations.

MODULAR MANY-VALUED SEMANTICS FOR COMBINED LOGICS

AbstractWe obtain, for the first time, a modular many-valued semantics for combined logics, which is built directly from many-valued semantics for the logics being combined, by means of suitable universal operations over partial non-deterministic logical matrices. Our constructions preserve finite-valuedness in the context of multiple-conclusion logics, whereas, unsurprisingly, it may be lost in the context of single-conclusion logics. Besides illustrating our constructions over a wide range of examples, we also develop concrete applications of our semantic characterizations, namely regarding the semantics of strengthening a given many-valued logic with additional axioms, the study of conditions under which a given logic may be seen as a combination of simpler syntactically defined fragments whose calculi can be obtained independently and put together to form a calculus for the whole logic, and also general conditions for decidability to be preserved by the combination mechanism.

Quasivarieties of Wajsberg hoops

In this paper we deal with quasivarieties of residuated structures which form the equivalent algebraic semantics of a positive fragment of some substructural logic. Our focus is mainly on varieties and quasivarieties of Wajsberg hoops, which are the equivalent algebraic semantics of the positive fragment of Łukasiewicz many-valued logic. In particular we study the lattice of subquasivarieties of Wajsberg hoops and we describe completely all the subvarieties of Wajsberg hoops that are primitive. Though the treatment is mostly algebraic in nature, there are obvious connections with the underlying logics.

Data Verification in the Agent, Combining Blockchain and Quantum Keys by Means of Multiple-Valued Logic

Network control of autonomous robotic devices involves a vast number of secured data coding, verification, and identification procedures to provide reliable work of distant agents. Blockchain scheme provides here the model of the extended linked list for the verification of critical data, approved by quasi-random hash values assigned by external network nodes. And quantum lines are the source of high-quality quasi-random keys used as hash values. Discrete multiple-valued logic in such procedures is a simple and flexible tool to form the logic linked list, combining critical internal parameters of agents with data taken from external nodes. Such combination enlarges the set of possible schemes for data protection from illegal modifications and for data restoration.

Application of logical modeling for the analysis and classification of medical data for the purpose of diagnosis.

The subject of the research is a logical approach to data analysis and the development of software tools capable of identifying hidden patterns, even with a limited amount of data. The input data consists of indicators of the diagnosis of patients, their diagnoses and the experience of doctors obtained in the course of medical practice. The research method is the development of software tools based on systems of multivalued predicate logic for the analysis of patient data. This approach considers the source data as a set of general rules, among which it is possible to distinguish those rules that are sufficient to explain all the observed data. These rules, in turn, are generative for the area under consideration and help to better understand the nature of the objects under study. The novelty of the study lies in the use of multivalued logic to analyze a limited amount of medical data of patients in order to determine the most likely diagnosis with a given accuracy. The proposed approach makes it possible to detect hidden patterns in the symptoms and results of patient examinations, classify them and identify unique signs of various forms of gastritis. Unlike neural networks, logical analysis is transparent and does not require training on large amounts of data. The conclusions of the study show the possibility of such an approach for diagnosis with a lack of information, as well as the offer of alternatives if the required accuracy of diagnosis is not achieved.

MXene-Based Sc2CHO/Sc2NHO/Sc2CHO Magnetic Tunnel Junctions for Multi-Value Logic Computing Devices: A First Principles Study

The rapid development of technologies such as machine learning and artificial intelligence has further accelerated the growth of multi-value logic (MVL) computing nanodevices. However, current MVL nanodevices based on conventional materials face the challenges of low peak–valley ratio (PVR) and unstable spin filtering effects. Therefore, the intrinsic half-metal nanoscale MXene has become the answer to the development bottleneck of MVL nanodevices for its outstanding properties such as high Curie temperature and an appropriate band structure. The present work attempts to design spintronic magnetic tunnel junctions (MTJs) based on new predicted Sc2CHO as half-metallic electrodes and Sc2NHO as semiconductor-based scattering regions. Furthermore, we simulate its transport properties from density functional theory combined with nonequilibrium Green’s function. And we have considered the effect of the length of the scattering region on MTJ performance. According to our calculations, the spintronic transport of the MTJs demonstrates up to perfect 100% polarizability spin currents stably due to the single-channel conduction capability of half-metal Sc2CHO. The MTJs exhibit a significant negative differential resistance (NDR) phenomenon, with the PVR of the type 2N reaching 1.28 × 106, the highest value among the two-dimensional spintronic nanodevices currently being theoretically explored. MTJs with a high PVR will be beneficial for the application and development of MVL nanodevices. The spin filtering effect and NDR phenomenon can be well-maintained as the scattering region length increases, and the PVR usually almost always remains 104. This is well reflected in the transmission spectra and molecular projection self-consistent Hamiltonian. The tunneling magnetoresistance phenomenon is also observed.

Energy efficient design of unbalanced ternary logic gates and arithmetic circuits using CNTFET

The emergence of multi-valued logic (MVL) is a substitute to binary logic approaches for realizing high-information density logic systems and high-operating speed systems. In this paper, a design for standard ternary inverter (STI), ternary NAND (TNAND), ternary NOR (TNOR) using carbon nanotube field effect transistors (CNTFETs) is proposed in which a p-type dynamic diode is used with the goal of lowering the energy consumption expressed as power delay product (PDP) and thereby reducing battery usage. Additionally, the basic arithmetic operations are then performed using proposed ternary logic circuits, which can be extended to realize more complex operations. The proposed designs are simulated in HSPICE using a 32 nm Stanford CNTFET model. With respect to variation in process parameters, the reliability of the proposed STI circuit is examined. Simulation results verify that the proposed designs show improvement in terms of power consumption and power delay product (PDP) compared to the other CNTFET based ternary logic circuits. Moreover, less variations are observed in power and PDP of the proposed logic gates with variation in process parameters, capacitance, temperature, frequency and supply voltage. The proposed circuit designs of STI, TNAND, TNOR, ternary half adder (THA), ternary multiplier (TMUL) show 78 %, 98 %, 99 %, 99 %, 99 % improvement in PDP respectively, as compared to the conventional CNTFET based circuit designs and 99 % PDP improvement in all proposed circuits compared to CNTFET based logic circuits with resistive load.

Highly-Efficient CNTFET-Based Unbalanced Ternary Logic Gates

A large number of interconnections required to implement a binary logic-based circuit leads to an increase in power/energy consumption and area overhead. Utilizing multiple-valued logic (MVL), especially ternary logic, can improve power/energy and total area by reducing the number of interconnections. A ternary logic-based circuit is easily implemented by using carbon nanotube field-effect transistors (CNTFETs) because they have the capability of manifesting different threshold voltages. This paper uses CNTFET devices for the design and implementation of highly-efficient ternary logic gates such as the standard ternary inverter (STI), ternary buffer (TBUF), ternary OR (TOR), and ternary AND (TAND). The proposed STI design offers improvement between 12% and 91.17% in energy consumption and increases noise margin by at least 1.02×, while the proposed TBUF design reduces energy consumption by 14.73%–96.82%. Furthermore, the proposed TOR design reduces power dissipation and energy consumption by at least 72.62% and 84.80%, while the proposed TAND design improves them by at least 8.55% and 11.38%, respectively. The simulations have been performed by using HSPICE software with the Stanford 32 nm CNTFET model at 0.9 V supply voltage.

The Logic Doctrine of A.A. Zinoviev

The article is devoted to the analysis of the main provisions of A.A. Zinoviev’s logic doctrine. The author shows Zinoviev’s evolution from the traditional view of the formal logic as knowledge of the laws and regulations of correct thinking to the understanding of it as the science that deals with the aspects of natural language that make it the instrument of thinking and comprehension. According to Zinoviev, the logic singles out and abstracts in language phenomena certain structural components that form the structure of knowledge irrespective of whether this knowledge pertains to the sphere of physics, biology, history, sociology etc. The laws and regulations prescribed by it are not discovered by people, but are invented by them in the process of cognition methods perfecting. The author characterizes Zinoviev’s innovative contribution to the development of non-standard logics, and above all, multivalued logic, succession theory, logic principles of the natural and social science methodology, as well as to the creation of complex logic. The author shows the actual importance of Zinoviev’s logic and methodological legacy for the development of scientifi c perception and for the resistance to the phenomenon that the thinker referred to as the threatof mass stupefaction.

Chiro-Optoelectronic Encodable Multilevel Thin Film Electronic Elements with Active Bio-Organic Electrolyte Layer.

It is suggested that chiral photonic bio-enabled integrated thin-film electronic elements can pave the base for next-generation optoelectronic processing, including quantum coding for encryption as well as integrated multi-level logic circuits. Despite recent advances, thin-film electronics for encryption applications with large-scale reconfigurable and multi-valued logic systems are not reported to date. Herein, highly secure optoelectronic encryption logic elements are demonstrated by facilitating the humidity-sensitive helicoidal organization of chiral nematic phases of cellulose nanocrystals (CNCs) as an active electrolyte layer combined with printed organic semiconducting channels. The ionic-strength controlled tunable photonic band gap facilitates distinguishable and quantized 13-bit electric signals triggered by repetitive changes of humidity, voltage, and the polarization state of the incident light. As a proof-of-concept, the integrated circuits responding to circularly polarized light and humidity are demonstrated as unique physically unclonable functional devices with high-level logic rarely achieved. The convergence between functional nanomaterials and the multi-valued logic thin-film electronic elements can provide optoelectronic counterfeiting, imaging, and information processing with multilevel logic nodes.

A High-Speed Low-Energy One-Trit Ternary Multiplier Circuit Design in CNTFET Technology

Contemporary system-on-chip-based applications are battery-powered. To increase the operation time, they need various low-power/energy circuits. Carbon nanotube field-effect transistor (CNTFET) is a potential alternative to complementary metal-oxide-semiconductor for power/energy-efficient circuits implementation due to offering high performance. Another way to reduce power/energy consumption in a circuit is to use multiple-valued logic, especially ternary logic, which has three logical states. This paper presents a novel 1-trit ternary multiplier circuit with 23 transistors based on only unary operators of the ternary logic system and the dual-supply voltages technique. The proposed design does not use the ternary decoder/encoder, logic gates, cascading transmission gates, and ternary multiplexer to reduce the transistors count, delay, power, and energy. The Stanford CNTFET model in the 32 nm technology node is used to simulate the proposed design. The delay, power, and delay-power-product (PDP) of the proposed design at 0.9 V are 0.026 ns, 0.139 μW, and 3.614 aJ, respectively. It offers improvements between 50% and 61.19% in delay and between 52.72% and 59.75% in PDP compared to previously published multiplier circuits, which are based on the dual-supply voltages and use 23 transistors. These improvements make the proposed design a good candidate for the design of the next generation of multiplier circuits in arithmetic blocks.

A Kind of Optoelectronic Memristor Model and Its Applications in Multi-Valued Logic

Memristors have been proved effective in intelligent computing systems owing to the advantages of non-volatility, nanometer size, low power consumption, compatibility with traditional CMOS technology, and rapid resistance transformation. In recent years, considerable work has been devoted to the question of how to design and optimize memristor models with different structures and physical mechanisms. Despite the fact that the optoelectronic effect inevitably makes the modelling process more complex and challenging, relatively few research works are dedicated to optoelectronic memristor modelling. Based on this, this paper develops an optoelectronic memristor model (containing mathematical model and circuit model). Moreover, the composite memristor circuit (series- and parallel-connected configuration) with a rotation mechanism is discussed. Further, a multi-valued logic circuit is designed, which is capable of performing multiple logic functions from 0–1, verifying the validity and effectiveness of the established memristor model, as well as opening up a new path for the circuit implementation of fuzzy logic.