Multi-transputer Systems Research Articles

Multi-transputer systems with dynamic reconfiguration control based on the serial bus

The paper presents new architectures of dynamically reconfigurable multi-transputer systems based on first generation transputers. Transputer link connections in the proposed systems are organized in crossbar switches on demand in the application program at run-time. Link connection reconfiguration control is based on transmission of control messages through the serial bus compatible with the transputer link protocol. The bus is built using the TRANSBUS controller proposed and designed by IRESTE University of Nantes. 1 Two dynamically reconfigurable multi-transputer architectures are discussed. The first one, called GARTS, is based on nine-worker transputer clusters with unrestricted dynamic link connectivity. Inter-cluster connections are also dynamically organized. The second architecture, called HP-MODTRANS, is based on three-transputer fully connected clusters with dynamically organized inter-cluster link connections. The structures and functional properties of both architectures are discussed. Then, analytical model for reconfiguration control communication overheads and some performance figures obtained using these models are presented for the discussed architectures.

HP-FLEXAR: A reconfigurable multi-unit heterogeneous topology architecture for time critical applications

The main objective of this paper is to present a newly developed high performance reconfigurable multitransputer heterogeneous topology architecture called HP-FLEXAR. The proposed architecture is aimed to be used for time critical applications, especially for performing such computational tasks which could be solved in separate heterogeneous topology execution units using parallel decomposition and allocation algorithms. The HP-FLEXAR enables dynamic assignment of program tasks to the worker transputers of separate execution units. The heterogeneous topology of these units can be also dynamically changed (during a program execution) according to the run-time analysis performed in the HP-FLEXAR decision and distribution unit (a DD unit). A feedback between the execution and DD units is one of the most important features of the HP-FLEXAR architecture. This enables taking full advantage of its dynamic reconfiguration capabilities. The HP-FLEXAR being a flexible architecture is not limited to the above applications. One of the other areas of its potential applications is support of development of architectural concepts and communication strategies aimed to increase the efficiency of reconfigurable multi-transputer systems. This can be achieved through direct mapping of different multi-transputer architectural designs onto the HP-FLEXAR structure.

The ZEUS Eventbuilder: experience with a distributed real-time parallel transputer system

The Eventbuilder of the ZEUS experiment is a real-time parallel data formatting and transport system. It combines data flows originating from various detector components and transfers them to the third level trigger processor farm. The Eventbuilder is based on an asynchronous packet-switching transputer network and uses transputer links for bulk data transfer. A high-speed 64/spl times/64 custom made crossbar switch allows dynamic linking of any detector component to any branch of third level processor nodes, offering a bandwidth of more than 24 MB/s over a distance of 100 m. Experience gained in operating a transputer network, constructing transputer specific hardware, and developing parallel software is promising. Multi-transputer systems are easy-to-build, can be efficiently programmed in the common high-level language C, and are running stably and reliably.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Real-time behavior monitoring for multi-processor systems

Monitoring tools to observe the behavior of multi-task programs running on multi-processor architectures are important to help debugging complex real-time applications. To design such a tool, two issues are to be solved, relevant information gathering without disturbing the application behavior, display of this information in a way easily interpreted by designers. This paper presents a new solution for these two above issues. First, it describes a method and a tool to collect an event trace which can be implemented by software only or in an hybrid (software and hardware) way. Information to be collected are automatically selected from the tool and the overhead monitoring time is kept very low. Then, it describes the display tool which clearly shows to the designer the inter-function dependencies, all task states and execution times of real-time kernel primitives. This tool may also be used by designers to observe the value of relevant internal variables of the system. Our solution is target independent: it can be implemented on multi-transputer systems or on any conventional or heterogeneous microprocessor architectures.

Instrumental complex of parallel software system development and operating environment support for distributed processing within multitransputer systems, TRANSSOFT

No abstract available.

Dynamically reconfigurable multi-transputer systems with serial bus control

New architectural solutions for dynamically reconfigurable multitransputer systems are proposed in the paper. They are based on transmissions of configuration requests from worker to control transputers through the serial bus which connects selected links of these transputers.

DELTA-T: A user-transparent software-monitoring tool for multi-transputer systems

Monitoring tools are important parts of future programming environments for parallel computers. In this paper the software monitor DELTA-T is presented which has been developed for performance monitoring of (standard) multi-transputer systems at the University of Paderborn. Instrumentation is implemented by ‘spy’-processes which are inserted into the target system either to observe it at the node or at the process level. Measurement traces generated by these spies are buffered locally in the node memories. A global system view is achieved by time-stamping the recorded events with a globally valid system time. Evaluation is carried out offline on a host workstation either with an animation tool or an interactive graphical visualization tool.

SIMPAC-T : A simulator for multitransputer systems

Performance evaluation of parallel algorithms and architectures has several advantages. We present an event driven simulator for performance evaluation and modelling of multitransputer systems. The system topology and architectural details are input to the simulator. The application program is mapped by the user on to the system using the higher level primitives of the simulation language provided. The simulator produces performance metrics of resource (processor, communication link) utilization besides process sojourns in various states. A trace file containing the log of the system snapshots is output which can be used for various analyses by the user and the system designer.

Distributed shared-memory implementation for multitransputer systems

A new method for the implementation of distributed shared memory on multitransputer systems is presented. The method is based on an extension of the common parallel programming language occam2, allowing the use of constructs such as virtual channels, global semaphores, and shared variables (with strong coherence). The allocation of the shared variables is done at compile-time on any of the available transputer nodes. Semaphores allow explicit process synchronization, while virtual channels facilitate the programmer's task, by providing an abstract view of process communication, regardless of the particular network topology.

Concurrent simulation of neurons on multi-Transputer systems

This paper reports on a concurrent approach to efficiently simulate neurons on multi-Transputer systems. The neurons are represented as a series of interconnected isopotential compartments modeled by lumped electrical components. The corresponding system of first-order ODEs is mapped onto processor arrays of various sizes. The concurrent OCCAM program can be easily adapted to different model equations or integration methods.

A distributed dynamic load balancer and its implementation on multi-transputer systems for molecular dynamics simulation

A new and efficient approach is described to the dynamic load-balancing problem which is central in concurrent computing. A transputer-based implementation is tested on a molecular dynamics simulation of spinodal phase separation.

Supercomputing with transputers—past, present and future

The paper traces the development of large multi-transputer systems for high-performance scientific and engineering computing. After defining what we mean by 'supercomputing' in the context of this paper, the past and present state of transputer supercomputing environments is illustrated by a discussion of three specific projects. These are the Esprit 'SuperNode' project or P1085, the Edinburgh Concurrent Supercomputer project and the Victor project at IBM Research in Yorktown Heights. The present parallel programming environments available for transputer systems are also briefly reviewed. The paper concludes with a look to the future. Inmos' announced plans for the next generation transputer, code-named H1, are described along with a comparison with the new Intel iWarp chip. We can classify this Intel component as a 'generic' transputer in that it integrates computing elements, memory elements and communication hardware on a single VLSI chip. Both these new components should make for a bright future for supercomputing with transputer-like building blocks.

Implementing CS-Prolog on a communicating process architecture

The distributed implementation techniques of CS-Prolog in a multitransputer environment are presented in the paper. The first section gives an overview of CS-Prolog including the explanation of the extra built-in predicates. Section 2 describes the distributed backtracking scheme of CS-Prolog. The solution of a natural language parser problem illustrates how CS-Prolog can be used for parallel processing. Sections 4 and 5 describe the distributed implementation; the decisions and techniques used for implementing CS-Prolog on multitransputer systems. The last section contains a demonstration example of CS-Prolog used for simulating a deadlock detection algorithm for solving a problem encountered during the distributed implementation of CS-Prolog.

CS-PROLOG on multitransputer systems

This paper presents a concurrent extension of prolog called cs-prolog ∗ ∗ cs-prolog is a joint development between Multilogic Computing Ltd, Brainware Gmbh and Densitron Computers (Communicating Sequential prolog) which explicitly involves the concept of communicating sequential processes and is intended to be implemented on distributed (nonshared memory) parallel computers, mainly on transputer networks. cs-prolog can also be considered as a distributed simulation language. First, an informal introduction to cs-prolog summarizes the main features of the language. The power of the language is illustrated by solving some simple problems. The scheduling principles of cs-prolog on single transputers and on multiple transputer systems are described in detail. The cs-prolog distributed backtracking algorithm is defined and the details of distributed implementation on multitransputer systems are explored. cs-prolog is currently available on monoputers and multiputers connected to PC-compatible hosts.

Dynamically reconfigurable multi-transputer systems

Multi-transputer systems containing large number of transputers can operate more efficiently if they are dynamically reconfigurable. This paper proposes two methods of achieving high-speed dynamic reconfiguration and discusses how system reliability can be improved without sacrificing cost advantage by introducing measured redundancy in the second system.