Multithreaded Execution Research Articles

A Hardware Memory Race Recorder for Deterministic Replay

As hardware vendors transition to multicore chips, software vendors face increased software reliability challenges. To effectively debug software in this new world, developers must be able to replay executions that exhibit a bug so that they can zero in on concurrency bugs - especially intermittent ones. Such deterministic replay also aids fault detection and recovery, intrusion detection, and the like. Deterministic replay requires both a recorder and a replayer. The recorder logs information during multithreaded program execution that is sufficient to enable deterministic replay. In the postmortem analysis, the replayer uses the logged information, together with the program binary, to faithfully replay the original execution. The replay will always exercise the same bugs and produce the same outputs. Clearly, an investment in modest chip resources has great potential to ease the challenges of debugging the multithreaded software that both users and vendors will continue to demand

A Multithreaded Distributed Telerobotic Framework

A reliable real-time client-server telerobotic system that uses a distributed component framework to promote software reusability, ease of extensibility, debugging, and data encapsulation is proposed. .NET remoting is used for automatic handling of the network resources and data transfer while isolating the components from network protocol issues. A client-server transfer of live stereo video provides the operator three-dimensional (3-D) views of the slave scene with augmented reality (AR) framework and services. Overall distributed framework and design independence improves the portability and modularity of the proposed telerobotic system. A multithreaded execution is proposed for streaming of force, command, and for the transfer of live stereo video data. The proposed framework provides a useful integrated software and hardware environment to enhance man-machine interactions using stereo visualization and AR in real-time telerobotic systems

Data-Driven Multithreading Using Conventional Microprocessors

This paper describes the data-driven multithreading (DDM) model and how it may be implemented using off-the-shelf microprocessors. Data-driven multithreading is a nonblocking multithreading execution model that tolerates internode latency by scheduling threads for execution based on data availability. Scheduling based on data availability can be used to exploit cache management policies that reduce significantly cache misses. Such policies include firing a thread for execution only if its data is already placed in the cache. We call this cache management policy the CacheFlow policy. The core of the DDM implementation presented is a memory mapped hardware module that is attached directly to the processor's bus. This module is responsible for thread scheduling and is known as the thread synchronization unit (TSU). The evaluation of DDM was performed using simulation of the data-driven network of workstations (D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> NOW). D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> NOW is a DDM implementation built out of regular workstations augmented with the TSU. The simulation was performed for nine scientific applications, seven of which belong to the SPLASH-2 suite. The results show that DDM can tolerate well both the communication and synchronization latency. Overall, for 16 and 32-node D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> NOW machines the speedup observed was 14.4 and 26.0, respectively

SAC—A Functional Array Language for Efficient Multi-threaded Execution

We give an in-depth introduction to the design of our functional array programming language SAC, the main aspects of its compilation into host machine code, and its parallelisation based on multi-threading. The language design of SAC aims at combining high-level, compositional array programming with fully automatic resource management for highly productive code development and maintenance. We outline the compilation process that maps SAC programs to computing machinery. Here, our focus is on optimisation techniques that aim at restructuring entire applications from nested compositions of general fine-grained operations into specialised coarse-grained operations. We present our implicit parallelisation technology for shared memory architectures based on multi-threading and discuss further optimisation opportunities on this level of code generation. Both optimisation and parallelisation rigorously exploit the absence of side-effects and the explicit data flow characteristic of a functional setting.

Synergistic Processing in Cell's Multicore Architecture

Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism. The streamlined architecture provides an efficient multithreaded execution environment for both scalar and SIMD threads and represents a reaffirmation of the RISC principles of combining leading edge architecture and compiler optimizations. These design decisions have enabled the Cell BE to deliver unprecedented supercomputer-class compute power for consumer applications

POWER5 system microarchitecture

This paper describes the implementation of the IBM POWER5TM chip, a two-way simultaneous multithreaded dual-core chip, and systems based on it. With a key goal of maintaining both binary and structural compatibility with POWER4TM systems, the POWER5 microprocessor allows system scalability to 64 physical processors. A POWER5 system allows both single-threaded and multithreaded execution modes. In single-threaded execution mode, a POWER5 system allows for higher performance than its predecessor POWER4 system at equivalent frequencies. In multithreaded execution mode, the POWER5 microprocessor implements dynamic resource balancing to ensure that each thread receives its fair share of system resources. Additionally, software-settable thread priority is enforced by the POWER5 hardware. To conserve power, the POWER5 chip implements dynamic power management that allows reduced power consumption without affecting performance.

Shared memory multiprocessor support for functional array processing in SAC

Classical application domains of parallel computing are dominated by processing large arrays of numerical data. Whereas most functional languages focus on lists and trees rather than on arrays, SAC is tailor-made in design and in implementation for efficient high-level array processing. Advanced compiler optimizations yield performance levels that are often competitive with low-level imperative implementations. Based on SAC, we develop compilation techniques and runtime system support for the compiler-directed parallel execution of high-level functional array processing code on shared memory architectures. Competitive sequential performance gives us the opportunity to exploit the conceptual advantages of the functional paradigm for achieving real performance gains with respect to existing imperative implementations, not only in comparison with uniprocessor runtimes. While the design of SAC facilitates parallelization, the particular challenge of high sequential performance is that realization of satisfying speedups through parallelization becomes substantially more difficult. We present an initial compilation scheme and multi-threaded execution model, which we step-wise refine to reduce organizational overhead and to improve parallel performance. We close with a detailed analysis of the impact of certain design decisions on runtime performance, based on a series of experiments.

JVM Independent Replay in Java

Deterministic replay can help to understand the cause of a failing execution of a multi-threaded program. Stepwise browsing of a counterexample serves the same purpose in the context of static and dynamic checking. In this paper we present a tool for deterministic replay of a multi-threaded execution of a Java program. The replay engine is independent of a specific JVM. We also suggest a language to describe thread schedules. Such schedules can be produced either directly by a tool or virtual machine or can, given some additional information, be extracted from a bytecode trace. Thus, off-the-shelf debuggers can be used for both, cyclic debugging of multi-threaded Java programs, and for browsing of concurrent execution traces produced by many checking tools. Experimental results show that correct replay can be performed with acceptable overhead across a number of virtual machines. Plug-ins have been implemented to generate schedules automatically for Java PathFinder and for JNuke.

NePSim: a network processor simulator with a power evaluation framework

This article presents NePSim, an integrated system that includes a cycle-accurate architecture simulator, an automatic formal verification engine, and a parameterizable power estimator for NPs consisting of clusters of multithreaded execution cores, memory controllers, I/O ports, packet buffers, and high-speed buses. To perform concrete simulation and provide reliable performance and power analysis, we defined our system to comply with Intel's IXP1200 processor specification because academia has widely adopted it as a representative model for NP research.

A cluster-based solution for high performance hmmpfam using EARTH execution model

Hmmpfam is a widely used computation-intensive bioinformatics software for sequence classification. The contribution of this paper is the first largely scalable and robust cluster-based solution of parallel hmmpfam based on EARTH (Efficient Architecture for Running Threads), which is an eventdriven fine-grain multi-threaded programming execution model. When compared with the original PVM implementation, our implementation shows notable improvements on absolute speed-up and better scalability. Experiments on two advanced supercomputing clusters at Argonne National Laboratory achieve an absolute speedup of 222.8 on 128 dual-CPU nodes for a representative data set, which means that the total execution time is reduced from 15.9 h (serial program) to only 4.3 min.

Dynamic tiling for effective use of shared caches on multithreaded processors

Simultaneous multithreaded (SMT) processors use data caches which are dynamically shared between threads. Depending on the processor workload, sharing the data cache may harm performance due to excessive cache conflicts. A way to overcome this problem is to physically partition the cache between threads. Unfortunately, partitioning the cache requires additional hardware and may lead to lower utilisation of the cache in certain workloads. It is therefore important to consider software mechanisms to implicitly partition the cache between threads by controlling the locations in the cache in which each thread can load data. This paper proposes standard program transformations for partitioning the shared data caches of SMT processors, if and only if there are conflicts between threads in the shared cache at runtime. We propose transformations based on dynamic tiling. The key idea is to use two tile sizes in the program, one for single-threaded execution mode and one suitable for multithreaded execution mode and switch between tile sizes at runtime. Our transformations combine dynamic tiling with either copying or storing arrays in block layout. The paper presents an implementation of these transformations along with runtime mechanisms for detecting cache contention between threads and react to it on-the-fly. Our experimental results show that for regular, perfect loop nests, these transformations provide substantial performance improvements.

Distributed-sum termination detection supporting multithreaded execution

A fast, wire-efficient synchronization technique is developed that supports dynamic allocation of multiple threads on shared-memory, message-passing, and/or single-chip multiprocessors. The proposed distributed-sum bit-comparison (DSBC) method employs the execution-sequence invariant property such that the instantaneous process production equals the instantaneous process consumption only upon barrier completion. For a system of n processing elements (PEs), a single instance of the global logic unit, and n instances of the local logic unit, interconnected by 3 n wires, are shown to provide direct support for any arbitrary number of barriers. The barrier detection time is shown to scale linearly in terms of the number of active barriers in the system. Comparisons to Wired-NOR hardware and Shared-Lock software approaches indicate reduced barrier detection time, decreased inter-PE wiring requirements, and increased functionality. Suitability of adaptation of the DSBC method to a skew-insensitive clockless design is also discussed.

실시간 검색을 위한 다중 사용자용 주기억장치 자료저장 시스템 개발

주기억장치 자료저장 시스템은 실시간 트랜젝션에 충분한 여유 시간을 부여하여 실시간 트랜잭션의 성능을 높혀준다. 이런 특성으로 인하여 주기억장치를 이용한 데이터관리 시스템들이 이동 통신 관리 시스템의 가입자 위치 관리와 같은 여유시간의 급박한 실시간 트랜잭션에 많이 활용되고 있다. 본 논문에서는 다중 사용자용 멀티쓰레드 방식의 실시간 검색시스템 개발의 일환으로 대량의 실시간 검색 트랜잭션과 자료 변경 트랜잭션이 주기억장치 자료저장 시스템의 자료를 검색, 변경하는 환경에서 주기억장치 자료저장 시스템을 설계 구현하였다. 구현된 시스템은 기존의 디스크 데이터베이스 시스템과 상호 보완적인 형태로 사용되는 내장형 방식으로 다중 쓰레드 방식으로 동작되며, 동시성 제어는 주기억장치의 특성을 살려 복잡한 잠금방식이 아닌 래치를 사용한다. 주기억장치 자료저장 시스템에는 가장 최근의 데이터만을 저장하며, 동기화 기법으로는 디스크 데이터베이스 시스템에서 변경 트랜잭션이 발생하는 경우에 구현 시스템의 데이터를 갱신하는 방법을 사용한다. 시스템은 검색 및 변경 쓰레드의 비율을 제한하여 실시간 검색의 최소성능을 보장할 수 있게 하였다. Main Memory storage system can increase the performance of the system by assigning enough slack time to real-time transactions. Due to its high response time of main memory devices, main memory resident data management systems have been used for location management of personal mobile clients to cope with urgent location related operations. In this paper we have developed a multi-threaded main memory storage system as a core component of real-time retrieval system to handle a huge amount of readers and writers of main memory resident data. The storage system is implemented as an embedded component which is working with the help of a disk resident database system. It uses multi-threaded executions and utilizes latches for its concurrency control rather than complex locking method. It only saves most recent data on main memory and data synchronization is done only when disk resident database asks for update transactions. The system controls the number of read threads and update threads to guarantee the minimum requirements of real-time retrievals.

Pentium 4 performance-monitoring features

The Intel Pentium 4's unique performance-monitoring features overcome many limitations and problems found in previous processors. Pentium 4 Xeon performance monitoring supports simultaneous multithreaded execution features.

Automatic parallelization of compiled event driven VHDL simulation

In this paper, we present approaches and algorithms for parallelization of compiled event driven VHDL simulations on shared-memory multiprocessors (SMP). An efficient single-threaded algorithm for simulation of VHDL descriptions is first presented. This algorithm is shown to be competitive with a commercial VHDL simulator. Schemes for multithreaded execution of this algorithm are then described. These have been implemented on top of the POSIX pthreads library and experimental results have been shown on a Sun SparcServer 1000E. Speedups of up to four on eight processors have been achieved for some benchmarks.

Power and energy reduction via pipeline balancing

Minimizing power dissipation is an important design requirement for both portable and non-portable systems. In this work, we propose an architectural solution to the power problem that retains performance while reducing power. The technique, known as Pipeline Balancing (PLB), dynamically tunes the resources of a general purpose processor to the needs of the program by monitoring performance within each program. We analyze metrics for triggering PLB, and detail instruction queue design and energy savings based on an extension of the Alpha 21264 processor. Using a detailed simulator, we present component and full chip power and energy savings for single and multi-threaded execution. Results show an issue queue and execution unit power reduction of up to 23% and 13%, respectively, with an average performance loss of 1% to 2% .

Resource Management in Dataflow-Based Multithreaded Execution

Due to the large amount of potential parallelism, resource management is a critical issue in multithreaded execution. The challenge in code generation is to control the parallelism without reducing the machine's ability to exploit it. Controlled parallelism reduces idle time, communication, and delay caused by synchronization. At the same time it increases the potential for exploitation of program data structure locality. In this paper, we evaluate the performance of methods to control program parallelism and resource usage in the context of the fine-grain dataflow execution model. The methods are in themselves not new, but their performance analysis is. The two methods to control parallelism here are slicing and chunking. We present the methods and their compilation strategy and evaluate their effectiveness in terms of run time and matching store occupancy. Communication is categorized in memory, loop, call, and expression communication. Input and output message locality is measured. Two techniques to reduce communication are introduced. Grouping allocates loop and function bodies on one processor and bundling combines messages with the same sender and receiver into one. Their effects on the total communication volume are quantified.

A multithreaded parallel implementation of a dynamic programming algorithm for sequence comparison.

This paper discusses the issues involved in implementing a dynamic programming algorithm for biological sequence comparison on a general-purpose parallel computing platform based on a fine-grain event-driven multithreaded program execution model. Fine-grain multithreading permits efficient parallelism exploitation in this application both by taking advantage of asynchronous point-to-point synchronizations and communication with low overheads and by effectively tolerating latency through the overlapping of computation and communication. We have implemented our scheme on EARTH, a fine-grain event-driven multithreaded execution and architecture model which has been ported to a number of parallel machines with off-the-shelf processors. Our experimental results show that the dynamic programming algorithm can be efficiently implemented on EARTH systems with high performance (e.g., speedup of 90 on 120 nodes), good programmability and reasonable cost.

A combined compiler and architecture technique to control multithreaded execution of branches and loop iterations

Simultaneous Speculation Scheduling ( S 3 ) is a combined compiler and architecture technique to control multiple path execution. It can be used for dual path branch speculation in case of unpredictable branches and for multiple path speculative execution of loop iterations in case of loop-carried dependences that make parallel execution otherwise impossible. We apply S 3 In situations where purely static techniques cannot prove data independence. S 3 can be seen as a cost-effective alternative to purely dynamic speculation techniques. We explain the S 3 technique and discuss the requirements on possible target architectures. We further compare S 3 to other speculation techniques.

Dispo: Distributed Multi-Threaded Execution of Prolog Programs

DISPO is a distributed prolog virtual machine for interpreting and executing Prolog programs through distribution and multi-threading. It is a distributed version of a standard Prolog interpreter designed for exploiting OR-parallelism and pipe-lined AND parallelism. Some distinctive features of DISPO are that it speeds up the execution of Prolog programs and generates all possible solutions for a query, that is to say, it works as an all-solutions Prolog virtual machine. The effectiveness of its distribution technique and load balancing equations resulted in a 70% average speed-up in the execution time of a number of Prolog benchmark programs. These results are presented graphically with a detailed analysis of system performance.