Multithreaded Execution Research Articles

SFA-SPA: a suffix array based short peptide assembler for metagenomic data.

The determination of protein sequences from a metagenomic dataset enables the study of metabolism and functional roles of the organisms that are present in the sampled microbial community. We had previously introduced algorithm and software for the accurate reconstruction of protein sequences from short peptides identified on nucleotide reads in a metagenomic dataset. Here, we present significant computational improvements to the short peptide assembly algorithm that make it practical to reconstruct proteins from large metagenomic datasets containing several hundred million reads, while maintaining accuracy. The improved computational efficiency is achieved using a suffix array data structure that allows for fast querying during the assembly process, and a significant redesign of assembly steps that enables multi-threaded execution. The program is available under the GPLv3 license from sourceforge.net/projects/spa-assembler.

The Design of Heterogeneous Network Integration Gateway System Based on Multi-Threaded

This paper mainly describes an iot gateway which has broad access capability of making the integrated communications among heterogeneous networks to be possible.The capability described above can set up multi-threaded execution,so that it can read,segment,extract,recombine,establish Socket and transmit the data which are collected by heterogeneous WSN to the serve through the way of the UDP transport protocol.And then realizing the perception of heterogeneous sensor network data terminal broad access, integration, processing, transmission, and finally realizing the perception network and transmission network connectivity.This paper will use this experimental method to show the final fusion of Intelligent transportation project in the induction system and the parking system.

Automation Highlights from the Literature

Automation Highlights from the Literature

Comparison of Numerically Stable Methods for Implementation of a Double Porosity Model with First-Order Reaction Terms

The influence of barometric cycling on gas transport through complex media can be described using a double porosity model. Here vertical channels simulate the effect of cracks that pass through homogeneous regions of media. The cracks are coupled to the atmosphere and act as boundaries for the sections of homogeneous media. Convection–diffusion models are then used to simulate gas transport through the coupled system. This approach has been used to model soil aeration, subsurface movement of volatile compounds, and the migration of gases to the surface after below ground nuclear detonations. In the present work, we describe four stable numerical methods that can be used to implement the double porosity model when first-order reactions produce and consume the gaseous species of interest. We find that all four methods satisfy analytical crosschecks and agree to at least seven digits of precision. An iterative solver based on Newton’s method is found to be optimal as it is easily scalable to 3-D models and to multithreaded execution.

Large-scale automated image analysis for computational profiling of brain tissue surrounding implanted neuroprosthetic devices using Python.

In this article, we describe the use of Python for large-scale automated server-based bio-image analysis in FARSIGHT, a free and open-source toolkit of image analysis methods for quantitative studies of complex and dynamic tissue microenvironments imaged by modern optical microscopes, including confocal, multi-spectral, multi-photon, and time-lapse systems. The core FARSIGHT modules for image segmentation, feature extraction, tracking, and machine learning are written in C++, leveraging widely used libraries including ITK, VTK, Boost, and Qt. For solving complex image analysis tasks, these modules must be combined into scripts using Python. As a concrete example, we consider the problem of analyzing 3-D multi-spectral images of brain tissue surrounding implanted neuroprosthetic devices, acquired using high-throughput multi-spectral spinning disk step-and-repeat confocal microscopy. The resulting images typically contain 5 fluorescent channels. Each channel consists of 6000 × 10,000 × 500 voxels with 16 bits/voxel, implying image sizes exceeding 250 GB. These images must be mosaicked, pre-processed to overcome imaging artifacts, and segmented to enable cellular-scale feature extraction. The features are used to identify cell types, and perform large-scale analysis for identifying spatial distributions of specific cell types relative to the device. Python was used to build a server-based script (Dell 910 PowerEdge servers with 4 sockets/server with 10 cores each, 2 threads per core and 1TB of RAM running on Red Hat Enterprise Linux linked to a RAID 5 SAN) capable of routinely handling image datasets at this scale and performing all these processing steps in a collaborative multi-user multi-platform environment. Our Python script enables efficient data storage and movement between computers and storage servers, logs all the processing steps, and performs full multi-threaded execution of all codes, including open and closed-source third party libraries.

Dynamic feature modelling for closed-loop machining process control of complex parts

Dynamically changing machining conditions and uncertain manufacturing resource availability are forcing manufacturing enterprises to implement advanced process planning and control systems with an adaptive machining information model in order to increase productivity and ensure product quality. This article proposes a dynamic feature modelling method for closed-loop machining process control of complex parts. A software platform is developed to include feature modelling software units with algorithms to represent and integrate geometric, machining, inspection and monitoring information and a service software unit with algorithms to update dynamic feature information and trigger online inspection. A multi-thread execution approach and a finite state machine method are adopted to support the execution and collaboration of multiple algorithms for dynamic feature modelling. A sharing memory approach is utilised for real-time communication between software units and the computer numerical control (CNC) kernel. The dynamic feature model is highly informative and can support autonomous decision-making and bidirectional information flow. By implementing the proposed dynamic feature modelling, a closed-loop process machining control including the integration of process planning, machining, inspection and monitoring for complex parts can be achieved.

Parallel Implementation of Color Based Image Retrieval Using CUDA on the GPU

Most image processing algorithms are inherently parallel, so multithreading processors are suitable in such applications. In huge image databases, image processing takes very long time for run on a single core processor because of single thread execution of algorithms. Graphical Processors Units (GPU) is more common in most image processing applications due to multithread execution of algorithms, programmability and low cost. In this paper we implement color based image retrieval system in parallel using Compute Unified Device Architecture (CUDA) programming model to run on GPU. The main goal of this research work is to parallelize the process of color based image retrieval through color moments; also whole process is much faster than normal. Our work uses extensive usage of highly multithreaded architecture of multi-cored GPU. An efficient use of shared memory is needed to optimize parallel reduction in CUDA. We evaluated the retrieval of the proposed technique using Recall, Precision, and Average Precision measures. Experimental results showed that parallel implementation led to an average speed up of 6.305×over the serial implementation when running on a NVIDIA GPU GeForce 610M. The average Precision and the average Recall of presented method are 53.84% and 55.00% respectively.

Input-covering schedules for multithreaded programs

We propose constraining multithreaded execution to small sets of input-covering schedules , which we define as follows: given a program P, we say that a set of schedules ∑ covers all inputs of program P if, when given any input, P's execution can be constrained to some schedule in ∑ and still produce a semantically valid result. Our approach is to first compute a small ∑ for a given program P, and then, at runtime, constrain P's execution to always follow some schedule in ∑, and never deviate. We have designed an algorithm that uses symbolic execution to systematically enumerate a set of input-covering schedules, ∑. To deal with programs that run for an unbounded length of time, we partition execution into bounded epochs , find input-covering schedules for each epoch in isolation, and then piece the schedules together at runtime. We have implemented this algorithm along with a constrained execution runtime for pthreads programs, and we report results Our approach has the following advantage: because all possible runtime schedules are known a priori , we can seek to validate the program by thoroughly verifying each schedule in ∑, in isolation, without needing to reason about the huge space of thread interleavings that arises due to conventional nondeterministic execution.

Efficient heterogeneous execution on large multicore and accelerator platforms: Case study using a block tridiagonal solver

The algorithmic and implementation principles are explored in gainfully exploiting GPU accelerators in conjunction with multicore processors on high-end systems with large numbers of compute nodes, and evaluated in an implementation of a scalable block tridiagonal solver. The accelerator of each compute node is exploited in combination with multicore processors of that node in performing block-level linear algebra operations in the overall, distributed solver algorithm. Optimizations incorporated include: (1) an efficient memory mapping and synchronization interface to minimize data movement, (2) multi-process sharing of the accelerator within a node to obtain balanced load with multicore processors, and (3) an automatic memory management system to efficiently utilize accelerator memory when sub-matrices spill over the limits of device memory. Results are reported from our novel implementation that uses MAGMA and CUBLAS accelerator software systems simultaneously with ACML (2013) [2] for multithreaded execution on processors. Overall, using 940 nVidia Tesla X2090 accelerators and 15,040 cores, the best heterogeneous execution delivers a 10.9-fold reduction in run time relative to an already efficient parallel multicore-only baseline implementation that is highly optimized with intra-node and inter-node concurrency and computation–communication overlap. Detailed quantitative results are presented to explain all critical runtime components contributing to hybrid performance.

Parallel Implementation of Texture Based Image Retrieval on The GPU

Most image processing algorithms are inherently parallel, so mu ltithreading processors are suitable in such applications. In huge image databases, image processing takes very long time fo r run on a single core processor because of single thread execution of algorith ms . Graphical Processors Units (GPU) is more co mmon in most image p rocessing applications due to multithread execution of algorith ms, programmab ility and low cost. In this paper we implement texture based image retrieval system in parallel using Co mpute Unified Device Architecture (CUDA) programming model to run on GPU. The main goal of this research work is to parallelize the process of texture based image retrieval through entropy, standard deviation, and local range, also whole process is much faster than normal. Our wo rk uses extensive usage of highly mu ltithreaded architecture of mu lt i-cored GPU. We evaluated the retrieval of the proposed technique using Recall, Precision, and Average Precision measures. Experimental results showed that parallel implementation led to an average speed up of 140.046×over the serial imp lementation. The average Precision and the average Recall of presented method are 39.67% and 55.00% respectively.

Limits of region-based dynamic binary parallelization

Efficiently executing sequential legacy binaries on chip multi-processors (CMPs) composed of many, small cores is one of today's most pressing problems. Single-threaded execution is a suboptimal option due to CMPs' lower single-core performance, while multi-threaded execution relies on prior parallelization, which is severely hampered by the low-level binary representation of applications compiled and optimized for a single-core target. A recent technology to address this problem is Dynamic Binary Parallelization (DBP), which creates a Virtual Execution Environment (VEE) taking advantage of the underlying multicore host to transparently parallelize the sequential binary executable. While still in its infancy, DBP has received broad interest within the research community. The combined use of DBP and thread-level speculation (TLS) has been proposed as a technique to accelerate legacy uniprocessor code on modern CMPs. In this paper, we investigate the limits of DBP and seek to gain an understanding of the factors contributing to these limits and the costs and overheads of its implementation. We have performed an extensive evaluation using a parameterizable DBP system targeting a CMP with light-weight architectural TLS support. We demonstrate that there is room for a significant reduction of up to 54% in the number of instructions on the critical paths of legacy SPEC CPU2006 benchmarks. However, we show that it is much harder to translate these savings into actual performance improvements, with a realistic hardware-supported implementation achieving a speedup of 1.09 on average.

Domain decomposition adaptivity for the Richards equation model

This paper presents a study on efficient and economical domain decomposition adaptivity for Richards equation problems. Many real world applications of the Richards equation model typically involve solving systems of linear equations of huge dimensions. Multi-thread methods are therefore often preferred in order to reduce the required computation time. Multi-thread (parallel) execution is typically achieved by domain decomposition methods. In the case of non-homogeneous materials, the problem conditioning can be significantly improved if the computational domain is split efficiently, as each subdomain can cover only a certain material set within some defined parameter range. For linear problems, e.g. heat conduction, it is very easy to split the domain in this way. A problem arises for the nonlinear Richards equation, where the values of the constitutive functions, even over a homogeneous material, can vary within several orders of magnitude, see e.g. Kuraz et al. (Appl Math Comput 2012, in press). If the Rothe method is considered for time integration, a robust algorithm will be obtained if the domain is split adaptively over the time integration levels. The domain decomposition technique considered here is the standard multiplicative Schwarz method with coarse level, see e.g. Toselli and Widlund (Domain decomposition: methods algorithms and theory, Springer, Berlin, 2005). A method of the domain decomposition adaptivity will be studied in this paper.

N-step FM-Index for Faster Pattern Matching

Fast pattern matching is a requirement for many problems, specially for bioinformatics sequence analysis like short read mapping applications. This work presents a variation of the FM-index method, denoted n-step FM-index, that is applied in exact match genome search.We propose an alternative two-dimensional FM-index structure that allows backward-search navigation giving steps of n symbols at a time. The main advantages of this arrangement are the reduction of the computational work, but most importantly, the reduction by n of the chain of dependent data accesses, and the increase in the temporal locality of the data access pattern. This benefit comes at the expense of increasing the total amount of data required for the index.We present an in-depth performance analysis of a multi-core implementation of the algorithm using large references (up to 1.5G). We identify memory latency as the major performance limiter for single-thread execution and memory bandwidth for multi-thread execution. Our proposal provides speedups ranging from 1.4× to 2.4×, when there is no limitation on DRAM capacity.We also analyse the trade-off of compacting the proposed data structure in order to reduce memory capacity requirements, now at the expense of increasing execution time. An extra 33% of DRAM space allows our proposal to improve performance by 1.2×, while doubling DRAM size enables an additional 1.5×.Our proposal of n-step algorithm provides an alternative for pseudo-random memory access algorithms to be redesigned to scale in current and future computer systems.

Optimistic parallelism based on speculative asynchronous message passing

This article proposes a new speculative multi-threading execution model for object-oriented programs. Using this model, sequential object-oriented programs are partitioned into multiple speculative object threads according to their structure and semantics by compiler and runtime system. Object threads that serve as the basic unit of the parallel target code are dynamically mapped onto thread units of the target machine. However, synchronous message passing between objects in a source program prevents parallel execution of object threads in the target code at synchronous points. By speculating the execution of message passing in object-oriented programs, we can convert synchronous message passing into speculative asynchronous message passing. This enables us to decrease synchronization overhead in runtime and to exploit greater parallelism for such programs. The runtime system verifies speculative asynchronous message passing by comparing it with non-speculative synchronous message passing so that parallel execution remains predictable and deterministic. This model was implemented as a prototype system, Rope, for evaluation. Experiments with a Java version of the Olden benchmark suite showed that the proposed model exhibits excellent accelerating effects for object-oriented programs.

A Distributed Run-Time Environment for the Kalray MPPA®-256 Integrated Manycore Processor

The Kalray MPPA®-256 is a single-chip manycore processor that integrates 256 user cores and 32 system cores in 28nm CMOS technology. These cores are distributed across 16 compute clusters of 16+1 cores, and 4 quad-core I/O subsystems. Each compute cluster and I/O subsystem owns a private address space, while communication and synchronization between them is ensured by data and control Networks-on-Chip (NoC). This processor targets embedded applications whose program- ming models fall within the following classes: Kahn Process Networks (KPN), as motivated by media processing; single program multiple data (SPMD), traditionally used for numerical kernels; and time-triggered control systems.We describe a run-time environment that supports these classes of programming models and their composition. This environment combines classic POSIX single-process multi-threaded execution inside the compute clusters and I/O subsystems, with a set of specific Inter-Process Communication (IPC) primitives that exploit the NoC architecture. We combine these primitives in order to provide the run-time support for the different target programming models. Interestingly enough, all these NoC-specific IPC primitives can be mapped to a subset of the classic synchronous and asynchronous POSIX file descriptor operations. This design thus extends the canonical ‘pipe-and-filters’ software component model, where POSIX processes are the atomic components, and IPC instances are the connectors.

Graphs for Mining-Based Defect Localization in Multithreaded Programs

Trends in modern multicore architecture design requires software developers to develop and debug multithreaded programs. Consequently, software developers must face new challenges because of bug patterns occurring at runtime and due to the non-deterministic behavior of multi-threaded program executions. This calls for new defect-localization techniques. There has been much work in the field of defect localization for sequential programs on the one side and on the localization of specific multithreading bugs on the other side, but we are not aware of any general technique for multithreaded programs. This paper proposes such an approach. It generalizes data mining-based defect-localization techniques for sequential programs. The techniques work by analyzing call graphs. More specifically, we propose new graph representations of multithreaded program executions as well as two mining-based localization approaches based on these representations. Our evaluation shows that our technique yields good results and is able to find defects that other approaches cannot localize.

Execution privatization for scheduler-oblivious concurrent programs

Making multithreaded execution less non-deterministic is a promising solution to address the difficulty of concurrent programming plagued by the non-deterministic thread scheduling. In fact, a vast category of concurrent programs are scheduler-oblivious: their execution is deterministic, regardless of the scheduling behavior. We present and formally prove a fundamental observation of the privatizability property for scheduler-oblivious programs, that paves the theoretical foundation for privatizing shared data accesses on a path segment. With privatization, the non-deterministic thread interleavings on the privatized accesses are isolated and as the consequence many concurrency problems are alleviated. We further present a path and context sensitive privatization algorithm that safely privatizes the program without introducing any additional program behavior. Our evaluation results show that the privatization opportunity pervasively exists in real world large complex concurrent systems. Through privatization, several real concurrency bugs are fixed and notable performance improvements are also achieved on benchmarks.

Mixed speculative multithreaded execution models

The current trend toward multicore architectures has placed great pressure on programmers and compilers to generate thread-parallel programs. Improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), but, instead, via multithreaded execution. One notable technique that facilitates the extraction of parallel threads from sequential applications is thread-level speculation (TLS). This technique allows programmers/compilers to generate threads without checking for inter-thread data and control dependences, which are then transparently enforced by the hardware. Most prior work on TLS has concentrated on thread selection and mechanisms to efficiently support the main TLS operations, such as squashes, data versioning, and commits. This article seeks to enhance TLS functionality by combining it with other speculative multithreaded execution models. The main idea is that TLS already requires extensive hardware support, which when slightly augmented can accommodate other speculative multithreaded techniques. Recognizing that for different applications, or even program phases, the application bottlenecks may be different, it is reasonable to assume that the more versatile a system is, the more efficiently it will be able to execute the given program. Toward this direction, we first show that mixed execution models that combine TLS with Helper Threads (HT), RunAhead execution (RA) and MultiPath execution (MP) perform better than any of the models alone. Based on a simple model that we propose, we show that benefits come from being able to extract additional ILP without harming the TLP extracted by TLS. We then show that by combining all the execution models in a unified one that combines all these speculative multithreaded models, ILP can be further enhanced with only minimal additional cost in hardware.

Background optimization in full system binary translation

Binary translation and dynamic optimization are widely used to provide compatibility between legacy and promising upcoming architectures on the level of executable binary codes. Dynamic optimization is one of the key contributors to dynamic binary translation system performance. At the same time it can be a major source of overhead, both in terms of CPU cycles and whole system latency, as long as optimization time is included in the execution time of the application under translation. One of the solutions that allow to eliminate dynamic optimization overhead is to perform optimization simultaneously with the execution, in a separate thread. In the paper we present implementation of this technique in full system dynamic binary translator. For this purpose, an infrastructure for multithreaded execution was implemented in binary translation system. This allowed running dynamic optimization in a separate thread independently of and concurrently with the main thread of execution of binary codes under translation. Depending on the computational resources available, this is achieved whether by interleaving the two threads on a single processor core or by moving optimization thread to an underutilized processor core. In the first case the latency introduced to the system by a computational intensive dynamic optimization is reduced. In the second case overlapping of execution and optimization threads also results in elimination of optimization time from the total execution time of original binary codes.

Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors

Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the latency and high demand of the on-chip network and the off-chip memory communication. One of the main trade-offs when searching an optimal cache hierarchy is the sharing degree of cache space and its on-die distribution. Several techniques have appeared recently that optimize these parameters to get a better performance. This work provides some insight in the most promising configurations for tiled microarchitectures and shows the advantages and limitations of each of them in terms of performance and energy efficiency. This paper extends previous works by providing a complete study that evaluates different network topologies, single and multithreaded benchmarks, and single and multiprogrammed execution. In all these studies, the Distributed Cooperative Caching shows to be a promising alternative to traditional configurations for chip multiprocessors, providing a scalable and energy efficient solution.