Multithreaded Execution Research Articles

Symmetry-free routing and spectrum assignment: a universal algorithm based on first-fit

First-fit (FF) is a well-known and widely deployed algorithm for spectrum assignment (SA), but until our recent study [J. Opt. Commun. Netw. 14, 165 (2022)JOCNBB1943-062010.1364/JOCN.445492], investigations of the algorithm had been experimental in nature and no formal properties of the algorithm with respect to SA were known. In this work, we make two contributions. First, we show that FF is a universal algorithm for the SA problem in the sense that, for any variant, 1) it can be used to construct solutions equivalent to, or better than, any solution obtained by any other algorithm, and 2) it can construct an optimal solution. This universality property applies to both the min-max and min-frag objectives and to variants of the SA problem with or without guard band constraints. Consequently, the spectrum symmetry-free model of our recent study [J. Opt. Commun. Netw. 14, 165 (2022)JOCNBB1943-062010.1364/JOCN.445492] extends to all known SA variants, which therefore reduce to permutation problems. Second, we extend the spectrum symmetry-free model to the routing and spectrum assignment (RSA) problem in general topologies. This model allows for the design of more efficient algorithms as it eliminates from consideration an exponential number of equivalent symmetric solutions. By sidestepping symmetry, the RSA solution space is naturally and optimally decomposed into a routing space and a connection permutation space. Building upon this property, we introduce a two-parameter, symmetry-free universal algorithm that can be used to tackle any RSA variant in a uniform manner. The algorithm is amenable to multi-threaded execution to speed up the search process, and the value of the parameters can be adjusted to strike a balance between running time and solution quality. Our evaluation provides insight into the relative benefits of path diversity (which determines the size of the routing space) and connection diversity (which determines the size of the permutation space).

Accurate and efficient constrained molecular dynamics of polymers using Newton's method and special purpose code

In molecular dynamics simulations we can often increase the time step by imposing constraints on bond lengths and bond angles. This allows us to extend the length of the time interval and therefore the range of physical phenomena that we can afford to simulate. We examine the existing algorithms and software for solving nonlinear constraint equations in parallel and we explain why it is necessary to advance the state-of-the-art. We present ILVES-PC, a new algorithm for imposing bond constraints on proteins accurately and efficiently. It solves the same system of differential algebraic equations as the celebrated SHAKE algorithm, but ILVES-PC solves the nonlinear constraint equations using Newton's method rather than the nonlinear Gauss-Seidel method. Moreover, ILVES-PC solves the necessary linear systems using a specialized linear solver that exploits the structure of the protein. ILVES-PC can rapidly solve constraint equations as accurately as the hardware will allow. The run-time of ILVES-PC is proportional to the number of constraints. We have integrated ILVES-PC into GROMACS and simulated proteins of different sizes. Compared with SHAKE, we have achieved speedups of up to 4.9× in single-threaded executions and up to 76× in shared-memory multi-threaded executions. Moreover, ILVES-PC is more accurate than P-LINCS algorithm. Our work is a proof-of-concept of the utility of software designed specifically for the simulation of polymers.

Leveraging HPC resources with distributed RDataFrame

The declarative approach to data analysis provides high-level abstractions for users to operate on their datasets in a much more ergonomic fashion compared to imperative interfaces. ROOT offers such a tool with RDataFrame, which has been tested in production environments and used in real-world analyses with optimal results. Its programming model acts by creating a computation graph with the operations issued by the user and executing it lazily only when the final results are queried. It has always been oriented towards parallelisation, with native support for multi-thread execution on a single machine. Recently, RDataFrame has been extended with a Python layer that is capable of steering and executing the RDataFrame computation graph over a set of distributed resources. In addition, such a layer requires minimal code changes for an RDataFrame application to run distributedly. The new tool effectively allows running a C++ event loop based on RDataFrame while leveraging common industry tools like Dask to schedule the usage of resources. This work presents results and insights gathered through the distributed RDataFrame tool running a physics analysis connecting multiple nodes with a Dask scheduler that requests resources from a Slurm cluster.

Key4hep Software Stack for Detector Studies

Detector optimisation and physics performance studies are an integral part of the development of future collider experiments. The Key4hep project aims to design a common set of software tools for future, or even present, High Energy Physics projects. Based on the iLCSoft and FCCSW frameworks an integrated solution for detector simulation, reconstruction and analyses is being developed. This presentation will give a short overview of the major ingredients of the Key4hep turnkey software; the common event datamodel – EDM4hep, the Gaudi based event processing framework, some dedicated packages developed on top of these, and the use of the Spack package manager, which enables installations on a variety of platforms. A first example highlights the synergies that were already achieved by the collaboration of the different collider communities (CEPC, CLIC, FCC, ILC). It shows the seamless integration of fast simulation with Delphes and the LCFIplus vertexing processor from iLCSoft. This combination is possible due to EDM4hep, the processor wrapper (k4MarlinWrapper), and the k4SimDelphes framework integration in Key4hep. As a second example, the multi-threaded execution of the iLCSoft processors in the Gaudi framework making use of the k4MarlinWrapper will be showcased. The third example will demonstrate the execution of a multi-threaded simulation of a drift chamber in the CEPC experiment. The chosen application will take information of primary ionizations generated by an incident charged particle as input and will create the waveform as the final output, which represents the signal collected by the chamber’s signal wire. The simulation algorithm is based on a neural network model which can be used to simulate the effects from the ionization electron’s drift and avalanches. Using these examples we review some of the challenges and issues that we encountered as well as how they were addressed in the end. We close with a brief discussion of the next steps for the Key4hep project.

Programming parallel dense matrix factorizations and inversion for new-generation NUMA architectures

We propose a methodology to address the programmability issues derived from the emergence of new-generation shared-memory NUMA architectures. For this purpose, we employ dense matrix factorizations and matrix inversion (DMFI) as a use case, and we target two modern architectures (AMD Rome and Huawei Kunpeng 920) that exhibit configurable NUMA topologies. Our methodology pursues performance portability across different NUMA configurations by proposing multi-domain implementations for DMFI plus a hybrid task- and loop-level parallelization that configures multi-threaded executions to fix core-to-data binding, exploiting locality at the expense of minor code modifications. In addition, we introduce a generalization of the multi-domain implementations for DMFI that offers support for virtually any NUMA topology in present and future architectures.Our experimentation on the two target architectures for three representative dense linear algebra operations validates the proposal, reveals insights on the necessity of adapting both the codes and their execution to improve data access locality, and reports performance across architectures and inter- and intra-socket NUMA configurations competitive with state-of-the-art message-passing implementations, maintaining the ease of development usually associated with shared-memory programming.

FragGeneScanRs: faster gene prediction for short reads

BackgroundFragGeneScan is currently the most accurate and popular tool for gene prediction in short and error-prone reads, but its execution speed is insufficient for use on larger data sets. The parallelization which should have addressed this is inefficient. Its alternative implementation FragGeneScan+ is faster, but introduced a number of bugs related to memory management, race conditions and even output accuracy.ResultsThis paper introduces FragGeneScanRs, a faster Rust implementation of the FragGeneScan gene prediction model. Its command line interface is backward compatible and adds extra features for more flexible usage. Its output is equivalent to the original FragGeneScan implementation.ConclusionsCompared to the current C implementation, shotgun metagenomic reads are processed up to 22 times faster using a single thread, with better scaling for multithreaded execution. The Rust code of FragGeneScanRs is freely available from GitHub under the GPL-3.0 license with instructions for installation, usage and other documentation (https://github.com/unipept/FragGeneScanRs).

ИСПОЛЬЗОВАНИЕ ГЕТЕРОГЕННЫХ ВЫЧИСЛИТЕЛЬНЫХ УЗЛОВ В ГРИД-СИСТЕМАХ ПРИ РЕШЕНИИ КОМБИНАТОРНЫХ ЗАДАЧ

The main goal of this work is to create a parallel application that performs computationsusing a multithreaded execution model, optimized to make the best utilization of all availablehardware resources. One of the main implementation requirements is to optimize application performanceon different computer architectures, and to enable parallel execution of the applicationon various computing devices that are part of a heterogeneous computing system. The possibilityof applying various methods of software and algorithmic optimization on multiprocessor architecturesof different generations was investigated as well as the effectiveness of their use for highlyloaded multithreaded applications was estimated. The problem of quasi-optimal dynamic distributionof computational tasks among all currently available computing devices of a heterogeneouscomputing system was also solved. Currently, not only multiprocessor computing systems are usedto solve large computational problems, but also various types of distributed systems. Distributedcomputing systems have a number of features: possible failures of nodes and communicationchannels, unstable operating time of nodes, possible errors in calculations, heterogeneity of computingnodes. By heterogeneity of computing nodes, we will understand not only the different computingcapacity and different architectures of central processors, but also the presence of otherdevices on the node capable of performing calculations. Such devices include video cards andmathematical coprocessors. A node of a distributed computing system will be called heterogeneousif, in addition to one or more central processing units, it contains additional computing devices.When solving a computational problem on a distributed system, it is necessary to maximize theutilization of all available computing resources. To do this, it is necessary not only to distributecomputing subtasks to nodes in accordance with their computing capacity, but also to take intoaccount the features of additional computing devices. This work is devoted to the study of methodsfor maximizing the resources utilization of heterogeneous nodes.

Empirical Analysis Measuring the Performance of Multi-threading in Parallel Merge Sort

Sorting is one of the most frequent concerns in Computer Science, various sorting algorithms were invented for specific requirements. As these requirements and capabilities grow, sequential processing becomes inefficient. Therefore, algorithms are being enhanced to run in parallel to achieve better performance. Performing algorithms in parallel differ depending on the degree of multi-threading. This study determines the optimal number of threads to use in parallel merge sort. Furthermore, it provides a comparative analysis of various degrees of multithreading. The implementation in this empirical experiment takes a group of devices with various specifications. For each device, it takes fixed-sized data set and executes merge sort for sequential and parallel algorithms. For each device, the lowest average runtime is used to measure the efficiency of the experiment. In all experiments, single-threaded is more efficient when the data size is less than 105 since it claimed 53% of the lowest runtime than the multithreaded executions. The overall average of the experiments shows either four or eight threads, with 72% and 28%, respectively, are most efficient when data sizes exceed 105.

ParallelGlobal with Low Thread Interactions

Global is an optimization algorithm conceived in the ’80s. Since then several papers discussed improvements of the algorithm, but adapting it to a multi-thread execution environment is only a recent branch of development [1]. Our previous work focused on parallel implementation on a single machine but sometimes the use of distributed systems is inevitable. In this paper we introduce a new version of Global which is the first step towards a fully distributed algorithm. While the proposed implementation still works on a single machine, it is easy to see how gossip based information sharing can be built into and be utilized by the algorithm. We show that ParallelGlobal is a feasible way to implement Global on a distributed system. However, further improvements must be made to solve real world problems with the algorithm.

Fast Key-Value Lookups with Node Tracker

Lookup operations for in-memory databases are heavily memory bound, because they often rely on pointer-chasing linked data structure traversals. They also have many branches that are hard-to-predict due to random key lookups. In this study, we show that although cache misses are the primary bottleneck for these applications, without a method for eliminating the branch mispredictions only a small fraction of the performance benefit is achieved through prefetching alone. We propose the Node Tracker (NT), a novel programmable prefetcher/pre-execution unit that is highly effective in exploiting inter key-lookup parallelism to improve single-thread performance. We extend NT with branch outcome streaming (BOS) to reduce branch mispredictions and show that this achieves an extra 3× speedup. Finally, we evaluate the NT as a pre-execution unit and demonstrate that we can further improve the performance in both single- and multi-threaded execution modes. Our results show that, on average, NT improves single-thread performance by 4.1× when used as a prefetcher; 11.9× as a prefetcher with BOS; 14.9× as a pre-execution unit and 18.8× as a pre-execution unit with BOS. Finally, with 24 cores of the latter version, we achieve a speedup of 203× and 11× over the single-core and 24-core baselines, respectively.

A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor

A Qualcomm® Hexagon™ compute digital signal processor (CDSP) enhances reliability by integrating a current and temperature limiting system to avoid circuit failures from operating at excessive current levels for a sustained duration or from thermal runaway. The current and temperature limiting system consists of on-die current and temperature sensors, a limits evaluation (LE) circuit, and a randomized pulse modulation (RPM) circuit to control the instruction-issue rate. After the on-die sensors detect current or temperature exceeding a target threshold, the RPM circuit precisely adjusts the instruction-issue rate to maximize the performance while operating below the current and temperature specifications. The RPM circuit adapts performance in approximately five CDSP clock cycles after accounting for the clock-domain-crossing synchronization overhead to satisfy the 1- $\mu \text{s}$ latency requirement for the entire limiting system. From silicon measurements in a 7-nm CDSP, the RPM instruction-issue control circuit enables a 0.4% performance resolution across a wide range of operation from 100% to 0.4%. In addition, the RPM circuit avoids thread starvation during multi-threaded execution to maintain the CDSP quality of service (QoS). In comparison to a clock control for a limiting system, the RPM instruction-issue control enables CDSP performance gains ranging from ~2% to ~50%, depending on the workload and adjustment level, while satisfying the current and temperature specifications.

Detection of Concurrency Errors in Multithreaded Applications Based on Static Source Code Analysis

Computer systems that allow multithreaded execution of applications have become extremely common, even small portable devices operate in multithreaded mode. This is undoubtedly very convenient for users, but for programmers it is associated with many unwanted errors, which can occur after writing application code. These errors include race condition, deadlock, atomicity violation and order violation. The subject of this work is related to the detection of these errors in the process of static software analysis. The paper presents the author’s model, which was then used to detect the above-mentioned occurrences, additionally each error has been discussed in detail. A tool supporting the detection of errors in multithreaded applications was also developed and the results of this tool were presented.

Ontology Fixing by Using Software Engineering Technology

This paper presents OntologyFixer, a web-based tool that supports a methodology to build, assess, and improve the quality of ontology web language (OWL) ontologies. Using our software, knowledge engineers are able to fix low-quality OWL ontologies (such as those created from natural language documents using ontology learning processes). The fixing process is guided by a set of metrics and fixing mechanisms provided by the tool, and executed primarily through automated changes (inspired by quick fix actions used in the software engineering domain). To evaluate the quality, the tool supports numerical and graphical quality assessments, focusing on ontology content and structure attributes. This tool follows principles, and provides features, typical of scientific software, including user parameter requests, logging, multithreading execution, and experiment repeatability, among others. OntologyFixer architecture takes advantage of model view controller (MVC), strategy, template, and factory design patterns; and decouples graphical user interfaces (GUI) from ontology quality metrics, ontology fixing, and REST (REpresentational State Transfer) API (Application Programming Interface) components (used for pitfall identification, and ontology evaluation). We also separate part of the OntologyFixer functionality into a new package called OntoMetrics, which focuses on the identification of symptoms and the evaluation of the quality of ontologies. Finally, OntologyFixer provides mechanisms to easily develop and integrate new quick fix methods.

Tell You a Definite Answer: Whether Your Data is Tainted During Thread Scheduling

With the advent of multicore processors, there is a great need to write parallel programs to take advantage of parallel computing resources. However, due to the nondeterminism of parallel execution, the malware behaviors sensitive to thread scheduling are extremely difficult to detect. Dynamic taint analysis is widely used in security problems. By serializing a multithreaded execution and then propagating taint tags along the serialized schedule, existing dynamic taint analysis techniques lead to under-tainting with respect to other possible interleavings under the same input. In this paper, we propose an approach called DSTAM that integrates symbolic analysis and guided execution to systematically detect tainted instances on all possible executions under a given input. Symbolic analysis infers alternative interleavings of an executed trace that cover new tainted instances, and computes thread schedules that guide future executions. Guided execution explores new execution traces that drive future symbolic analysis. We have implemented a prototype as part of an educational tool that teaches secure C programming, where accuracy is more critical than efficiency. To the best of our knowledge, DSTAM is the first algorithm that addresses the challenge of taint analysis for multithreaded program under fixed inputs.

A Fast and Simple Method for Detecting Identity-by-Descent Segments in Large-Scale Data

Segments of identity by descent (IBD) are used in many genetic analyses. We present a method for detecting identical-by-descent haplotype segments in phased genotype data. Our method, called hap-IBD, combines a compressed representation of haplotype data, the positional Burrows-Wheeler transform, and multi-threaded execution to produce very fastanalysis times. An attractive feature of hap-IBD is its simplicity: the input parameters clearly and precisely define the IBD segments that are reported, so that program correctness can be confirmed by users. We evaluate hap-IBD and four state-of-the-art IBD segment detection methods (GERMLINE, iLASH, RaPID, and TRUFFLE) using UK Biobank chromosome 20 data and simulated sequence data. We show that hap-IBD detects IBD segments faster and more accurately than competing methods, and that hap-IBD is the only method that can rapidly and accurately detect short 2-4 centiMorgan (cM) IBD segments in the full UK Biobank data. Analysis of 485,346UKBiobank samples through the use of hap-IBD with 12 computational threads detects 231.5 billion autosomal IBD segments with length ≥2 cM in 24.4 h.

Exploring Prefetching, Pre-Execution and Branch Outcome Streaming for In-Memory Database Lookups

Lookup operations for in-memory databases are heavily memory-bound because they often rely on pointer-chasing linked data structure traversals. They are also branch heavy with branches that are hard-to-predict due to random key lookups. In this study, we show that although cache misses are the primary bottleneck for these applications, without a method for eliminating the branch mispredictions, only a small fraction of the performance benefit is achieved through prefetching. We propose the Node Tracker (NT), a novel programmable prefetcher/pre-execution unit that is highly effective in exploiting inter key-lookup parallelism to improve single-thread performance. We extend the NT with branch outcome streaming (BOS) to reduce branch mispredictions and show that NT with BOS can achieve an extra 3x speedup. Finally, we evaluated the NT as a pre-execution unit and show that we can further improve the performance in both single- and multi-threaded execution modes.

Evaluation of Classical Machine Learning Techniques towards Urban Sound Recognition on Embedded Systems

Automatic urban sound classification is a desirable capability for urban monitoring systems, allowing real-time monitoring of urban environments and recognition of events. Current embedded systems provide enough computational power to perform real-time urban audio recognition. Using such devices for the edge computation when acting as nodes of Wireless Sensor Networks (WSN) drastically alleviates the required bandwidth consumption. In this paper, we evaluate classical Machine Learning (ML) techniques for urban sound classification on embedded devices with respect to accuracy and execution time. This evaluation provides a real estimation of what can be expected when performing urban sound classification on such constrained devices. In addition, a cascade approach is also proposed to combine ML techniques by exploiting embedded characteristics such as pipeline or multi-thread execution present in current embedded devices. The accuracy of this approach is similar to the traditional solutions, but provides in addition more flexibility to prioritize accuracy or timing.

Mahtab: Phase-wise acceleration of regression testing for C

Software regression testing consists of offline, online, and execution phases which are executed sequentially. The offline phase involves code instrumentation and test-coverage collection. Subsequently, the online phase performs program differencing, test-suite selection and prioritization. Finally, the selected test-cases are executed against the new version of software for its re-validation. Regression testing is a time-consuming process and is often on the critical path of the project. To improve the turn-around time of software development cycle, our goal is to reduce regression testing time across all phases using multi-core parallelization. This poses several challenges that stem from I/O, dependence on third-party libraries, and inherently sequential components in the overall testing process. We propose parallelization test-windows to effectively partition test-cases across threads. To measure the benefit of prioritization coupled with multi-threaded execution, we propose a new metric, EPSilon, for rewarding failure observation frequency in the timeline of test-execution. To measure the rate of code-change coverage due to regression test prioritization, we introduce ECC, a variant of the widely used APFD metric. We illustrate the effectiveness of our approach using the popular Software-artifact Infrastructure Repository (SIR) and five real-world projects from GitHub.

RedScarf: an open-source multi-platform simulation environment for performance evaluation of Networks-on-Chip

Abstract The design space of Networks-on-Chip (NoCs) comprises a large number of architectural parameters. To comply with the performance requirements of target applications, NoC-based system designers need to employ tools to assess the impact of each parameter on the NoC and the performance of the application. In view of this, this paper presents a simulation environment named RedScarf, which was developed to facilitate the design space exploration of NoCs. RedScarf integrates a graphical user interface and a set of tools that automate the process of configuring and evaluating the network characteristics. By providing resources like multi-platform and multi-thread execution, among others, RedScarf is a powerful tool for Research and Education on NoCs. This work describes the RedScarf architecture and tools, and demonstrates by means of experiments how it can aid a designer in the task of assessing the performance of on-chip interconnect architectures.

GPU Accelerated PIC and SIC for OFDM-NOMA

Non-orthogonal multiple access (NOMA) is a candidate multiple access scheme for the fifth-generation (5G) cellular networks. In NOMA systems, all users operate at the same frequency and time, which poses a challenge in the decoding process at the receiver side. In this work, the two most popular receiver structures, successive interference cancellation (SIC) and parallel interference cancellation (PIC) receivers, for NOMA reverse channel are implemented on a graphics processing unit (GPU) and compared. Orthogonal frequency division multiplexing (OFDM) is considered. The high computational complexity of interference cancellation receivers undermines the potential deployment of NOMA systems. GPU acceleration, however, challenges this weakness, and our numerical results show speedups of about from 75–220-times as compared to a multi-thread implementation on a central processing unit (CPU). SIC and PIC multi-thread execution time on different platforms reveals the potential of GPU in wireless communications. Furthermore, the successful decoding rates of the SIC and PIC are evaluated and compared in terms of bit error rate.