Multilevel Nonvolatile Memory Research Articles

An organic multilevel non-volatile memory device based on multiple independent switching modes

The demand for higher data density memory structures is greater today than ever before. Multilevel resistive organic memory devices (OMD) provide an ideal solution, in being easily fabricated, cost-effective and at the same time promising high storage capacity. However, conventional methods for multilevel OMDs impose demanding requirements on material properties and attain only limited performance. We hereby provide an alternative design concept that combines multiple switching modes in one device to realize multilevel function. The device possesses a simple structure by using a ferroelectric phase-separated blend as the active layer. Two switching modes, the ferroelectric switching and the metallic filament switching, are realized simultaneously in this device, and enable a ternary storage function. The cross-section scanning electron microscope (SEM) images provide a strong evidence of the formation and annihilation of the metallic filament.

Resistive switching behavior in Pt/YSZ/Nb:SrTiO3 heterostructure for nonvolatile multilevel memories

The yittra-stablized zirconia (YSZ) thin film was deposited on a Nb:SrTiO3 (NSTO) substrate by pulsed laser deposition to form a Pt/YSZ/NSTO heterostructure device. This device exhibits high resistive switching ratio of 105 at a read voltage of −0.1V after applied +3V/−4V pulse voltages. Moreover, the resistance states could be reversibly switched among multilevel resistance states by changing the magnitude of Set or Reset pulse voltages, which shows potential application in multilevel nonvolatile memory devices. The RS mechanism of the device could be attributed to the modulation of YSZ/NSTO Schottky-like junction depletion, which is caused by the carrier injection-trapped/detrapped process under the applied electric field.

Adaptive Threshold Read Algorithms in Multi-Level Non-Volatile Memories

For an array of memory cells that are read by threshold measurements, we ask the question of how to choose the measurements in the read sequence to minimize the number of measurements before the array is fully read. We propose and study analytically and experimentally various adaptive read algorithms, and provide corresponding lower bounds on the average number of measurements. We show that new two-dimensional read algorithms improve over the best one-dimensional ones. We further adapt the read algorithms to the case where the cell levels are not uniformly distributed, as motivated by partially-erased memory arrays.

Multilevel recording in Bi-deficient Pt/BFO/SRO heterostructures based on ferroelectric resistive switching targeting high-density information storage in nonvolatile memories

We demonstrate the feasibility of multilevel recording in Pt/Bi1-δFeO3/SrRuO3 capacitors using the ferroelectric resistive switching phenomenon exhibited by the Pt/Bi1−δFeO3 interface. A tunable population of up and down ferroelectric domains able to modulate the Schottky barrier height at the Pt/Bi1−δFeO3 interface can be achieved by means of either a collection of SET/RESET voltages or current compliances. This programming scheme gives rise to well defined resistance states, which form the basis for a multilevel storage nonvolatile memory.

Graphene-ferroelectric hybrid devices for multi-valued memory system

We demonstrate and explain the operation of a multi-level nonvolatile memory system using dual-gated single-layer graphene field-effect transistor with a polymer ferroelectric as top-gate dielectric and a linear bottom-gate dielectric. The multiple memory states are represented by various levels of graphene channel resistance obtained by changing the doping type and the number of p−n junctions in graphene. This is achieved by controlling the polarity of the domains in the ferroelectric thin film using a biased metal-coated atomic force microscope tip. We show a five level memory with the resistance change between the lowest and highest state greater than 200%.

Dynamic Threshold Schemes for Multi-Level Non-Volatile Memories

In non-volatile memories, reading stored data is typically done through the use of predetermined fixed thresholds. However, due to problems commonly affecting such memories, including voltage drift, overwriting, and inter-cell coupling, fixed threshold usage often results in significant asymmetric errors. To combat these problems, Zhou, Jiang, and Bruck recently introduced the notion of dynamic thresholds and applied them to the reading of binary sequences. In this paper, we explore the use of dynamic thresholds for multi-level cell (MLC) memories. We provide a general scheme to compute and apply dynamic thresholds and derive performance bounds. We show that the proposed scheme compares favorably with the optimal thresholding scheme. Finally, we develop limited-magnitude error-correcting codes tailored to take advantage of dynamic thresholds.

Nonvolatile resistive switching behaviour and the mechanism in Nd:BiFeO3/Nb:SrTiO3 heterostructure

This paper reports the bipolar resistive switching (RS) effect of the Nd0.05Bi0.95FeO3/Nb:SrTiO3 heterostructure fabricated by pulsed laser deposition. This heterostructure shows a high RS ratio of over 600 at a read voltage of −0.3V after applying 5V/−8V pulse voltages. Moreover, the resistance states could be switched reversibly among multilevel resistance states by changing the magnitude of set or reset pulse voltages, which shows promise for multilevel nonvolatile memory application. The mechanism of the RS between high- and low-resistance states could be attributed to the carrier injection-trapped/detrapped process, which changes the height and thickness of the barrier at the Nd0.05Bi0.95FeO3/Nb:SrTiO3interface.

Immunity to Device Variations in a Spiking Neural Network With Memristive Nanodevices

Memristive nanodevices can feature a compact multilevel nonvolatile memory function, but are prone to device variability. We propose a novel neural network-based computing paradigm, which exploits their specific physics, and which has virtual immunity to their variability. Memristive devices are used as synapses in a spiking neural network performing unsupervised learning. They learn using a simplified and customized “spike timing dependent plasticity” rule. In the network, neurons' threshold is adjusted following a homeostasis-type rule. We perform system level simulations with an experimentally verified model of the memristive devices' behavior. They show, on the textbook case of character recognition, that performance can compare with traditional supervised networks of similar complexity. They also show that the system can retain functionality with extreme variations of various memristive devices' parameters (a relative standard dispersion of more than 50% is tolerated on all device parameters), thanks to the robustness of the scheme, its unsupervised nature, and the capability of homeostasis. Additionally the network can adjust to stimuli presented with different coding schemes, is particularly robust to read disturb effects and does not require unrealistic control on the devices' conductance. These results open the way for a novel design approach for ultraadaptive electronic systems.

Multilevel resistive switching memory with amorphous InGaZnO-based thin film

Multi-level storage capability of resistive random access memory (RRAM) using amorphous indium-gallium-zinc-oxide (InGaZnO) thin film is demonstrated by the TiN/Ti/InGaZnO/Pt device structure under different operation modes. The distinct four-level resistance states can be obtained by varying either the trigger voltage pulse or the compliance current. In addition, the RRAM devices exhibit superior characteristics of programming/erasing endurance and data retention for the application of multi-level nonvolatile memory technology. Physical transport mechanisms for the multi-level resistive switching characteristics are also deduced in this study.

Multilevel nonvolatile transistor memories using a star-shaped poly((4-diphenylamino)benzyl methacrylate) gate electret

Multilevel nonvolatile transistor memories were fabricated using star-shaped poly((4-diphenylamino)benzyl methacrylate) (star-PTPMA) electret dielectric for charge storage and N,N′-bis(2-phenylethyl)perylene-3,4,9,10-bis(dicarboximide) (BPE-PTCDI) as an n-type semiconductor. Charges were controllably stored by applying a negative voltage bias, detected by shifting the threshold voltage, and this device retained the digital states even when the supplied voltage was removed. The multilevel data storage characteristics obtained by applying different gate voltages suggested that the device possessed nonvolatile write-many-read-many (WMRM) memory behaviors. The electronic charges were transferred and permanently accumulated in the gate electret from the restricting region of the star-PTPMA with well-defined charge trapping elements, but not in the case of linear-PTPMA. P-type pentacene was also used as a semiconductor layer to clarify the operating mechanism under a gate electric field. Our results demonstrated the significance of the architecture effect of the polymer electrets for nonvolatile organic transistor memory devices and their potentials in high-density data storage. Nonvolatile transistor memories combine the functionality of transistors in microchips with memory elements that are able to store information even if the power is turned off. As such they have great promise for the construction of next-generation computers. Wen-Chang Chen from National Taiwan University and colleagues from National Central University in Taiwan and Hokkaido University in Japan have now developed an organic multilevel nonvolatile transistor memory. The transistor element of the device is constructed from a polymer and a polymer electret - a dielectric material that has a quasi permanent electric charge. In this system current is generated by a combination of an applied external voltage and the charge stored in the electret - variation of which controls the overall current. Such polymer memory devices are of particular interest for potential applications in flexible electronics. Multilevel nonvolatile transistor memories were fabricated with inserted electret dielectric of star-shaped poly((4-diphenylamino)benzyl methacrylate). The devices could be controllably charged and retain the digital states even when the supply voltage was removed. The multilevel data storage characteristics by applying different gate voltages suggested novel ‘write-many-read-many memory’ behaviors.

Improved bipolar resistive switching properties in CeO2/ZnO stacked heterostructures

This paper reports the resistive switching effects of ZnO, CeO2 and CeO2/ZnO stacked heterostructure deposited on Nb:SrTiO3 substrates by pulsed laser deposition. The CeO2/ZnO stacked heterostructure shows high resistive switching ratio of over 104 at a read voltage of −0.5 V and an expected retention ability of ten years, which is better than that of ZnO- or CeO2-based device. Furthermore, multilevel resistance states could be adjusted by changing the maximum value of the applied voltage, which shows promise for high-performance nonvolatile multilevel memory application. Studies indicated that the trap-mediated space charge limited conduction governs the low- and high-resistance states. The good resistive switching characteristics of CeO2/ZnO stacked heterostructure could be attributed to the carrier injection-trapped/detrapped process at the CeO2/ZnO interface and ZnO films in which oxygen vacancies act as ‘trapping center’.

Fabrication and mechanism of high performance bipolar resistive switching device based on SrTiO3/NiO stacked heterostructure

► SrTiO 3 /NiO stacked heterostructure was epitaxially grown by pulsed laser deposition. ► High performance bipolar resistive switching was demonstrated in the heterostructure. ► High resistive switching ratio of over 10 4 and high retention ability was obtained. ► Adjustable resistive switching shows promising for multilevel memories application. ► Excellent properties was attributed to carrier injection-trapped/detrapped process. This paper reports the bipolar resistive switching effect in a SrTiO 3 /NiO stacked heterostructure which was epitaxially deposited on an Nb doped SrTiO 3 substrate by pulsed laser deposition. This heterostructure shows high resistive switching ratio of over 10 4 at the read voltage of −0.5 V and an expected retention ability of ten years, which is better than that of NiO-based device. Moreover, the resistive switching ratio can be adjusted by changing the maximum applied voltage or compliance current, which shows promising for multilevel nonvolatile memories application. Meanwhile, these results have been discussed by carrier injection-trapped/detrapped process.

Transistors: Flexible Non‐Volatile Ferroelectric Polymer Memory with Gate‐Controlled Multilevel Operation (Adv. Mater. 44/2012)

A flexible field effect transistor with a poly(3-hexylthiophene) (P3HT) active channel and a ferroelectric poly(vinlyidene fluoride-co-trifluoro ethylene) (PVDF-TrFE) insulator exhibits gate-voltage-controllable multilevel non-volatile memory characteristics with highly reliable data retention and endurance. The operating mechanism of the device is based on multileveled non-volatile current states of a polymeric semiconductor precisely controlled by various remnant polarization states of ferroelectric polymer domains. Further details can be found in the article by Cheolmin Park and co-workers on page 5910.

Flexible Non‐Volatile Ferroelectric Polymer Memory with Gate‐Controlled Multilevel Operation

A flexible field-effect transistor with a poly(3-hexylthiophene) (P3HT) active channel and a ferroelectric poly(vinlyidene fluoride-co-trifluoro ethylene) (PVDF-TrFE) insulator exhibits gate-voltage-controllable multilevel non-volatile memory characteristics with highly reliable data retention and endurance.

Multilevel Schottky Barrier Nanowire SONOS Memory With Ambipolar n- and p-Channel Cells

A novel multilevel Schottky barrier nonvolatile nanowire memory is experimentally reported with low-voltage operations and excellent reliability. Using efficient hot-electrons and hot-holes generation associated with Schottky barrier source/drain, the multilevel schemes of silicon nanowire silicon-oxide-nitride-oxide-silicon (SONOS) cells are achieved at adequately low gate voltages. The n-channel cells work at a small gate voltage of 5 to 7 V using multilevel electron programming, whereas the p-channel cells operate at a low gate voltage of -7 to -11 V using multilevel hole programming. The roles of electron and hole carriers in the n-channel cells are exchanged in the p-channel nanowire cells because of ambipolar conduction. Both the n- and p-channel multilevel Schottky barrier nanowire SONOS cells preserve excellent thermal retention and cycling endurance for use in practical embedded and stand-alone nonvolatile memories.

A study on low-power, nanosecond operation and multilevel bipolar resistance switching in Ti/ZrO2/Pt nonvolatile memory with 1T1R architecture

Low-power, bipolar resistive switching (RS) characteristics in the Ti/ZrO2/Pt nonvolatile memory with one transistor and one resistor (1T1R) architecture were reported. Multilevel storage behavior was observed by modulating the amplitude of the MOSFET gate voltage, in which the transistor functions as a current limiter. Furthermore, multilevel storage was also executed by controlling the reset voltage, leading the resistive random access memory (RRAM) to the multiple metastable low resistance state (LRS). The experimental results on the measured electrical properties of the various sized devices confirm that the RS mechanism of the Ti/ZrO2/Pt structure obeys the conducting filaments model. In application, the devices exhibit high-speed switching performances (250 ns) with suitable high/low resistance state ratio (HRS/LRS > 10). The LRS of the devices with 10 year retention ability at 80 °C, based on the Arrhenius equation, is also demonstrated in the thermal accelerating test. Furthermore, the ramping gate voltage method with fixed drain voltage is used to switch the 1T1R memory cells for upgrading the memory performances. Our experimental results suggest that the ZrO2-based RRAM is a prospective alternative for nonvolatile multilevel memory device applications.

Design Considerations for Multilevel CMOS/Nano Memristive Memory

With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems by facilitating the implementation of multilevel logic. This work describes the design of such a multilevel nonvolatile memristor memory system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin for accurately reading and writing the data stored in a device are analyzed. Also analyzed are the nondisruptive read and write methodologies for the hybrid multilevel memristor memory to program and read the memristive information without corrupting it. This work showcases two write methodologies that leverage the best traits of memristors when used in either linear (low power) or nonlinear drift (fast speeds) modes. The system can therefore be tailored depending on the required performance parameters of a given application for a fast memory or a slower but very energy-efficient system. We propose for the first time, a hybrid memory that aims to incorporate the area advantage provided by the utilization of multilevel logic and nanoscale memristive devices in conjunction with CMOS for the realization of a high density nonvolatile multilevel memory.

Multilevel Data Storage Memory Using Deterministic Polarization Control

Multilevel non-volatile memory for high-density date storage is achieved by using the deterministic control of ferroelectric polarization. In a real ferroelectric thin-film system, eight stable and reproducible polarization states are realized (i.e., 3-bit data storage) by adjusting the displacement current. This approach can be used to triple or quadruple the memory density, even at existing feature scales.

A Simple Device Unit Consisting of All NiO Storage and Switch Elements for Multilevel Terabit Nonvolatile Random Access Memory

Present charge-based silicon memories are unlikely to reach terabit densities because of scaling limits. As the feature size of memory shrinks to just tens of nanometers, there is insufficient volume available to store charge. Also, process temperatures higher than 800 °C make silicon incompatible with three-dimensional (3D) stacking structures. Here we present a device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory using resistance switching. It is demonstrated that NiO films are scalable to around 30 nm and compatible with multilevel cell technology. The device unit can be a building block for 3D stacking structure because of its simple structure and constituent, high performance, and process temperature lower than 300 °C. Memory resistance switching of NiO storage element is accompanied by an increase in density of grain boundary while threshold resistance switching of NiO switch element is controlled by current flowing through NiO film.

Performance enhancement of multilevel cell nonvolatile memory by using a bandgap engineered high-κ trapping layer

A high-κ based charge trap flash (CTF) memory structure using bandgap engineered trapping layer HfO2/Al2O3/HfO2 (HAH) has been demonstrated for multilevel cell applications. Compared to a single HfO2 trapping layer, a CTF memory device based on the HAH trapping layer exhibits a larger memory window of 9.2 V, faster program/erase speed, and significantly improved data retention. Enhancements of memory performance and reliability are attributed to the modulation of charge distribution by bandgap engineering in trapping layer. The findings provide a guide for future design of CTF.