Multi-core Environment Research Articles

SSCFM: Separate Signature-Based Control Flow Error Monitoring for Multi-Threaded and Multi-Core Environments

Soft error is a key challenge in computer systems. Without soft error mitigation, control flow error (CFE) can lead to system crash. Signature-based CFE monitoring scheme is a representative technique for detecting CFEs during runtime. However, most of the signature-based CFE monitoring schemes proposed thus far are based on a single thread. Currently, the widely used multi-threaded and multi-core environments have greatly improved the performance of the computing system, but, if the these schemes are applied in these environments, performance improvement is difficult to achieve, or rather performance degradation may occur. In this paper, we propose a separate signature-based CFE monitoring (SSCFM) scheme that separates the signature update and the signature verification on the thread level. The signature update is combined with application thread and signature verification and executed on separate monitor threads, so that we can expect performance improvements in multi-threaded or multi-core environments. Furthermore, the SSCFM scheme can fully cover inter-procedural CFE not covered by many signature-based CFE monitoring schemes by using inter-procedural control flow analysis. With the proposed SSCFM scheme, the execution time overhead is reduced by approximately 26.67% on average from the SEDSR scheme, and the average CFE detection rate with SSCFM is approximately 93.69%. In addition, this paper also introduces the LLVM compiler-based SSCFM generator that makes it easy to apply the SSCFM scheme to software applications.

JAliEn: the new ALICE high-performance and high-scalability Grid framework

The ALICE experiment will undergo extensive hardware and software upgrades for the LHC Run3. This translates in significant increase of the CPU and storage resources required for data processing, and at the same time the data access rates will grow linearly with the amount of resources. JAliEn (Java ALICE Environment) is the new Grid middleware designed to scale-out horizontally to fulfil the computing needs of the upgrade, and at the same time to modernize all parts of the distributed system software. This paper will present the architecture of the JAliEn framework, the technologies used and performance measurements. This work will also describe the next generation solution that will replace our main database backend, the AliEn File Catalogue. The catalogue is an integral part of the system, containing the metadata of all files written to the distributed Grid storage and also provides powerful search and data manipulation tools. As for JAliEn, the focus has been put onto horizontal scalability, with the aim to handle near exascale data volumes and order of magnitude more workload than the currently used Grid middleware. Lastly, this contribution will present how JAliEn manages the increased complexity of the tasks associated with the new ALICE data processing and analysis framework (ALFA) and multi-core environments.

Using Local Clocks to Reproduce Concurrency Bugs

Multi-threaded programs play an increasingly important role in current multi-core environments. Exposing concurrency bugs and debugging such multi-threaded programs are quite challenging due to their inherent non-determinism. In order to mitigate such non-determinism, many approaches such as record-and-replay have been proposed. However, those approaches often suffer significant performance degradation because they require a large amount of recorded information and/or long analysis and replay time. In this paper, we propose an efficient and effective approach, ReCBuLC (reproducing concurrency bugs using local clocks), to take advantage of the hardware clocks available on modern processors. The key idea is to reduce the recording overhead and the time to analyze events’ global order by recording timestamps in each thread. These timestamps are used to determine the global order of shared accesses. To avoid the large overhead in accessing system-wide global clock, we opt to use local per-core clocks that incur much less access overhead. We then propose techniques to resolve skews among local clocks and obtain an accurate global event order. By using per-core clocks, state-of-the-art bug reproducing systems such as PRES and CLAP can reduce their recording overheads by up to 85 percent, and the analysis time up to 84.66% $\sim$ 99.99%, respectively.

Parallel MapReduce: Maximizing Cloud Resource Utilization and Performance Improvement Using Parallel Execution Strategies.

MapReduce is the preferred cloud computing framework used in large data analysis and application processing. MapReduce frameworks currently in place suffer performance degradation due to the adoption of sequential processing approaches with little modification and thus exhibit underutilization of cloud resources. To overcome this drawback and reduce costs, we introduce a Parallel MapReduce (PMR) framework in this paper. We design a novel parallel execution strategy of Map and Reduce worker nodes. Our strategy enables further performance improvement and efficient utilization of cloud resources execution of Map and Reduce functions to utilize multicore environments available with computing nodes. We explain in detail makespan modeling and working principle of the PMR framework in the paper. Performance of PMR is compared with Hadoop through experiments considering three biomedical applications. Experiments conducted for BLAST, CAP3, and DeepBind biomedical applications report makespan time reduction of 38.92%, 18.00%, and 34.62% considering the PMR framework against Hadoop framework. Experiments' results prove that the PMR cloud computing platform proposed is robust, cost-effective, and scalable, which sufficiently supports diverse applications on public and private cloud platforms. Consequently, overall presentation and results indicate that there is good matching between theoretical makespan modeling presented and experimental values investigated.

BRAM-based function reuse for multi-core architectures in FPGAs

Modern processors contain several specific hardware modules and multiple cores to ensure performance for a wide range of applications. In this context, FPGAs are frequently used as the implementation platform, since they offer architecture customization and fast time-to-market. However, many of them may not have the needed resources to implement all the necessary features, because of costs or complexity of the system to be implemented. When some needed functionalities do not fit in the target, they must be mapped into the much slower software domain. In this work, we exploit the fact these designs usually underuse their available BRAMs and propose a low-cost hardware-based function reuse mechanism for FPGAs, recovering some of the performance lost from the software part of applications that could not be implemented in hardware logic, with minimal impact on LUT usage. This is achieved by saving the inputs and outputs of the most frequently executed functions in a BRAM-based reuse table, so the next function executions with the same arguments can be skipped. This mechanism supports both precise and approximate modes and is evaluated with a 4-issue VLIW processor implemented in HDL, also considering a multi-core environment. Precise reuse, in single and multi-core scenarios, is assessed by running applications that use a software library to emulate floating point operations. Approximate reuse is evaluated over a single-core image-processing application that tolerates a certain level of error. Our scheme achieves 1.39 × geomean speedup in the precise single-core, while the multi-core case demonstrates application improvements from 1.25 × to 1.9 × when we start sharing the reuse table. In the approximate scenario, we achieve 1.52 × speedup with less than 10% error.

Parallel chance-constrained dynamic programming for cascade hydropower system operation

With continuing development of hydropower in China, cascade hydropower system will account for more in the power grid, and may increase power grid operation risk under global climate change. This paper presents a parallel chance-constrained dynamic programming model to derive optimal operating policies for a cascade hydropower system in China. The innovation work of this paper is mainly embodied in two aspects. First, the reliabilities of meeting the firm power requirements of the cascade hydropower system and avoiding extreme system failure under extreme events are explicitly embedded in the model using Lagrangian duality theory and a penalty function. Multiple operating policies are generated by updating the values of Lagrangian multiplier and penalty coefficient for system disruption, then best operating rules are selected based on system performance and evaluated according to simulated reliability, extreme system failure, and maximum benefit. Second, the Fork/Join parallel framework is deployed to parallelize the chance-constrained dynamic programming in a multi-core environment for improving computational efficiency. Two computing platforms with contrasting configurations are employed to illustrate the parallelization performance. Results from a cascade hydropower system operation demonstrate that the proposed method is computationally efficient and can obtain satisfying operating policies, especially for extreme drought events.

VBMq: pursuit baremetal performance by embracing block I/O parallelism in virtualization

Barely acceptable block I/O performance prevents virtualization from being widely used in the High-Performance Computing field. Although the virtio paravirtual framework brings great I/O performance improvement, there is a sharp performance degradation when accessing high-performance NAND-flash-based devices in the virtual machine due to their data parallel design. The primary cause of this fact is the deficiency of block I/O parallelism in hypervisor, such as KVM and Xen. In this paper, we propose a novel design of block I/O layer for virtualization, named VBMq. VBMq is based on virtio paravirtual I/O model, aiming to solve the block I/O parallelism issue in virtualization. It uses multiple dedicated I/O threads to handle I/O requests in parallel. In the meanwhile, we use polling mechanism to alleviate overheads caused by the frequent context switches of the VM’s notification to and from its hypervisor. Each dedicated I/O thread is assigned to a non-overlapping core to improve performance by avoiding unnecessary scheduling. In addition, we configure CPU affinity to optimize I/O completion for each request. The CPU affinity setting is very helpful to reduce CPU cache miss rate and increase CPU efficiency. The prototype system is based on Linux 4.1 kernel and QEMU 2.3.1. Our measurements show that the proposed method scales graciously in the multi-core environment, and provides performance which is 39.6x better than the baseline at most, and approaches bare-metal performance.

Performance improvement of using lambda expressions with new features of Java 8 vs. other possible variants of iterating over ArrayList in Java

Abstract A fluent programming is the programming technique where operations return a value that allows the invocation of another operation. With the fluent programming, it is perfectly natural to end up with one huge statement that is the concatenation of as many operations as you like. The Java Development Kit (JDK) streams (added in Java 8) are designed to support fluent programming. Instead of looping over all elements in the sequence repeatedly (once for filter, then again for map, and eventually for toArray), the chain of filtermapper-collector can be applied to each element in just one pass over the sequence. In this context, we often encounter lambda expressions used to create locally defined anonymous functions. They provide a clear and concise way to represent one method interface using an expression. Oracle claims that use of lambda expressions also improve the collection libraries making it easier to iterate through, filter, and extract data from a collection. In addition, new concurrency features improve performance in multicore environments. There are multiple ways to traverse, iterate, or loop collection in Java. Therefore, to solve one problem, we have several options for solutions that differ by undeniably increasing of the code readability. Searching for answers to the question of whether these new features really bring performance benefits over conventional way, is the subject of this paper.

Load Balancing Based SRMI in Multicore Environment

Load Balancing Based SRMI in Multicore Environment

Heterogeneous multi-core simulator based on SMP for the efficient application development at the heterogenous multi-core environment

Heterogeneous multi-core simulator based on SMP for the efficient application development at the heterogenous multi-core environment

An efficient multi-core implementation of the Jaya optimisation algorithm

ABSTRACTIn this work, we propose a hybrid parallel Jaya optimisation algorithm for a multi-core environment with the aim of solving large-scale global optimisation problems. The proposed algorithm is called HHCPJaya, and combines the hyper-population approach with the hierarchical cooperation search mechanism. The HHCPJaya algorithm divides the population into many small subpopulations, each of which focuses on a distinct block of the original population dimensions. In the hyper-population approach, we increase the small subpopulations by assigning more than one subpopulation to each core, and each subpopulation evolves independently to enhance the explorative and exploitative nature of the population. We combine this hyper-population approach with the two-level hierarchical cooperative search scheme to find global solutions from all subpopulations. Furthermore, we incorporate an additional updating phase on the respective subpopulations based on global solutions, with the aim of further improving the convergence rate and the quality of solutions. Several experiments applying the proposed parallel algorithm in different settings prove that it demonstrates sufficient promise in terms of the quality of solutions and the convergence rate. Furthermore, a relatively small computational effort is required to solve complex and large-scale optimisation problems.

An evolutionary scheduling approach for trading-off accuracy vs. verifiable energy in multicore processors

Abstract This work addresses the problem of energy-efficient scheduling and allocation of tasks in multicore environments, where the tasks can allow a certain loss in accuracy in the output, while still providing proper functionality and meeting an energy budget. This margin for accuracy loss is exploited by using computing techniques that reduce the work load, and thus can also result in significant energy savings. To this end, we use the technique of loop perforation, that transforms loops to execute only a subset of their original iterations, and integrate this technique into our existing optimization tool for energy-efficient scheduling. To verify that a schedule meets an energy budget, both safe upper and lower bounds on the energy consumption of the tasks involved are needed. For this reason, we use a parametric approach to estimate safe (and tight) energy bounds that are practical for energy verification (and optimization applications). This approach consists in dividing a program into basic (‘branchless’) blocks, establishing the maximal (resp. minimal) energy consumption for each block using an evolutionary algorithm, and combining the obtained values according to the program control flow, by using static analysis to produce energy bound functions on input data sizes. The scheduling tool uses evolutionary algorithms coupled with the energy bound functions for estimating the energy consumption of different schedules. The experiments with our prototype implementation were performed on multicore XMOS chips, but our approach can be adapted to any multicore environment with minor changes. The experimental results show that our new scheduler enhanced with loop perforation improves on the previous one, achieving significant energy savings (31% on average for the test programs) for acceptable levels of accuracy loss.

Complexity Analysis of Vedic Mathematics Algorithms for Multicore Environment

The huge computations performed sequentially requires a lot of time for execution as on contrary to the concurrent implementation. Many problems are involved in the dense linear algebra operations the main focus for this work is for solving linear equations. The problem of solving linear equations when approached using parallel implementation will yield better results. The Vedic mathematical method of Paravartya Yojayet is having less complexity as compared to the conventional methods. This work mainly focuses on the parallel implementation of the Paravartya Yojayet and its comparison to the benchmarking of the existing LU decomposition. The results of this implementation of Paravartya Yojayet are better when analysed theoretically but its actual parallel implementation will vary so it needs to be analysed and this work presents the same. The comparative analysis of the two ways for parallelization of the Paravartya Yojayet methods viz. ‘For loop' parallelization and the ‘direct parallelization' is also analysed in this work.

An efficient strategy for the activation of MIP relaxations in a multicore global MINLP solver

Solving mixed-integer nonlinear programming (MINLP) problems to optimality is a NP-hard problem, for which many deterministic global optimization algorithms and solvers have been recently developed. MINLPs can be relaxed in various ways, including via mixed-integer linear programming (MIP), nonlinear programming, and linear programming. There is a tradeoff between the quality of the bounds and CPU time requirements of these relaxations. Unfortunately, these tradeoffs are problem-dependent and cannot be predicted beforehand. This paper proposes a new dynamic strategy for activating and deactivating MIP relaxations in various stages of a branch-and-bound algorithm. The primary contribution of the proposed strategy is that it does not use meta-parameters, thus avoiding parameter tuning. Additionally, this paper proposes a strategy that capitalizes on the availability of parallel MIP solver technology to exploit multicore computing hardware while solving MINLPs. Computational tests for various benchmark libraries reveal that our MIP activation strategy works efficiently in single-core and multicore environments.

Optimum design of hybrid HVDC circuit breakers using a parallel genetic algorithm and a MATLAB‐EMTP environment

The optimum design of power system components is becoming a relevant topic in power system studies. Genetic algorithms (GAs) are considered as a proper approach for optimisation problems in which non-linear elements are involved. Several trends are presently leading GAs to a new level; for instance, its combination with parallel computing can facilitate the solution of problems where individual evaluations of the fitness function require an important computational effort. This study presents a procedure based on a MATLAB-EMTP application and the usage of a multicore environment for the optimum selection of hybrid high-voltage DC (HVDC) circuit breaker parameters; the goal is to obtain a transient response of the hybrid design with voltages, currents and fault clearance times within specified limits.

SharkDB: an in-memory column-oriented storage for trajectory analysis

The last decade has witnessed the prevalence of sensor and GPS technologies that produce a high volume of trajectory data representing the motion history of moving objects. However some characteristics of trajectories such as variable lengths and asynchronous sampling rates make it difficult to fit into traditional database systems that are disk-based and tuple-oriented. Motivated by the success of column store and recent development of in-memory databases, we try to explore the potential opportunities of boosting the performance of trajectory data processing by designing a novel trajectory storage within main memory. In contrast to most existing trajectory indexing methods that keep consecutive samples of the same trajectory in the same disk page, we partition the database into frames in which the positions of all moving objects at the same time instant are stored together and aligned in main memory. We found this column-wise storage to be surprisingly well suited for in-memory computing since most frames can be stored in highly compressed form, which is pivotal for increasing the memory throughput and reducing CPU-cache miss. The independence between frames also makes them natural working units when parallelizing data processing on a multi-core environment. Lastly we run a variety of common trajectory queries on both real and synthetic datasets in order to demonstrate advantages and study the limitations of our proposed storage.

RAMSYS: Resource-Aware Asynchronous Data Transfer with Multicore SYStems

High-speed data transfer is vital to data-intensive computing that often requires moving large data volumes efficiently within a local data center and among geographically dispersed facilities. Effective utilization of the abundant resources in modern multicore environments for data transfer remains a persistent challenge, particularly, for Non-Uniform Memory Access (NUMA) systems wherein the locality of data accessing is an important factor. This requires rethinking how to exploit parallel access to data and to optimize the storage and network I/Os. We address this challenge and present a novel design of asynchronous processing and resource-aware task scheduling in the context of high-throughput data replication. Our software allocates multiple sets of threads to different stages of the processing pipeline, including storage I/O and network communication, based on their capacities. Threads belonging to each stage follow an asynchronous model, and attain high performance via multiple locality-aware and peer-aware mechanisms, such as task grouping, buffer sharing, affinity control and communication protocols. Our design also integrates high performance features to enhance the scalability of data transfer in several scenarios, e.g., file-level sorting, block-level asynchrony, and thread-level pipelining. Our experiments confirm the advantages of our software under different types of workloads and dynamic environments with contention for shared resources, including a 28-160 percent increase in bandwidth for transferring large files, 1.7-66 times speed-up for small files, and up to 108 percent larger throughput for mixed workloads compared with three state of the art alternatives, GridFTP , BBCP and Aspera.

멀티코어 환경에서 비실시간 메시지의 응답시간 지연을 최소화하는 리눅스 기반 메시지 처리기의 설계 및 구현

메시지 처리기란 다양한 클라이언트로부터 오는 메시지를 받아 처리하는 서버 소프트웨어이며, 메시지의 종류에 따라 마감기한 이내에 처리해야 하는 실시간 메시지와 비실시간 메시지를 처리한다. 최근 마이크로프로세서 기술의 발전과 리눅스의 빠른 보급에 따라 메시지 처리기는 멀티코어 기반의 리눅스 서버에서 구현되고 있으며, 멀티코어 환경에서는 코어를 효율적으로 사용해야 시스템의 성능을 극대화 시킬 수 있다. 멀티코어를 효율적으로 사용하기 위한 다양한 실시간 스케줄러가 제안되어 있지만, 많은 연구들이 이론적 분석이나 시뮬레이션에 국한되어 있고, 리눅스를 위해 제안된 일부 알고리즘들도 커널을 수정하거나 특정 커널 버전에서만 동작된다는 단점이 있다. 본 논문에서는 멀티코어 환경에서 쓰레드를 사용자 수준에서 코어에 직접 매핑하는 리눅스 기반 메시지 처리기의 구조를 제안한다. 구현된 메시지 처리기에서는 기존의 RM(Rate Monotonic) 알고리즘을 수정하여 사용하였고, 특정 코어에 최대한 실시간 메시지를 몰아서 처리하도록 First fit 기반의 빈패킹(Bin-Packing) 알고리즘을 사용하여, 실시간 메시지의 위배율을 보장하면서 비실시간 메시지의 응답시간의 지연을 최소화하였다. 성능평가를 위하여 LITMUS 프레임워크에서 제공하는 2가지 멀티코어 스케줄링 알고리즘(GSN-EDF, P-FP)을 이용하여 메시지 처리기를 구현한 후 제안된 시스템과 비교한 결과, 비실시간 메시지의 응답시간이 2가지 알고리즘 대비 최대 17～18%까지 향상되는 것을 확인하였다.

Layout Lock

Data-structures can benefit from dynamic data layout modifications when the size or the shape of the data structure changes during the execution, or when different phases in the program execute different workloads. However, in a modern multi-core environment, layout modifications involve costly synchronization overhead. In this paper we propose a novel layout lock that incurs a negligible overhead for reads and a small overhead for updates of the data structure. We then demonstrate the benefits of layout changes and also the advantages of the layout lock as its supporting synchronization mechanism for two data structures. In particular, we propose a concurrent binary search tree, and a concurrent array set, that benefit from concurrent layout modifications using the proposed layout lock. Experience demonstrates performance advantages and integration simplicity.

멀티코어 환경에서 SEDA 기반 메시지 처리기의 수행함수 특성을 고려한 쓰레드 매핑 기법

멀티코어 환경에서 SEDA 기반 메시지 처리기의 수행함수 특성을 고려한 쓰레드 매핑 기법