Motion Estimation Architecture Research Articles

About the improvement in Mars Polar Motion determination from radio tracking of two landers

The polar motion of Mars is defined as the movement of the rotation axis with respect to a body-fixed frame tied to the crust of the planet. It is composed of forced motion at annual and sub-annual frequencies caused by the seasonal mass redistribution, formation of the polar ice caps and angular momentum variations of the atmosphere, and of the free mode called the Chandler wobble.Radio-tracking data from landers offers the most suitable means to measure the rotation of Mars, including its polar motion. The latter, however, has not yet been achieved using lander data alone. In this study, we assess the uncertainties associated with Mars polar motion estimation using Direct-To-Earth Doppler, range and Same-Beam Interferometry (SBI) observables between multiple landers on the surface of Mars. We evaluate the improvement enabled by combining data from multiple landers with respect to one-lander scenarios, and identify the optimal mission architectures for polar motion estimation by considering the influence of respective mission parameters on the estimation uncertainty. In particular, we consider the effects of absolute and relative locations of the landers and of mission scheduling. We re-evaluate the possibility of estimating the polar motion using data from landers in proximity to the equator, and apply our considerations to simulated data consistent in number and accuracy with that collected by past Martian missions. We notice and explain a strong longitude dependence of the formal errors when the polar motion parameters are estimated concurrently with the seasonal spin variation parameters, making it impossible to properly determine all components of polar motion with a single lander regardless of its location. However, the use of two or more landers in optimal locations with respect to each other eliminates those limitations. We evaluate the influence of latitudinal and longitudinal separation on polar motion determination in such cases. In particular, we are able to determine polar motion well even in cases where the longitudes of the two landers make determination from each single lander impossible.

An efficient hardware architecture of integer motion estimation based on early termination and data reuse for Versatile video coding

The integer motion estimation (IME) involves high computational complexity and large amount of computation data due to the variable block sizes, and it is one of the most critical bottlenecks in video coding. The traditional algorithm for integer motion estimation loses search accuracy when simplifying the motion search process, or it becomes complex to pursue search accuracy, which is not conducive to video encoding and transmission. This paper presents a data reuse algorithm based on search window division, block splitting, the arrangement of search points in the Test Zone (TZ) search algorithm and block division. which divides pixel blocks of different sizes into several 8x8 pixel blocks and then reuses the overlapping 8x8 pixel blocks between adjacent search points of the Test Zone (TZ) search algorithm to reduce hardware resource consumption. By comparing the Sum of Absolute Differences (SAD) values of left and top pixel blocks with current pixel block, the integer motion estimation (IME) can be terminated in advance, reducing the computation complexity of integer motion estimation by over 70 %. Furthermore, the paper also presents a hardware architecture based on the data reuse algorithm, which can process 7680 × 4320@60fps videos at an operating clock frequency of 182.99 MHz, with lower resource consumption compared to similar hardware designs.

An efficient VLSI architecture for fast motion estimation by hybridizing parallel spiral and adaptive threshold star diamond search algorithm‐based search algorithm in HEVC

SummaryThis article proposes a high efficiency video coding (HEVC) standard hardware using block matching motion estimation algorithm. A hybrid parallel spiral and adaptive threshold star diamond search algorithm (Hyb PS‐ATSDSA) proposes for fast motion estimation in HEVC. Parallel spiral search approach utilizes spiral pattern for searching from center to the surroundings and adaptive threshold SDA consists of two phases, they are adaptive threshold and star diamond algorithm. To lower computational complexities in HEVC architecture, parallel spiral search algorithm uses several blocks matching schemes. Adaptive threshold and star diamond algorithm are used to reduce the matching errors and remove the invalid blocks early from the procedure of motion estimation and finally predicts the final motion of the image. Speed is increased while using this hybrid algorithm. Proposed structure is carried out in Xilinx; ISE 14.5 design suit, then the experimental outcomes are analyzed to existing motion estimation strategies in field‐programmable gate array devices. Experimental performance of the proposed Hyb‐PS‐ATSDSA‐ME‐HEVC method attains lower delay 33.97%, 32.97%, 62.97, and 26.97%, and lower area 34.867%, 45.97%, 27.97%, and 43.967% compared with the existing methods, such as FSA‐ME‐HEVC, TZSA‐ME‐HEVC, hyb TZSA‐IME‐HEVC, and IBMSA‐ME‐HEVC, respectively.

Correction to: An Efficient VLSI Architecture for Fast Motion Estimation Exploiting Zero Motion Prejudgment Technique and a New Quadrant Depended on Search Algorithm in HEVC

Correction to: An Efficient VLSI Architecture for Fast Motion Estimation Exploiting Zero Motion Prejudgment Technique and a New Quadrant Depended on Search Algorithm in HEVC

Myocardial strain analysis of echocardiography based on deep learning.

Strain analysis provides more thorough spatiotemporal signatures for myocardial contraction, which is helpful for early detection of cardiac insufficiency. The use of deep learning (DL) to automatically measure myocardial strain from echocardiogram videos has garnered recent attention. However, the development of key techniques including segmentation and motion estimation remains a challenge. In this work, we developed a novel DL-based framework for myocardial segmentation and motion estimation to generate strain measures from echocardiogram videos. Three-dimensional (3D) Convolutional Neural Network (CNN) was developed for myocardial segmentation and optical flow network for motion estimation. The segmentation network was used to define the region of interest (ROI), and the optical flow network was used to estimate the pixel motion in the ROI. We performed a model architecture search to identify the optimal base architecture for motion estimation. The final workflow design and associated hyperparameters are the result of a careful implementation. In addition, we compared the DL model with a traditional speck tracking algorithm on an independent, external clinical data. Each video was double-blind measured by an ultrasound expert and a DL expert using speck tracking echocardiography (STE) and DL method, respectively. The DL method successfully performed automatic segmentation, motion estimation, and global longitudinal strain (GLS) measurements in all examinations. The 3D segmentation has better spatio-temporal smoothness, average dice correlation reaches 0.82, and the effect of target frame is better than that of previous 2D networks. The best motion estimation network achieved an average end-point error of 0.05 ± 0.03 mm per frame, better than previously reported state-of-the-art. The DL method showed no significant difference relative to the traditional method in GLS measurement, Spearman correlation of 0.90 (p < 0.001) and mean bias -1.2 ± 1.5%. In conclusion, our method exhibits better segmentation and motion estimation performance and demonstrates the feasibility of DL method for automatic strain analysis. The DL approach helps reduce time consumption and human effort, which holds great promise for translational research and precision medicine efforts.

Correction to: An Efficient VLSI Architecture for Fast Motion Estimation Exploiting Zero Motion Prejudgment Technique and a New Quadrant-Based Search Algorithm in HEVC

In this manuscript, new quadrant-based search algorithm with zero motion prejudgment is proposed for motion estimation (ME) in HEVC (High Efficiency Video Coding) standard. The HEVC standard is used to obtain efficient output with low motion estimation time. The proposed quadrant-based search algorithm is a fast block matching algorithm that obtain better block matching amid the current block and reference block. The zero motion prejudgment (ZMP) method is used to find the block, whether it is motion or static and it is used for decreasing the computational complexity (CC) in the proposed quadrant-based search algorithm. The proposed quadrant-based search algorithm with ZMP technique for motion estimation in HEVC is implemented on the FPGA hardware platform. The entire architecture is executed in Verilog HDL with Virtex-5 technology and integrated with Xilinx ISE Design Suite 14.5. The results are integrated into the CIF (352 × 288 pixels) and HD (1280 × 720 pixels) video input sequence. The evaluation metrics like PSNR, Motion estimation time, sum of absolute difference (SAD) value are analyzed with existing method like hexagon, adaptive root pattern algorithm, and diamond search algorithm. Then the hardware parameters like power consumption and maximum operating frequency are measured. The hardware utilization is reduced and the power consumption of the proposed model is diminished to 0.143 W. The maximal operating frequency of the proposed model is 440.470 MHz. The experimental outcomes demonstrate that the proposed motion evaluation approach in HEVC is more effective than existing algorithms.

An efficient field programmable gate array based hardware architecture for efficient motion estimation with parallel implemented genetic algorithm

SummaryThe main idea of this article is to propose a hardware design of block matching (BM) algorithm for an efficient motion estimation (ME) strategy in a field programmable gate array platform based on a parallel implemented genetic algorithm (GA). Easiness and the effectiveness of the BM algorithm while implementing have a major drawback of low quality and computationally cost expensive during the process of ME. Therefore, here in this article, we suggest GA based BM for a quick and cost‐effective computation of motion vectors, without negotiating the quality factor. The ME carried out for various video sequences is implemented by using Xilinx ISE Design Suite 14.1. Delay, time, area, power, PSNR, MSE, SNR, SSIM, and NRMSE are the metrics used for analyzing the performance, and the simulation outcome shows that this parallel implemented BM architecture design shows an exotic improvement in time, quality and in utilization of power on estimating the motion than that of the conventional designs.

An efficient highly parallelized ReRAM-based architecture for motion estimation of HEVC

Motion estimation (ME) is a high efficiency video coding (HEVC) process for determining motion vectors that describe the blocks transformation direction from one adjacent frame to a future frame in a video sequence. ME is a memory and computation consuming process which accounts for more than 50% of the total running time of HEVC. To conquer the memory and computation challenges, this paper presents ReME, a highly paralleled processing-in-memory (PIM) architecture for the ME process based on resistive random access memory (ReRAM). In ReME, the space of ReRAM is mainly separated into storage engine and ME processing engine. The storage engine is used as conventional memory to store video frames and intermediate data, while the computation operations of ME are performed in ME processing engines. Each ME processing engine in ReME consists of Sum of Absolute Differences (SAD) modules, interpolation modules, and Sum of Absolute Transformed Difference (SATD) modules that transfer ME functions into ReRAM-based logic analog computation units. ReME further cooperates these basic computation units to perform ME processes in a highly parallel manner. Simulation results show that the proposed ReME accelerator significantly outperforms other implementations with time consuming and energy saving.

Correction to: H.264 Video Coding‑Based Motion Estimation Architecture for Video Broadcasting from a Studio

Correction to: H.264 Video Coding‑Based Motion Estimation Architecture for Video Broadcasting from a Studio

Fast and energy-efficient approximate motion estimation architecture for real-time 4 K UHD processing

Approximate computing techniques exploit the characteristics of error-tolerant applications either to provide faster implementations of their computational structures or to achieve substantial improvements in terms of energy efficiency. In video encoding, the motion estimation (ME) stage, including the Integer ME (IME) and the Fractional ME (FME) steps, is the most computational intensive task and it is highly resilient to controlled losses of accuracy. In accordance, this article proposes the exploitation of approximate computing techniques to implement energy efficient dedicated hardware structures targeting the motion estimation stage of current video encoders. The designed ME architecture supports IME and FME and is able to real-time process 4 K UHD videos (3840 × 2160 pixels) at 30 frames per second, while dissipating 108.92 mW. When running at its maximum operation frequency, the architecture can process 8 K UHD videos (7680 × 4320 pixels) at 120 frames per second. The solution described in this article presents the highest throughput and the highest energy efficiency among all state-of-the-art compared works, showing that the use of approximate computing is a promising solution when implementing video encoders in dedicated hardware.

H.264 Video Coding-Based Motion Estimation Architecture for Video Broadcasting from a Studio

Motion estimation (ME) as a process in H.264 coding basically deals with huge number of image data and needs a lot of calculation so that it should be considered to improve by hardware implementation and data redundancy reduction. This paper proposes an H.264 coding-based motion estimation architecture for video broadcasting from a studio. To implement a hardware of motion estimation, parallel processing is logically applied in the preprocessing and keypoint finding processes, and time-domain based algorithm is replaced by the frequency-domain based algorithm in order to filter the informative data in the low frequency range. The experimental results show that the proposed H.264 coding-based motion estimation architecture achieved significant improvement while maintaining the signal quality.

BlockNet: A Deep Neural Network for Block-Based Motion Estimation Using Representative Matching

Owing to the limitations of practical realizations, block-based motion is widely used as an alternative for pixel-based motion in video applications such as global motion estimation and frame rate up-conversion. We hereby present BlockNet, a compact but effective deep neural architecture for block-based motion estimation. First, BlockNet extracts rich features for a pair of input images. Then, it estimates coarse-to-fine block motion using a pyramidal structure. In each level, block-based motion is estimated using the proposed representative matching with a simple average operator. The experimental results show that BlockNet achieved a similar average end-point error with and without representative matching, whereas the proposed matching incurred 18% lower computational cost than full matching.

Low Power Motion Estimation Algorithm and Architecture of HEVC/H.265 for Consumer Applications

High-quality videos like high-definition (HD) and ultra HD became an essential requirement in recent applications such as security surveillance, television system, etc. However, due to increase in resolution of the videos, the volume of visual information data increases significantly, which became a challenge for storage, transmission and processing the HD video data. The new video compression standard, high efficient video coding (HEVC), achieved two-fold video efficiency improvements as compared to H.264/AVC using efficient compression techniques. Motion estimation (ME) is one of the computationally intensive blocks in video CODEC. In HEVC, the complexity of ME further increases due to a large processing unit and flexible partitioning of the prediction unit (PU). In this paper, we proposed a low power ME algorithm and architecture of the HEVC for consumer applications. The proposed algorithm and architecture utilizes sub-sampling, data reuse, pixel truncation and adaptive search range techniques for reducing the computational power. Simulations result shows that the proposed ME algorithm requires an average of 53.82% fewer search points as compared to the reference software HM with a small degradation in PSNR and little increment in bit-rate. The proposed architecture is simulated and synthesized using standard 90 nm technology. The proposed ME architecture can process $3840\times2160$ @ 30 fps video sequences with only 4.5193 mm2 of the area and 8.192 KB of SRAM. The operating frequency of the proposed architecture is 250 MHz with 151.7619 mW of power.

A High-Speed VLSI Architecture for Motion Estimation Using Modified Adaptive Rood Pattern Search Algorithm

The paper presents an efficient VLSI architecture for fast Motion Estimation in video codec using modified Adaptive Rood Pattern Search Algorithm. The proposed architecture uses an interleaved memory arrangement and an early check technique to compute the Sum of Absolute Differences. The proposed design can process High Definition (1080p) video frames in real time while optimizing the hardware area. The architecture has been implemented in verilog HDL and mapped to 45 nm FPGA. It uses only 6.8K gates for the implementation of the datapath and the controller. It achieves a maximum frequency of 120 MHz. However, working at 100 MHz, it is able to process 60 HD ( $$1920\times 1080$$ ) frames per second while consuming 39 mW of power. The proposed architecture achieves premium speed with an optimum power and area requirements and can be suitably incorporated in light-weight video-intensive devices like smart-phones, tablet computers.

One-dimensional filtering based two-bit transform and its efficient hardware architecture for fast motion estimation

Video encoding is one of the most emerging application in many consumer electronics devices such as smartphones, tablets, cameras and camcorders in order to reduce required memory size for recording and utilized bandwidth for transmission purposes. The processing and battery power required for real-time video encoding is an important challenge for this kind of devices. Thus, efficient video encoding hardware architectures are required. Motion estimation process consumes most of the resources in a typical video encoder. Hence, low-complexity motion estimation approaches with efficient hardware implementations are investigated in the literature. In this paper, a novel low-complexity motion estimation approach based on one-dimensional filtering of input frames to construct two bit-planes for matching is presented. An embedded hardware architecture is also presented in order to demonstrate feasibility of the seamless integration into the state of the art consumer electronics devices. The, binarization stage of filtering based low- complexity motion estimation approaches are implemented in hardware first time in the literature. Experimental results show that the proposed motion estimation method and its hardware architecture provides an efficient alternative to existing low-complexity ME methods.

The algorithm and VLSI architecture of a high efficient motion estimation with adaptive search range for HEVC systems

This paper presents a novel algorithm and VLSI architecture of motion estimation (ME) for high efficiency video coding systems. The proposed algorithm examines a much smaller set of search candidates and thus greatly reduces the computational complexity. Furthermore, in order to strike a balance between the quality of the Video and the efficiency of the system, this algorithm possesses the advantages that the number of search candidates is adaptive to the characteristic of the Video content. The simulation results show that, compared to the HM reference software, the proposed algorithm leads to a 96% reduction in search candidates with only 1.98% increment in average bitrate. Based on this algorithm, a hardware-efficient VLSI architecture of ME is designed and implemented with 90 nm technology. The experimental results show that, occupying the area complexity of 274.5 kGE, the presented design achieves 60 frames per second with resolution of 3840 × 2160 at the frequency of 201 MHz. The proposed ME system enhances the hardware efficiency by at least 50% compared to the prior works.

Energy efficient processing of motion estimation for embedded multimedia systems

Visual sensor networks require low power compression techniques of large amount of video data in each camera node due to the energy-constrained and bandwidth-limited environments. In this paper, energy-efficient architecture for Variable Block Size Motion Estimation is proposed to fully utilize dynamic partial reconfiguration capability of programmable hardware fabric in distributed embedded vision processing nodes. Partial reconfiguration of FPGA is exploited to support run-time reconfiguration of the proposed modular hardware architecture for motion estimation. According to the required search range, hardware reconfiguration is performed adaptively to reduce the hardware resources and power consumption. A reconfigurable ME ranging from simple 1-D to a complex 2-D Sum of Absolute Differences (SAD) array to perform full search block matching is selected in order to support different search window size. The implemented scalable SAD array can provide different resolutions and frame rates for real time applications with multiple reconfigurable regions.

Design and implementation of low-power motion estimation based on modified full-search block motion estimation

Due to the increasing demand of data transfer in video process. Motion estimation is an important component in power-consumption of video codec. And the important thing to design the motion estimation is power optimization, which is achieved by carefully designing motion estimator. This paper is proposed with modified full-search block motion estimation algorithm for different video coding standard. The proposed architecture for full-search block motion estimation allows the frames into nine 16X16 sub-blocks. And finite-state machine is integrated with the proposed architecture for best block matching in the search area. In the proposed architecture, cells are used to store the current frame and compare the current frame with a reference frame to achieve the low-power by reusing the block. The proposed algorithm was designed using Verilog HDL and implemented in Altera FPGA using Altera Quartus II synthesis tool. Compare with the conventional architecture, our proposed architecture was designed with low power and area and high Peak signal to noise ratio (PSNR), which is 5 times faster than the conventional method.

Energy Efficient Reconfigurable Architecture for Motion Estimation in Video Coding

Background/Objectives: Reconfigurable architecture has ability to dynamically allocate the hardware resources during runtime. It can be effectively used in computationally intensive application like media processing. As the motion estimation in video coding consumes large amount of computational time and resources, it can be mapped into reconfigurable architecture to effectively manage the power utilization by dynamic reconfiguration. Methods/Statistical Analysis: A systolic array based reconfigurable architecture for motion estimation which can be configured based on the properties of input video is proposed. A dynamically reconfigurable hardware is designed which can be worked on different search regions based on the level of motion in frames of input video. For the input video, the level of motion among the adjacent frames is determined by motion analyzer. Based on the level of motion between the frames of video, the search window size for block search is selected and this selection will enable the optimum number of processing elements for processing. This dynamic selection of hardware resources based on the search window reduces the power dissipation and computational complexity. Findings: Two search windows have been fixed for analysis 8 × 8 and 7 × 7. For power dissipation analysis, the total logic elements, total registers and fan-out for each design is taken. The performance is analysed by enabling selective number of processing elements for different size of search window. It is observed that power dissipation is high for the search window 8 × 8, because the resource utilization is higher than 7 × 7 search window. Instead of using the same fixed search window for performing block batching, different sized search windows can be used based on the level of motion of the video. After analysis, it is positively found that the proper selection of search window will lead to the optimum utilization in terms of power and resources. Application/Improvements: The context-aware reconfigurable hardware design for highly computationally intensive applications like video processing would be helpful in optimizing the power and resource utilization in hand held devices like smart phones, cam-coders etc.

High Performance Architecture of Motion Estimation Algorithm for Video Compression

Motion estimation (ME) is a highly computationally intensive operation in video compression. Efficient ME architectures are proposed in the literature. This paper presents an efficient low computational complexity systolic architecture for full search block matching ME (FSBME) algorithm. The proposed architecture is based on one-bit transform-based full search (FS) algorithm. The proposed ME hardware architectures perform FS ME for four macroblocks (MBs) in parallel. The proposed hardware architecture is implemented in VHDL. The FSBME hardware consumes 34% of the slices in a Xilinx Vertex XC6vlx240T FPGA device with a maximum frequency of 133[Formula: see text]MHz and is capable of processing full high definition (HD) ([Formula: see text]) frames at a rate of 60 frames per second.