Most Significant Bit Research Articles

Intensity Adaptive LSB Method Applying a Revised Matching

paper proposes a new steganographic algorithm in spatial domain. A filtering method selects some color components of pixelsin BMP cover imagesfor embedding according to their Most Significant Bits(MSB) value. The components whose MSB value isgreater than a particular threshold,are qualified and the other ones will be skipped. This mechanism makes the retrieval of embedded message possible. Moreover, a matching technique ensures the most possible closeness of new intensity generated in embedding process to its original value.Performance of proposed method is evaluated by some measures namely MAE, MSE,LMSE,L P -Norm, SNR, PSNR, and NCC according to which, proposed method offers up to 40% better results in some measures compared to two other methods; LSB and SLSB.

QUANTIZATION-BASED FRAGILE WATERMARKING USING BLOCK-WISE AUTHENTICATION AND PIXEL-WISE RECOVERY SCHEME FOR TAMPERED IMAGE

This paper suggests an efficient fragile watermarking scheme for image content authentication along with altered region restoration capability. In this scheme, image is divided into nonoverlapping blocks of size 2 × 2 and for each block, eight bits for image content recovery data and four bits for authentication data from five most significant bits (MSBs) of each pixel, are generated. These 12 bits are embedded into the least significant bits (LSBs) of the pixels which are placed in its corresponding mapping block. At the receiver end by comparing the recalculated and extracted authentication data, the tampered blocks can easily be identified and using recovery data, one can easily restore the tampered block. Results of experiments demonstrate that the proposed scheme is effective enough for alteration detection as well as tamper recovery of the image.

An Adaptive Image Steganography Technique Using LSB and MSB

IN modern years Steganography is playing a significant role in secure communication. It is a technique of embedding secret information into cover media (image, video, audio and text) such that only the sender and the authoritative receiver can detect the occurrence of hidden information. The two essential properties of Steganography are good visual imperceptibility of the payload which is crucial for security of hidden communication and payload is essential for conveying huge quantity of secret information. Steganography has to satisfy two requirements, one is capability and the other is transparency. Capability means embedding large payload into media. Transparency means an ability to prevent distinction between stego and cover image by statistical analysis. Earlier they have used least significant bit (LSB), the simplest form of Steganography. In LSB method, data is inserted in the least significant bit which leads to a negligible change on the cover image that is not visible to the naked eye. Since this method can be easily cracked, it is more exposed to attacks. In the proposed system we propose Spatial Domain Steganography using 1-Bit Most Significant Bit (MSB) with confused manner.

Improved bounds for the implicit factorization problem

We study the problem of integer factoring with implicit hints. This problem is described as follows: Let $N_{1}=p_{1}q_{1},\dots,N_{k}=p_{k}q_{k}$ be $k$ different RSA moduli of same bit-size, where $q_1,\dots,q_k$ are of the same bit-size too. Given the implicit information that $p_{1},\dots,p_{k}$ share some certain portions of bit pattern, under what condition is it possible to factorize $N_{1},\dots,N_{k}$ efficiently? This problem has been studied in many references recently and many interesting results have been obtained. In this paper, we modify the previous algorithm presented by Sarkar and Maitra (IEEE TIT 57(6): 4002-4013, 2011). We show that our result achieves an improved generalized bounds in the cases where $p_{1},\dots,p_{k}$ share some amount of 1) most significant bits (MSBs); 2) least significant bits (LSBs); 3) MSBs and LSBs together. As far as we are aware, our result is better than all known results.

A Novel Least Significant Bit First Processing Parallel CRC Circuit

In HDLC serial communication protocol, CRC calculation can first process the most or least significant bit of data. Nowadays most CRC calculation is based on the most significant bit (MSB) first processing. An algorithm of the least significant bit (LSB) first processing parallel CRC is proposed in this paper. Based on the general expression of the least significant bit first processing serial CRC, using state equation method of linear system, we derive a recursive formula by the mathematical deduction. The recursive formula is applicable to any number of bits processed in parallel and any series of generator polynomial. According to the formula, we present the parallel circuit of CRC calculation and implement it with VHDL on FPGA. The results verify the accuracy and effectiveness of this method.

A novel chaos-based fragile watermarking for image tampering detection and self-recovery

In this paper, a novel watermarking approach is proposed to provide enhanced tampering localization and self-recovery. A cross chaotic map is used to confuse the blocks generated by the original image. A sister block embedding scheme is proposed to improve the recovery effect after tampering. Flags and a combination of the most significant bit (MSB) and the least significant bit (LSB) mechanism are applied to improve the tampering detection rate and the defense of attacks. And an optimization scheme is given to make the recovered image have advanced visual effects. Experiment results show that the proposed schemes are more secure and have better effect on tampering detection and recovery even though the tampered area is relatively large.

A Flexible Low Power DSP With a Programmable Truncated Multiplier

Truncated multiplication reduces part of the power required by multipliers by only computing the most-significant bits of the product. The most common approach to truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation subcircuits. However, this results in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision multiplier is implemented, but the active section of the partial product matrix is selected dynamically at run-time. This allows a power reduction tradeoff against signal degradation which can be modified at run time. Such an architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analyzed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a fine-grain truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. Software compensation is also shown to be effective when deploying truncated multipliers in a system.

A New Delay-Line Sharing Based CMOS Digital PWM Circuit

This paper presents a new circuit design for digital pulse-width modulators (DPWM). This method improves the structure of hybrid DPWM to a more compact architecture by utilizing the separation of MSB (most significant bit) and LSB (least significant bit) groups. In addition, a delay-line function block is shared with MSB and LSB groups to reduce power consumption. HSPICE post-layout simulation shows that this new DPWM circuit operates successfully at 200 MHz clock frequency and has 1.55-mW power consumption. An experimental chip had been fabricated by using a standard 0.18 micron CMOS process. The layout area of the chip including I/O pads is 461 m×370 m. The new DPWM design carries the advantages of smaller chip area and low power consumption especially for the high resolution required.

Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering

Array sensors require a high-performance analog-to-digital converter (ADC) array with small area and low power. Successive-approximation register (SAR) ADC has good potential for ADC array due to its simple analog circuits. However, SAR ADCs with 10-b resolution and higher normally need a large capacitor array due to the stringent matching requirement. The large capacitor array also limits the ADC dynamic performance. The capacitor mismatch has been compensated by analog calibration techniques. In this work, a novel digital calibration method is developed for SAR ADC based on dithering. With dithering, weights of most significant bit (MSB) capacitors can be measured accurately so that very small capacitors can be used in the SAR ADC due to the relaxed matching requirement. A modified bit-cycling procedure is developed to avoid the code gaps caused by capacitor dithering. This calibration technique requires no analog calibration overhead and simple digital decoders. The technique is implemented in an ADC array design including 256 SAR ADCs for a high-speed CMOS imaging sensor in a 0.18-μm CMOS process. The 10-b SAR ADC is designed with the minimum capacitor array size in the process. A single SAR ADC only occupies 15 μm × 710 μm. Sampling at 768 kS/s, peak DNL and peak INL of the original ADCs averaged across the array are 0.82 least significant bit (LSB) and 3.85 LSB, respectively. For a signal close to the Nyquist frequency, original ADCs have 7.96-b average ENOB. After calibration with dithering, ADCs have 0.55-LSB peak DNL and 0.77-LSB peak INL averaged across the array. The average ENOB improves to 9.83 b. Compared with the benchmark 10-b SAR ADCs, this design is the most area-efficient design. In this work, the calibration decoders are implemented off-chip. With a sample-and-hold amplifier, the calibration method can run in the background.

Unequal error protection scheme based hierarchical 16-QAM for 3-D video transmission

In this paper, an unequal error protection (UEP) scheme based on hierarchical quadrature amplitude modulation (HQAM) for three-dimensional (3-D) video transmission is proposed. The proposed scheme exploits unique characteristics of the color plus depth map stereoscopic video, where the color sequence has a more significant impact on the reconstructed video quality. The UEP scheme assigns more protection to the color sequence than the depth map so as to achieve high quality 3-D video. Different levels of protection are assigned through hierarchical 16-QAM. The color data with high priority (HP) are mapped onto the most significant bits (MSBs) of the 16- QAM constellation points and the depth map with low priority (LP) are mapped onto the less significant bits (LSBs). Simulation results demonstrate that the proposed UEP scheme outperforms the conventional equal error protection (EEP) schemes by up to 5 dB in terms of the received left and right views quality.

Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2m)

In this paper, a novel architecture for a versatile polynomial basis multiplier over GF(2m) is presented. The proposed architecture provides an efficient execution of the Most Significant Bit (MSB)-First, bit-serial multiplication for different operand lengths. The main advantages of the proposed architecture are (a) its flexibility on arbitrary Galois field sizes, (b) its hardware simplicity which results in small area implementation, (c) low power consumption by employing the gated clock technique (d) improvement of maximum clock frequency due to the lessening of critical path delay. These abilities are achieved by means of utilizing a row of tri-state buffers and some control signals along with the (MSB)-first multiplier in a particular architecture. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency, critical path) and space (gate-latch number) complexity.

A simple delay-line 4-PPM demodulator with near-optimum performance

We describe a simple 4-PPM demodulator that uses analog delay lines and simple 1-bit comparators to determine the least-significant bit and most-significant bit of the 4-PPM encoded data without additional digital signal processing. We show that with good optical filtering the comparator-based demodulator can theoretically operate with sensitivity only 0.23 dB from the optimum 4-ary receiver. We describe as an example of this approach the demodulator built for the Lunar Laser Communication Demonstration and show measured performance within 1.1 dB of the expected sensitivity. The technique is extendable to higher-order, and higher-symbol-rate orthogonal modulation formats.

Properties of Images in LSB Plane

Each pixel of an Image (assuming 24 bit BMP) is stored in the three 8 bits corresponding to three colors. Bit Plane Slicing is the technique of breaking image into 8 planes corresponding to 8 different bit positions. The bit plane image corresponding to the plane of the most significant bit (MSB) has the maximum contribution to the total image and forms the majority of the visually significant image data and planes corresponding to other lower bit positions contribute only the subtle details of the image. And the bit-plane image corresponding to the LSB of the RGB value has the minimum contribution of only 1 out of total of 255 Intensity level to the total image. In spite of this the LSB Plane of the image is not insignificant. In fact it is used in Image Steganography for hiding secret information in the images. Image based Steganography is a potent tool used by Terrorists and Criminal organizations for securely broadcasting, dead-dropping and communicating malicious secret messages over the internet by hiding them in the images. Our cyber space is full of such mala-fide images containing hidden secret information. The most difficult aspect of tracking such malicious images is the lack of efficient and fast algorithms for identifying and isolating them from the bulk of innocent images. Analysis of the pixels in the LSB Plane of the image is very effective technique of identification of Distributing Spatial Domain Steganographic Algorithms. In this paper the properties of Information Pixels pixel present in the LSB Plane of any stego image generated by Distributing Algorithms is analyzed in detail. These properties will be very useful in identification of malafide stego images lurking in our cyber space. All the images and tables used in this paper are generated using MATLAB ©Image Processing Tool Box.

SPIHT-based joint image compression and encryption

A joint of image encryption and compression is investigated, and a novel joint encryption and compression scheme is proposed. In our scheme, the encryption process is performed before compression. Making use of the properties of discrete wavelet transform (DWT) and Set Partitioning in Hierarchical Trees (SPIHT) coding, confusion is restricted to the interior of single subband image itself and so image details are retained. Furthermore, diffusion preserves the two most significant bits (MSBs) and the sign bit, which contain important information about the image. The experiments show that the proposed algorithm possesses a good visual quality of the reconstructed image and a high encryption speed.

A New Reduced Multiplication Structure for Low Power and Low Area Modified Booth Encoding Multiplier

This paper propose a new method for adding of sums and carries at the final stage of the Modified Booth Encoding (MBE) multiplier. In a conventional multiplier final stage, i.e carry propagate adder is used to add sums and carries. After partial product reduction these sums and carries are generated. In this method Carry Save Adder (CSA) is used to reduce the partial products generated by encoder and decoder. The carry generated by a column is fed to the input of a first adder of the next column on left side of the CSA and so on for few columns on Most Significant Bit (MSB) side. Due to removal of the few Adders, the proposed MBE 8x8 multiplier consumes less power, occupies less area, and operates at low voltages i.e at 1.0V. H-Spice is used to carry out the results for 180nm CMOS technology.

Several Classes of Codes and Sequences Derived From a $\BBZ_{4}$-Valued Quadratic Form

Let m and k be positive integers with m/gcd(m,k) being odd, for a ∈ R and b ∈ L, the exponential sum Σx∈LiTr(ax+2bx2k+1) is studied systematically in this paper, where i=√(-1), R = GR (4,m) is a Galois ring, L is the Teichmuller set of R and Tr(·) is the trace function from the Galois ring R to Z4. Through the discussions on the solutions of certain equations and the newly developed theory of Z4-valued quadratic forms, the distribution of the exponential sum is completely determined. As its applications, we can determine the Lee weight and Hamming weight distributions of a class of codes Ck over Z4 and the correlation distribution of a quaternary sequence family Uk, respectively. Furthermore, the Hamming weight distributions of the binary codes obtained from Ck under the most significant bit (MSB) and Gray maps are also determined. For the MSB map sequences of Uk, the nontrivial maximal correlation value is given and the correlation distribution is determined for the Gray map sequences of Uk. It should be noted that the distribution of the exponential sum for the case gcd(m,k) ≠ 1 is obtained for the first time, and then the corresponding codes and sequences are novel.

An image authentication method by applying Hamming code on rearranged bits

In 2007, Chan and Chang proposed an image authentication method using the Hamming code technique. The parity check bits were produced from pixels by using the Hamming code technique, and the produced bits were embedded in other pixels. When recovering, the method had to predict the value of the most-significant bit of each tampered pixel first. Then, the tampered pixel was able to be recovered by referring to the predicted bit and its parity check bits. However, using the most-significant bit is unsuitable because of the risk of making an incorrect prediction. In this paper, the parity check bits are produced from pixels whose bits have been rearranged. This way, the value of the most-significant bit of each tampered pixel can be determined according to its parity check bits. The recovery procedure is also modified to accommodate the rearranging procedure. The experimental results show that the proposed method has a better ability to recover the tampered areas, compared with Chan and Chang’s method. Moreover, the quality of the authenticated images of the proposed method is also higher than that of Chan and Chang’s method.

Approximate Integer Common Divisor Problem Relates to Implicit Factorization

In this paper, we analyze how to calculate the GCD of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> ( ≥ 2) many large integers, given their approximations. This problem is known as the approximate integer common divisor problem in literature. Two versions of the problem, presented by Howgrave-Graham in CaLC 2001, turn out to be special cases of our analysis when <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> = 2. We relate the approximate common divisor problem to the implicit factorization problem as well. The later was introduced by May and Ritzenhofen in PKC 2009 and studied under the assumption that some of Least Significant Bits (LSBs) of certain primes are the same. Our strategy can be applied to the implicit factorization problem in a general framework considering the equality of (i) most significant bits (MSBs), (ii) least significant bits (LSBs), and (iii) MSBs and LSBs together. We present new and improved theoretical as well as experimental results in comparison with the state of the art work in this area.

A Two-Step CORDIC Rotation Algorithm with Pre-Coded Scale Factors

CORDIC algorithm has been widely used for efficient implementation of vector rotation operations in hardware.However,it's hard to achieve small iteration numbers while not compromising the ease of scale factor computing and compensation.This paper proposes a novel table-driven CORDIC rotation algorithm with predictable scale factors and short pipelines.It maps the input angle during into and generates signals to modify the initial iteration value and control the rotation direction.The rotation process is composed of two steps.The coefficients and scale factors of step1 are acquired through lookup table indexed by the MSB(Most Significant Bits) of the mapped angle.After large-angle rotations of step1,the residual angle is brought into the convergence region of step2.The iteration of step2 is scaling-free,with the coefficients directly gotten from the binary representation of the residual angle.During such two processes,no further arithmetic computation in the angle approximation(z datapath) and scale factor computing datapath is required.The coefficients of step1 are generated by our angle decomposition algorithm,with two coefficients in one group,at most one non-zero value each group,and the scale factors are pre-computed and coded with radix-4 Booth recoding algorithm.In addition,some adjacent simple micro rotations are combined into one.All these techniques effectively reduce the iteration number,which is also beneficial to high accuracy due to less rounding errors.Moreover,the algorithm uses carry-save adders to accumulate three operands and omits expressions of machine zero,which reduces the latency and complexity of the system greatly.The MSB indexed lookup table gets over the poor scalability of full-word indexed lookup table,and entries grow slowly with accuracy.When using 28-bit datapath,the algorithm requires 38% less pipeline stages and 27.9% less area consumption compared to those of the conventional CORDIC,while achieving 3 more bits accuracy,which shows great performance superiority.

Bucket attack on numeric set watermarking model and safeguards

Numeric set watermarking is a way to provide ownership proof for numerical data. Numerical data can be considered to be primitives for multimedia types such as images and videos since they are organized forms of numeric information. Thereby, the capability to watermark numerical data directly implies the capability to watermark multimedia objects and discourage information theft on social networking sites and the Internet in general. Unfortunately, there has been very limited research done in the field of numeric set watermarking due to underlying limitations in terms of number of items in the set and LSBs in each item available for watermarking. In 2009, Gupta et al. proposed a numeric set watermarking model that embeds watermark bits in the items of the set based on a hash value of the items’ most significant bits (MSBs). If an item is chosen for watermarking, a watermark bit is embedded in the least significant bits, and the replaced bit is inserted in the fractional value to provide reversibility. The authors show their scheme to be resilient against the traditional subset addition, deletion, and modification attacks as well as secondary watermarking attacks.In this paper, we present a bucket attack on this watermarking model. The attack consists of creating buckets of items with the same MSBs and determine if the items of the bucket carry watermark bits. Experimental results show that the bucket attack is very strong and destroys the entire watermark with close to 100% success rate. We examine the inherent weaknesses in the watermarking model of Gupta et al. that leave it vulnerable to the bucket attack and propose potential safeguards that can provide resilience against this attack. Categories and subject descriptors[intellectual-property protection]