A nanoscale MOS transistor possessing an embedded SiO2-Si-SiO2 quantum well serving as source-drain channel is presented. To examine the influence of significant variables on discrete quantum energy levels, band gap, and optoelectronic characteristics of the electrical potential distribution through the channel, an advanced numerical model has been designed. Since the channel thickness – the key parameter for the light emission wavelength – is not always uniform between devices in the same fabrication batch, we propose using activation voltages to compensate for manufacturing errors in the Si-SiO2 interfaces of the quantum well. The expected benefits include the control of light emission through electrical voltages (VGS, VDS) and the channel thickness (tSi), the mitigation of parasitic currents through the insulation buried oxide layer, and a completely VLSI-compatible design for swift industry integration based on Si and SiO2. Through calculating the eigenvalues’ distribution along the channel length (L), we argue that electrical compensation of Si layer process mismatch can modulate the inter-sub-band transitions (ISBT) when applying adequate activation voltages. This is of particular importance for long (L) and large (W) channel transistors, as it is necessary to ensure a significant quantity of hot electrons for triggering the ISBT efficiently.

Abstract Current-voltage (I−V) characteristics of the npn structures used in vertical GaN trench metal-insulator-semiconductor field effect transistors (MOSFETs) were measured and analyzed. The shape of the measured I−V curves was found to be similar to the reverse I−V characteristics of the GaN p-n diodes. By analyzing the results using simulations, the I−V characteristics could be explained by band-to-band tunneling and the avalanche breakdown. The estimated acceptor concentrations by comparing the measured and the simulated I−V curves were relatively high, suggesting that the low threshold voltage of the GaN trench MOSFETs is not due to insufficient activation of Mg.

Circuit-level SPICE analysis of analog blocks in 28-nm bulk CMOS at doses approaching 1 Grad remains under-served. Device-centric characterizations and charge-based formalisms developed within TCAD rarely propagate into production EDA flows, leaving a lack of compact, SPICE-deployable models that represent radiation-induced degradation with sufficient fidelity and workflow alignment. BSIM RAD is proposed as a compact model base on BSIM that encapsulates Total Ionizing Dose damage by recasting oxide- and interface-trap contributions into an effective gate-oxide capacitance per unit area (C^'OX). The implementation is native to Cadence Virtuoso/Spectre, enabling drop-in use within standard verification setups. Calibration against measurements from 0 rad to 1 Grad covers nMOS/pMOS devices across distinct W/L sets and multiple V_DS values. Across this device matrix, the model reproduces the fractional shift in V_TH with sub-percent error and matches irradiated I_DS-V_GS characteristics within 2σ of the data, preserving the polarity-dependent displacement. The approach captures TID behavior to 1 Grad and beyond while maintaining parameter identifiability and CAD/EDA portability, closing a practical gap for global SPICE verification of radiation-tolerant analog circuits in 28-nm CMOS.

Negative capacitance double-gate junctionless MOS transistor for biosensing applications

Design of electronically tunable fractional-order elements based on distributed MOS transistor structures.

This paper presents a novel, minimalist floating memristor emulator circuit designed for low-power biomedical analog front ends. The proposed topology requires only two dynamic threshold MOS (DTMOS) transistors and one capacitor, constituting one of the most compact memristor emulators reported. The circuit operates without static power consumption and exploits the body-effect coupling in DTMOS devices to generate a state-dependent resistance. Comprehensive simulation in a 0.18 μm CMOS process verifies core memristive characteristics: a frequency-dependent pinched hysteresis loop tunable via capacitance, non-volatile memory, and robustness across temperature and process variations. Experimental validation using a discrete CD4007-based prototype confirms the pinched hysteresis loop from 100 Hz to 800 kHz, with a maximum simulated operating frequency of 500 MHz. A comparative analysis demonstrates that the design achieves a favorable trade-off, simultaneously minimizing transistor count and power while providing floating operation and high-speed performance. These attributes make the emulator a compelling candidate for integration into adaptive, area and power constrained biomedical signal conditioning systems.

ABSTRACT This paper presents a low‐voltage, low‐power second‐generation voltage conveyor (VCII) that achieves enhanced bandwidth and reduced power consumption. The proposed VCII employs dynamic threshold MOS (DTMOS) technique to operate under reduced supply voltages, while resistive compensation is incorporated to extend the bandwidth. Two novel memristor emulator designs are introduced based on the proposed VCII. The grounded memristor emulator utilizes a single VCII, a resistor, a capacitor, and an NMOS transistor, whereas the floating emulator configuration employs two VCIIs, a resistor, and an NMOS transistor. The proposed VCII achieves a bandwidth of 325 MHz, an output impedance of 38 Ω at terminal Z , and a power consumption of 0.068 mW. Simulation results further demonstrate that the proposed grounded and floating memristor circuits exhibit distinct pinch hysteresis loops (PHL) in the voltage–current plane up to a frequency of 80 MHz and 1.5 GHz and power consumption of 0.12 and 0.25 mW, respectively. The designs have been validated using 180 nm CMOS technology parameters, operating at a low DC supply voltage of ±0.45 V. Both proposed memristor designs show robust and satisfactory performance across a wide frequency range. The layout and postlayout simulation results of the proposed VCII and both memristor emulators have also been carried out, occupying areas of 2116.13, 2205.02, and 4759.53 μm 2 , respectively. In addition, the process corner simulation of the proposed memristor is also included. The practical relevance of the memristor is demonstrated through the successful realization of low‐pass, high‐pass, and band‐pass filter circuits, highlighting their suitability for next‐generation memristive computing.

The introduction of high-k/metal gate (HK/MG) technology enables independent tuning of N-type metal−oxide−semiconductor (NMOS) and P-type metal−oxide−semiconductor (PMOS) threshold voltages, facilitating advanced nodes and improving overall chip performance. However, severe pattern loading effects during PMOS device fabrication pose challenges in dummy poly removal. This work reports the optimization of the photoresist etch back (PREB) process, providing a wider process window for subsequent AL CMP. By tuning the PR coating uniformity to 1.6% and applying four-zone electrostatic chuck (ESC) temperature control, the wafer-level uniformities of PR, SiN, and SiO2 were reduced to 6.3%, 2.3%, and 5.1%, respectively. An optimized over etch (OE) recipe with a high selectivity of PR : SiN : SiO2 ≈ 1 : 1 : 6 effectively balanced gate height loading between N- and PMOS regions. Furthermore, precise EB1 time tuning enabled defect removal, while advanced KLA inspection ensured early detection of critical failure modes. Collectively, these measures establish a robust and stable PREB process for advanced logic device fabrication.

This paper proposes a corner analysis approach for CMOS circuits taking into the account radiation effects. The presented simulation approach is implemented using the open-source design automation (EDA) software QUCS-S 25.2.0 and Ngspice 45. It was developed a radiation-sensitive field-effect transistor (RADFET) SPICE macromodel representing threshold voltage shift versus radiation dose. The extraction procedure for this model is based on statistical measurements of pMOS transistors and process corner models (Slow, Typical, Fast) and involves percentile analysis. The article proposes an original design of the RADFET-based radiation sensor with RADFET device and CMOS readout circuit placed on the same die, which allows us to simplify the dosimeter schematic. The sensor output parameter dependency on process parameters, supply voltage, and temperature was investigated using the proposed simulation approach.

This paper proposes a low-offset balanced inverter that forms a push-pull structure using two composite transistors. Each composite transistor operates as either a current-sourcing or a current-sinking device, and can replace both the PMOS and NMOS transistors in a CMOS inverter. The symmetry between the pull-up and pull-down paths achieves a very low offset, enabling the implementation of a single-ended, lossless integrator without requiring any offset cancellation. The proposed balanced inverter is applied to realize a second-order delta-sigma ADC that digitizes the integration of extremely weak input currents from the resistor. Experimental results from the fabricated chip demonstrate that the resistor measuring ADC achieved a 0.4-Ω resolution over 106-dB dynamic range, confirming its practical applicability despite the process and temperature variations.

Two-dimensional (2D)transition metal dichalcogenides (TMDs) arepreponderant candidates for advanced nanoelectronics owing to theiratomically thin body, which could enable excellent electrostatic control.High current density NMOS transistors have been demonstrated withsemimetal Bi and Sb contacts. Both these semimetals have low meltingtemperatures and thus limit their integration flow compatibility withthe modern integrated circuit technologies. Integration of those metallayers requires exposing the transistors to 400 °C H2 environment for extended periods of time. Using a Bi confinementstrategy through AlOx and/or TiN barriers, RC values below 200 Ω·μm aredemonstrated while preserving device performance after forming gasannealing at 400 °C for up to 10 min; this finding is validatedthrough the characterizations of multiple devices. Furthermore, byusing fab-like SiO2 trench structures with TiN barrierand W plug in addition to the Bi, we confirm the thermal stabilityof the structures. The thermal stability is found to be good at 400°C under several process environments, such as N2,forming gas, and vacuum. Cross-sectional TEM and EDX confirm thatBi contacts remain fully confined without diffusion or outgassing,establishing the process compatibility of this confinement method.This study establishes a fab-compatible confinement strategy thatenables low RC monolayer MoS2 transistors while maintaining thermal robustness.

The integration of both memory and computation within memristive devices has emerged as a promising approach in the domain of in-memory computing (IMC). Among various architectures, memristor-based crossbars offer high packing density, scalability, and compatibility with CMOS technology, enabling not only dense storage but also efficient implementation of Boolean logic functions. Majority logic, in particular, has shown superior efficiency over conventional logic primitives across several nanotechnologies. This work presents an adder design leveraging the majority logic function (MJF), including the realization of a full adder and a ripple carry adder directly within the IMC framework. The design assumes the availability of both nominal and complementary input data within the crossbar, allowing computation to be performed entirely in memristors. To mitigate the sneak path problem and associated read disturbances, we employ a one-transistor-one-memristor (1T1R) crossbar structure using 45 nm nMOS transistors in conjunction with the VTEAM memristor model. Furthermore, we propose a resource-constrained mapping technique for implementing arbitrary logic functions using MJF within the 1T1R crossbar. Simulation results demonstrate substantial performance gains, achieving up to 90% reduction in computation steps and 70% improvement in memristor utilization compared to existing IMC approaches.

This article is dedicated to the research of methods for enhancing both the energy efficiency and the high-resolution capabilities of Switched-Capacitor (SC) Delta-Sigma (ΔΣ) Analog-to-Digital Converters (ADCs). It is also analyzed and justified why this architecture is chosen for further research. This is achieved by leveraging novel low-power CMOS circuit design techniques, specifically in scaled CMOS technologies. The priorities are high circuit performance, robustness, low manufacturing costs, and a simple design architecture that can be readily reused by the scientific community for validation and further development. The Delta-Sigma architecture was chosen for its inherent simplicity and high tolerance to major analog block non-idealities, such as op-amp finite gain and comparator offsets. The presented study uses switched-capacitor techniques as the core implementation to achieve high-precision matching between devices, resulting in a performance dependency that relies primarily on the external clock jitter rather than absolute component values. The developed low-current analog circuit methods are aimed at maximizing energy efficiency, taking advantage of the weak and moderate inversion regions of MOS transistor operation to optimize transconductance efficiency (gm/ID). New Class-AB operational amplifiers are also explored as active elements that use energy primarily for dynamic transitions, thus reducing static power consumption at the circuit level. Circuits that are not actively used during a certain period of time are dynamically powered down (power-gated), thus reducing overall power consumption at the system level and minimizing the number of switching devices in the critical signal path. Circuit reliability is improved by deliberately avoiding bootstrapping or other methods that could increase the operating voltage above the nominal power supply. This design choice prevents oxide overstress and enhances the long-term reliability of the target CMOS technology. The study also examines circuit topologies that remain relatively stable across process and temperature variations. Increased stability means better manufacturing yield and fewer inconsistencies between simulated and measured results. Taken together, these design decisions allow the converter to achieve better precision and efficiency without resorting to complex timing schemes, background calibration, or digital post-processing. This makes the proposed techniques suitable for a variety of intelligent sensor systems, including pressure and temperature measurement applications.

This study demonstrates drift-assisted positron annihilation lifetime spectroscopy on a p-type (100) silicon substrate in a MOS capacitor, using an applied electric field to control the spatial positron distribution prior to annihilation. The device was operated under accumulation, depletion, and inversion conditions, revealing that the internal electric field can drift-transport positrons either toward or away from the SiO2/Si interface, acting as a diffusion barrier or support, respectively. Key positron drift-transport parameters were derived from lifetime data, and the influence of the non-linear electric field on positron trapping was analyzed. The comparison of the presented results to our previous oxide-side drift experiment on the same metal-oxide–silicon capacitor indicates that the interface exhibits two distinct sides, with different types of defects: void-like and vacancy-like ( centers). The positron data also suggest that the charge state of the centers likely varies with the operation mode of the MOS, which affects their positron trapping behavior.

This paper reports the results of a system-level total ionizing dose (TID) effect simulation study on a SMIC 130 nm LEON2 processor. Firstly, the device-level simulations of the 130 nm NMOS transistors are performed using the Sentaurus TCAD software to analyze the effects of a bias condition, channel width, and irradiation dose on a TID-induced leakage current. Based on the TCAD simulation results, a Verilog-A-based compact model is developed for NMOS transistors to describe the TID-induced leakage current, and it is then embedded into target nodes of the SPICE netlist for the LEON2 processor, enabling system-level TID simulations. The simulation results reveal the processor’s failure threshold and corresponding failure mechanism; meanwhile, the increase in the power supply current with the irradiation dose is also observed. The research reported in this paper can provide beneficial guidance for radiation performance evaluation and radiation hardening by design (RHBD) in 130 nm bulk CMOS processors.

This article proposes a novel memristor emulator design capable of operating in the ultra-high-frequency range. The proposed memristor emulator, implemented using two nMOS transistors and a grounded MOS-capacitor, is designed and simulated in the Analog Design Environment of Cadence Virtuoso using a 90nm CMOS technology. It achieves a maximum operating frequency of 3 GHz, with a power consumption of 13.52 μ<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i>. The robustness of the proposed memristor emulator is validated through extensive simulations, including temperature variations, process corners, capacitance variations, and different combinations. Additionally, short-term non-volatility analysis has been conducted to evaluate its memory characteristics. The layout of the proposed memristor emulator is presented, along with pre-layout and post-layout simulations. Furthermore, hardware validation has been performed using commercial ICs (IRF840). Applications such as an 8:3 encoder, an adaptive neural network, and a ring oscillator circuit using the proposed memristor emulator are also reported in this article. The simulation results confirm that the memristive encoder functions correctly at 2 GHz and the ring oscillator generates an oscillation frequency greater than 2 GHz, demonstrating the emulator’s suitability for ultra-high-frequency applications.

The increasing use of battery-powered and energy-constrained embedded computing systems in deployment in applications like the Internet of Things, wearable electronics, and biomedical devices has provided an urgent and imperative demand to ultra-low-power VLSI circuit design methodologies. Most of the strategies that can be implemented, including sub-threshold operation, in which MOS transistors are operated in the weak field below the threshold voltage, have proved to be very effective in reducing energy consumption by taking advantage of the exponential currentvoltage properties of CMOS devices. In this paper, a systematic exploration of sub-threshold scheme of VLSI circuit design in the quest to attain energy-efficient embedded systems with prolonged life time is presented. The basic details of sub-threshold device modelling, the current conduction physics, and leakage characteristics are studied in order to have a firm theoretical background. The paper also analyses the main issues of design involved in sub-threshold operation such as a high sensitivity to variations in process, voltage, and temperature, reduced noise margins, and performance limits. In order to meet these needs, a number of circuit-level and systems level optimization solutions have been considered, which includes robust logic design, variability based sizing related measures, adaptive biasing and reduction of memory architecture with direct involvement towards ultra-low-voltage work. Specifically, performance and stability levels of the sub-threshold logic styles and the adapted SRAM cells are analysed so that they can be confident of being able to function reliably in the face of extreme voltage scaling. Evaluations of a representative CMOS technology node based on simulations show that power consumption and energy per operation reduction when compared to designs based on traditional super-threshold designs is large, and at lower throughput, performance with embedded workloads remains acceptable. The findings verify that well-selected sub-threshold VLSI circuits could provide substantial improvements in energy efficiency, and they can be used as a promising and scalable solution to next-generation ultra-low-power embedded systems with long battery life and energy independence.

This work presents a new ultra-fast electrical rapid annealing (ERA) technique that successfully recovers devices from total ionizing dose-induced degradation. The electrical rapid annealing technique was successfully demonstrated to be effective on three commercially available FinFET technologies and in Planar PDSOI technology: GlobalFoundries 12 nm (GF12LP and GF12LP+), Intel 16 nm FinFET node, and in 350 nm PDSOI node. ERA demonstrated significant recovery to pre-irradiation parameters such as off-state drain current, on-state drain current threshold voltage, and maximum transconductance. Additionally, reliability assessments and repeated ERA cycles highlight the method’s effectiveness and minimal reliability degradation. FinFET TCAD simulations show that ERA induces higher electric fields within STI regions rather than across the gate oxide, ensuring minimal oxide degradation. The proposed mechanism by which ERA rapidly recovers devices from TID degradation is discussed.

The use of logic circuits combined with emerging devices has been studied to overcome the limitations of complementary metal-oxide-semiconductor (CMOS) transistors. Among a variety of emerging devices, magnetic tunnel junction (MTJ) is a promising candidate owing to its non-volatility, high endurance, and CMOS compatibility. However, process variations in MTJs and CMOS transistors hinder reliable and precise resistance-to-voltage conversion in hybrid MTJ/CMOS logic circuits. To address this issue, this paper proposes a novel separated pre-charge sense amplifier that achieves fast-sensing, low-power, small-area, and high-reliability. The proposed circuit eliminates intermediate inverters between the discharge and evaluation stages. It incorporates P-channel MOS (PMOS) transistors within the inverter latch, whose gates are directly biased by voltages that reflect the resistance difference between a pair of MTJs. It minimizes its nodes to be charged or discharged during operation. Furthermore, it reduces the total transistor count, including clock-driven transistors. Simulations are performed using Cadence and HSPICE tools with the NCSU CMOS 45nm design kit and a physics-based MTJ SPICE model. Monte Carlo simulations are conducted to check the circuit’s reliability under process, voltage, and temperature (PVT) variations. Post-layout simulation results show that the proposed circuit achieves the fastest sensing delay among the compared circuits except for Separated Pre-Charge Sense Amplifier (SPCSA), lowest power consumption, lowest power-delay product, smallest area overhead, and lowest sensing error rate for a viable usage in hybrid MTJ/CMOS logic memory circuits.

As is customary in general automatic control theory, the open-loop system includes all components of resonant DC-DC converters, including the error amplifier and the power stage, except for the summing junction. The paper is devoted to the analysis of the circuitry and operating principles of the control-system components of DC converters, which, unlike the power stage and the error amplifier, have not been comprehensively addressed in the literature. The purpose of study is to analysis of the circuit topology and functional operation of open-loop control system components for resonant DC-DC converters based on commercial integrated circuits implementing frequency and phase control. Materials and methods. The analysis of the circuit design and operation of the resonant converter control system was performed using the circuit diagrams, timing diagrams, and formulas provided in the technical documentation for commercial ICs produced by leading manufacturers. Results. The structural diagrams of open-loop frequency and phase control systems for resonant DC-DC converters are presented and described, along with piecewise time-domain descriptions of their functional blocks. It has been established that all timing generators are based on the charge-discharge principle of a timing capacitor. Frequency control involves varying the switching frequency, while phase control implies shifting the phase of the control pulses of one leg of the half-bridge relative to the other at a fixed switching frequency, which simplifies the control system. Examples of circuit implementations using the UC3865, L6599, and UC3871 integrated circuits are provided, along with a discussion of pulse shaping circuits and the specific features of feedback implementation. Conclusions. The generation of clock pulses in the master oscillators for both frequency and phase control systems of DC-DC converters is performed by cyclic charging and discharging of a timing capacitor, whose parameters determine the output frequency of the system. The phase control scheme contains fewer functional units compared to the frequency control scheme, simplifying its practical implementation. As semiconductor manufacturing technology has advanced, the control ICs have also evolved – from using n-p-n bipolar transistors to hybrid circuits incorporating p-n-p and MOS transistors – which has significantly influenced the circuit design and operation of control ICs for resonant converters.