MOSFET Structure Research Articles

A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference: Design and Application

This paper presents the design and application of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET (SCM) structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. The two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a > 0.18mm standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of ±0.18% from -20°C to 75°C (or less than 15ppm/°C), operates from 3.6V down to 800mV while biased with a 5nA resistor-less PTAT current source that varies ±30% over PVT, and consumes less than 20nA with an area of 0.01mm2. The same concept was used to create a temperature compensated voltage drop with regard to a monitored power supply voltage but using a 2-PMOS SCM structure with transistors of different threshold voltages. These two circuits were adopted as part of a Power Management (PM) system for RFID tag applications. The PM includes a LDO voltage regulator and a low voltage detector that require both the voltage reference and the low voltage monitor. The LDO regulated output voltage and the trip-point of the voltage detector vary +/-5.5% and +/-3.3%, respectively, over temperature, without trimming.

Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog and RF Performance

This paper presents the continuous 2D analytical modelling of electrostatic potential, threshold voltage (Vth), subthreshold swing, drain induced barrier lowering (DIBL) and drain current of asymmetric junctionless dual material double gate MOSFET with high K gate stack (AJDMDG Stack MOSFET). The electrostatic potential is achieved by solving Poisson’s equation with the help of the parabolic approximation method. Analytical results are verified by using ATLAS TCAD Device simulator. A comparative study of short channel effects (SCEs) of AJDMDG Stack MOSFET and asymmetric junctionless dual material double gate MOSFET with high K gate stack (SJDMDG Stack MOSFET) has been observed in order to show the efficacy of asymmetry condition such as gate oxide asymmetry, gate work function asymmetry etc. for suppressing SCEs. Further, analog/RF performance parameters such as transconductance (gm), output resistance (rout), intrinsic gain, transconductance generation factor (TGF), cut-off frequency (fT), maximum frequency (fmax), gain bandwidth product (GBW) etc. of AJDMDG Stack MOSFET are observed and compared the results with SJDMDG Stack MOSFET structure. Results reveal that AJDMDG Stack MOSFET has better efficacy for RF applications.

Reliability enhanced SiC MOSFET with partially widened retrograde P‐well structure

In this Letter, a 1.2 kV SiC power MOSFET with a partially widened retrograde P-well (RP) structure and N -implanting region is proposed to enhance the device's reliability. Compared with the conventional SiC power MOSFET, the short circuit (SC) ability of the proposed structure can be improved effectively without sacrificing other performance. Simulation results reveal that a 40% reduction of the SC saturation current can be achieved, resulting in the SC withstand time increase from 7 to 10 μs at the DC-link voltage 800 V. Moreover, a better gate oxide reliability at 1.2 kV blocking condition also can be achieved. The peak electric field at the gate oxide interface is decreased by ∼48% owing to the shielding effect of the RP structure. In addition, the fabrication technology of the proposed structure is compatible with the standard planar SiC MOSFET manufacture process only with a few additional implanting steps. Therefore, this new MOSFET structure provides a simple and effective way to optimise the reliability of the planar SiC power MOSFET.

A 2D Analytical Modeling and Simulation of Double Halo Triple Material Surrounding Gate (DH-TMSG) MOSFET

In the nanoscale regime, scaling is the driving force for the miniaturized device applications. Many devices are scaled in size and performance analyses are measured. The scaling of MOSFET leads to the introduction of short channel effects. As the devices are scaled, the magnitude of these short channel effects hinders the performance of the device. In order to minimize these effects, gate engineering and channel engineering are performed. The modification in the gate material is pronounced as gate engineering and the changes in the doping concentration lead to channel engineering. In this paper, a combination of gate and channel engineering is utilized to reduce the short channel effects. A device called double halo triple material surrounding gate(DH-TMSG) MOSFET is introduced for the first time and its 2D analytical model is derived. The performance of the device is analyzed using TCAD ATLAS simulation tool. It has been found from the simulation results that DH-TMSG structure of MOSFET produce the ION current of 10−3A/μm and IOFF current of 10−12A/μm which proves to reduce the leakage current.

4H-SiC UMOSFET With an Electric Field Modulation Region Below P-Body

In this article, we investigate a novel optimized 4H-SiC U-shaped trench-gate MOSFET (UMOSFET) structure, which features an electric field modulation region below the P-body. This region consists of a p-type region and an n-type region, while the p-type region is wrapped by the n-type region. We use the p-type region to reduce the electric field at the P+ shielding layer and the gate oxide. The reduced electric field increases the breakdown voltage (BV) of the optimized UMOSFET substantially. The n-type region can also improve the ON-state characteristics of the UMOSFET. Under the combined action of the p-type region and the n-type region, the BV and figure of merit increased by 25.2% and 120.5%, respectively. Moreover, the specific ON-resistance dropped by 40.8%.

Sensitivity Analysis of the UTBSOI Transistor based Two-Stage Operational Amplifiers

In the nanoscale domain, the MOSFETs are prone to various physical effects due to their shorter channel region known as short-channel effects (SCE). The researchers have proposed an advanced structure of MOSFET known as the ultrathinbody silicon-on-insulator (UTBSOI) to overcome the limitations of SCEs. The UTBSOI is a type of double-gate (DG) MOSFET having superior controllability of gates over the shorter channel region. Nowadays, the UTBSOI MOSFETs can be adopted in the circuit simulators through the use of a device model named BSIM-IMG. The BSIM-IMG has made it possible for the circuit designers to simulate any UTBSOI based analog blocks like operational amplifiers (opamp). The performance parameters of an opamp are very much sensitive to any perturbation in size (W/L) of the constituent MOSFETs, that may cause a drastic change in the output. In this paper, the sensitivity analysis procedure has been proposed for the CMOS and UTBSOI based two-stage opamps as the function of perturbation in W/L. In addition to this, an algorithm has also been presented to do the same. From the simulation results, it is observed that the sensitivity of the UTBSOI based opamp (UTBSOI-opamp) is larger than that of CMOS based opamp (CMOS-opamp).

Heavy-Ion Microbeam Studies of Single-Event Leakage Current Mechanism in SiC VD-MOSFETs

Heavy-ion microbeams are employed for probing the radiation-sensitive regions in commercial silicon carbide (SiC) vertical double-diffused power (VD)-MOSFETs with micrometer accuracy. By scanning the beam spot over the die, a spatial periodicity was observed in the leakage current degradation, reflecting the striped structure of the power MOSFET investigated. Two different mechanisms were observed for degradation. At low drain bias (gate and source grounded), only the gate-oxide (at the JFET or neck region) is contributing in the ion-induced leakage current. For exposures at drain-source bias voltages higher than a specific threshold, additional higher drain leakage current is observed in the p-n junction region. This provides useful insights into the understanding of basic phenomena of single-event effects in SiC power devices.

Design and Simulation Analysis of Vertical Double-Gate MOSFET (VDGM) Structure for Nano-Device Application

Design and simulation analysis of vertical MOSFET structure with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length, L g = 50nm and analyzing its effect towards such small devices was successfully performed. The analysis continued with the comparative investigation of device performance with conventional planar MOSFET as scaling L g down to 50nm. The final part evaluates the innovative design of incorporating dielectric pocket (DP) on top of vertical MOSFET turret with comprehensive device performance analysis as compared to standard vertical MOSFET in nanoscale realm. An optimized body doping for enhanced performance of vertical MOSFET was revealed. The vicinity of DP near the drain end is found to reduce the charge sharing effects between source and drain that gives better gate control of the depletion region for short channel effect (SCE) suppression in nanodevice structure.

A review on performance comparison of advanced MOSFET structures below 45 nm technology node

CMOS technology is one of the most frequently used technologies in the semiconductor industry as it can be successfully integrated with ICs. Every two years the number of MOS transistors doubles because the size of the MOSFET is reduced. Reducing the size of the MOSFET reduces the size of the channel length which causes short channel effects and it increases the leakage current. To reduce the short channel effects new designs and technologies are implemented. Double gate MOSFET design has shown improvement in performance as amplifiers over a single MOSFET. Silicon-based MOSFET design can be used in a harsh environment. It has been used in various applications such as in detecting biomolecules. The increase in number of gates increases the current drive capability of transistors. GAA MOSFET is an example of a quadruple gate around the four sides of channel that increases gate control over the channel region. It also increases effective channel width that improves drain current and reduces leakage current keeping short channel effects under limit. Junctionless MOSFET operates faster and uses less power with increase in ON-state current leading to a good value of ION/IOFF ratio. In this paper, several gate and channel engineered MOSFET structures are analyzed and compared for sub 45 nm technology node. A comparison among different MOSFET structures has been made for subthreshold performance parameters in terms of IOFF, subthreshold slope and DIBL values. The analog/RF performance is analyzed for transconductance, effective transistor capacitances, stability factor and critical frequency. The paper also covers different applications of advance MOSFET structures in analog/digital or IoT/ biomedical applications.

High Threshold Voltage Normally off Ultra-Thin-Barrier GaN MISHEMT with MOCVD-Regrown Ohmics and Si-Rich LPCVD-SiNx Gate Insulator

A high threshold voltage (VTH) normally off GaN MISHEMTs with a uniform threshold voltage distribution (VTH = 4.25 ± 0.1 V at IDS = 1 μA/mm) were demonstrated by the selective area ohmic regrowth technique together with an Si-rich LPCVD-SiNx gate insulator. In the conventional GaN MOSFET structure, the carriers were induced by the inversion channel at a high positive gate voltage. However, this design sacrifices the channel mobility and reliability because a huge number of carriers are beneath the gate insulator directly during operation. In this study, a 3-nm ultra-thin Al0.25Ga0.75N barrier was adopted to provide a two-dimensional electron gas (2DEG) channel underneath the gate terminal and selective area MOCVD-regrowth layer to improve the ohmic contact resistivity. An Si-rich LPCVD-SiNx gate insulator was employed to absorb trace oxygen contamination on the GaN surface and to improve the insulator/GaN interface quality. Based on the breakdown voltage, current density, and dynamic RON measured results, the proposed LPCVD-MISHEMT provides a potential candidate solution for switching power electronics.

Intrinsic Voltage Gain of Stacked GAA Nanosheet MOSFETs Operating at High Temperatures

In the semiconductor industry, the scaling down of devices has always been the driver in order to improve circuit area efficiency and high current drive, leading to the triple gate FinFET, which is the newest technology for high performance applications. However, it is believed that these devices cannot reach the sub 7 nm nodes and the GAA nanowires MOSFETs has emerged as one of the most promising candidates for this technology node, as it presents high density of integration and higher electrostatic control between gate and channel (1-2).The studied devices are GAA silicon nanosheet MOSFETs, fabricated at Imec, Leuven – Belgium, with two stacked channels with the vertical distance between the sheets of 7.5 nm, an EOT of 0.9 nm, a width of 15 nm and a channel length varying from 200nm down to 28nm.The threshold voltage (VTH) as a function of temperature is presented in figure 1, in which it is possible to observe that, VTH is reduced (in absolute value) for both n- and pMOS as temperature increases due to the fermi potential reduction. The VTH variation rate for these devices shows to be better when compared to other technologies, presenting a variation around -0.64 mV/ºC for the p-type, and -0.4 mV/ºC for the n-type, while planar fully depleted SOI devices reach around -0.8 mV/ºC (3), junctionless FinFETs can achieve around -0.94 mV/ºC (4) and bulk nFinFETs present values around -0.67 mV/ºC for narrow fins and -0.92 mV/ºC for wide ones (5).It is possible to see that the subthreshold swing (SS) values (figure2) are very close to the theoretical limit for the MOS technology, except for 28nm channel length pMOS devices, indicating that pMOS is more susceptible to short channel effects (SCEs) than the nMOS counterpart.In figure 3, the Drain Induced Barrier Lowering (DIBL) degrades when the temperature increases. DIBL degradation for both n- and pMOS with temperature are very similar, showing a variation rate of 0.11 mV/V.ºC. It is also important to note that although DIBL is affected by the temperature, the obtained values (except for L=28nm) are very small reaching in the worst case 50mV/V at 200ºC.The transconductance (gmsat) and output conductance (gd) on saturation region of n-type and p-type, showed in figure 4, decreases with increased temperature mainly due to the carrier mobility degradation. Although the gd degradation for L=28nm occurs for both caused by the channel length modulation, the p-type device presents a higher degradation in all range of temperature due to the gate to channel electrostatic coupling as already observed in the SS behavior (figure 2).The intrinsic voltage gain (AV) does not change significantly with temperature due to the compensation between the gm degradation and gd improvement as shown in figure 4. Long p-channel devices present higher Av (gm/gd) than n-type GAA FETs due to the smaller values of gd which is not compensated by the gm degradation. However, for short devices the higher gd degradation results in smaller Av. As said before, AV is calculated considering gmsat and gd and both depend on the mobility, so it is possible to note that AV is barely affected by temperature. Other important highlight is the obtained AV values for the studied GAA MOSFETs that are very high considering other multiple gate MOSFET structures. Both nMOS and pMOS nanosheet devices, with channel length of 100 nm, reach around 42 dB and 50dB respectively, while for bulk FinFETs , junctionless SOI nanowires and W-gate SOI nanowires the values achieved are 34 dB (6), 37 dB (7) and 40 dB (8), respectively, for the same VGT and similar channel length.Even though the longest devices show better SCE immunity and higher AV values, the device with a channel length of 28 nm still shows a good performance. The GAA nanosheet achieves AV of 33 dB and 28 dB, for n and p-type, respectively, while triple gate SOI nanowires, with channel length of 40 nm, and W-gate SOI nanowires, with channel length of 20 nm, presents values around 27 dB (9) and 20 dB (10), respectively. Figure 1

Threshold Voltage Modeling of tri-Gate Schottky-Barrier (TGSB) Field-Effect-Transistors (FETs)

In this work, a threshold voltage model of Tri-Gate Schottky-Barrier (TGSB) MOSFET is presented by coupling threshold voltage models of symmetric and asymmetric double-gate Schottky-Barrier (SB) MOSFET structures giving due weight to each structure. The electrostatic potentials of double-gate SB MOSFETs are obtained using evanescent mode analysis method considering light doping in the channel region. In TGSB MOSFETs, the leakiest path in the subthreshold regime of device operation is located at the mid of the bottom of the channel region. The minimum potential of this leakiest path is considered to be the virtual cathode potential, which is subsequently used to calculate the threshold voltage of the SB MOS devices. The effects of device parameters like oxide thickness, buried oxide (BOX) thickness, channel height, width, and length, doping concentration and Schottky-Barrier height on threshold voltage have been extensively studied in this work. The proposed model results have been verified with numerical simulation results obtained from the 3-D device simulator of Sentaurus TCAD.

Optimization of n-MOS 6T Nanowire SRAM Bit Cell Based on Nanowires Ratio of SiNWTs

In nowadays technology, the primary memory structure widely used in many digital circuit applications is a six transistor (6T) Static Random Access Memory (SRAM) bit cell. The main reason for minimizing memory bit cell to nanodimensions is to provide the SRAM integrated circuits (ICs) with the possible largest memory size per one chip, and the main unit in 6T SRAM bit cell is the MOSFET. One of the new MOSFET structures that overcome conventional MOSFET structure problems under minimization towards nanodimension is the silicon nanowire transistor (SiNWT). This study is the first to explore and optimize the nanowire ratio of driver to load (KD/KL) for a six n-channel SiNWT-based SRAM bit cell. The MuGFET simulation tool has been used to calculate the output characteristics of each transistor individually, and then these characteristics are implemented in the MATLAB software to produce the final static butterfly and current characteristics of nanowire 6T-SRAM bit cell. The demonstration of the driver to load transistors’ nanowires ratio optimizations of nanoscale n-type SiNWT-based SRAM bit cell has been discussed. In this research, the optimization of KD/KL will strongly depend on inflection voltage and high and low noise margins (NMs) of butterfly characteristics. The improvement of NMs of butterfly characteristics has been done by increasing the drain current (Ids) of the driver transistor. Also, the optimization in principle will depend on whether NMs are equal and high, and the inflection voltage (Vinf) is near to Vdd/2 values as possible. These principles have been used as limiting factors for optimization. The results show that the optimization strongly depends on the nanowire ratio, and the best ratio was KD/KL 4. The increase in KD/KL leads to a continuous increase in NMH, acceptable NML and low percentage increment of static power consumption (ΔP %) at KD/KL 4.

A compact model of shield-gate trench MOSFET based on BSIM4

Shield-gate trench MOSFET in a low-to-medium voltage range (12－250 V) plays a key role in the power conversion market due to its low power loss caused by the sheild-gate structure. In order to eliminate the faults resulting from the parasitic effects of the device and improve the conversion efficiency, the device model is indispensable in designing a circuit system. In this paper, a compact model of shield-gate trench MOSFET based on BSIM4 is proposed, including the DC model and the capacitance model. In the DC model, the basic MOSFET structure uses BSIM4, and the equivalent resistances of the basic MOSFET in series are divided into three parts. The equivalent resistance model of JFET region is established by using the electric potential difference between both ends for the first time, and the equivalent resistance model of electron diffusion region is also introduced, in order to solve the problem of current error caused by neglecting the source potential of JFET region. The equivalent resistance between drain and JFET region and the equivalent resistance of electron diffusion region both prove to be constant. In the capacitance model based on BSIM4, the model of shield-gate to drain capacitance is added to the model of drain to source capacitance, and the voltage bias between drain and gate in the model of gate to drain capacitance is modified into the potential difference between the node at the end of the gate-drift overlap region and the gate. Poisson equations are used to solve the electric potential of this node. Furthermore, the gate oxide thickness factor <i>k</i><sub>1</sub>, the shield-gate oxide thickness factor <i>k</i><sub>2</sub>, the equivalent length of gate-drift overlap <i>L</i><sub>ovequ</sub> and the equivalent length of shield-gate <i>L</i><sub>SHequ</sub> are introduced to redefine the position of gate and shield-gate, thereby simplifying the Poisson equations and ensuring the smoothness of the potential curve of the node. Comparison of the data from the simulation by using Verilog-A program with the test results from the experimental platform shows that the model simulation results fit well with the test data, Therefore, the proposed model is verified.

Design and development of a novel MOSFET structure for reduction of reverse bias pn junction leakage current

Design and development of a novel MOSFET structure for reduction of reverse bias pn junction leakage current

TCAD и SPICE-модели для описания радиационных эффектов в наноразмерных МОП-транзисторных структурах

TCAD и SPICE-модели для описания радиационных эффектов в наноразмерных МОП-транзисторных структурах

Novel Isolation Structure for High-Voltage Integrated Superjunction MOSFETs

A novel isolation structure for high-voltage integrated superjunction (SJ) MOSFETs is proposed in this letter. The structure consists of serial lateral SJ diodes with etched underlying n-buffer layers and n-substrates. A theoretical analysis shows that its breakdown voltage is determined by both the number of serial diodes and the doping concentration of pillars. Two SJ MOSFETs of a half-bridge leg can be integrated on a single chip by using the proposal structure. The isolation region for 10 A devices designed with a pillar concentration of $4\times 10^{{15}}$ cm−3 occupies only 2.7% of the chip area. Breakdown initially occurs in the device area. A transient simulation using a resonance circuit reveals that the two SJ MOSFETs can work without interfering with each other.

Simulating the Self-Heating Effect for MOSFETs with Various Configurations of Buried Oxide

SOI MOSFETs have the worst properties of heat removal from an active region, which negatively affects the reliability and efficiency of integrated circuits. Using TCAD modeling, we investigate the self-heating effect in the following structures of deeply submicron MOSFETs with different configurations of buried oxide: traditional bulk MOSFET, SOI structure, SELBOX structure, partial SOI structure, thin-BOX SOI structure, UTBB SOI structure, and quasi-SOI structure. It is shown that, for a number of new designs, the maximum temperature in the MOSFET structure is significantly reduced as compared to Тmax of the standard SOI MOSFET structure; it approaches the values typical of standard MOSFETs on bulk silicon.

Gate Failure Physics of SiC MOSFETs Under Short-Circuit Stress

The unique gate failure mode of SiC MOSFETs is often identified but has not been fully understood yet. In this letter, post-failure cell inspections demonstrate that its main cause is the crack at the SiO2 dielectric layer with melted source aluminum inside. An electro-thermal-mechanical simulation is performed to reproduce the failure transition, and it reveals that the crack forms at an early stage. This new failure mechanism further enlightens on the vulnerability of the vertical power MOSFET structure in extremely high-temperature operation.

Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications

A simple continuous analytical model is developed for the drain current of unipolar junction dual material double gate MOSFET (UJDMDG). The model is based on electrostatic potentials obtained from the solution of Poisson’s equation using parabolic approximation method, surface potential, electric field, threshold voltage roll-off and drain current are explicitly modelled. Analytical results are verified and validated by comparing it with the result obtained from Silvaco TCAD ATLAS device simulator making it suitable for circuit design simulations. A comparative study of the short-channel effects (SCEs) for UJDMDG and unipolar junction single material double gate MOSFET (UJSMDG) structures has been carried out in order to show the efficacy of gate material engineering to suppress SCEs. Moreover, the variation of RF and analog figure of merits as a function of downscaled gate lengths has been reported. To exhibit the superiority in RF/analog performance of UJDMDG over UJSMDG MOSFETs, the analog/RF performance parameters has been studied and compared for SoC applications.