MOS Varactor Research Articles

Modeling and Characterization of VCOs with MOS Varactors for RF Transceivers

As more broadband wireless standards are introduced and ratified, the complexity of wireless communication systems increases, which necessitates extra care and vigilance in their design. In this paper, various aspects of popular voltage-controlled oscillators (VCOs) as key components in RF transceivers are discussed. The importance of phase noise of these key blocks in the overall performance of RF transceivers is highlighted. Varactors are identified as an important component of LC-based oscillators. A new model for accumulation-mode MOS varactors is introduced. The model is experimentally verified through measurements on LC-based VCOs designed in a standard 0.13 µm CMOS process.

Low-K/Cu CMOS-Based SoC Technology With 115-GHz<tex>$f_T$</tex>, 100-GHz<tex>$f_max$</tex>, Low Noise 80-nm RF CMOS, High-Q MiM Capacitor, and Spiral Cu Inductor

Logic CMOS-based RF technology is introduced for a 10-Gb transceiver in which active and passive RF devices have been realized in a single chip. RF nMOS of 115-GHz fT, 100-GHz fmax, and sub-1.0-dB NFmin at 10 GHz have been fabricated by aggressive device scaling and layout optimization. High-Q MiM capacitor and spiral Cu inductors have been successfully implemented in the same chip by 0.13-mum low-K/Cu back end of integration line technology. Core 1.0 V MOS and/or junction varactors for VCO at 10 GHz are offerings free of extra cost and realized by the elaborated layout

Influence of defects in gate-oxide peripheral regions on the electrical characteristics of MOS structures

Radiation-induced defect formation is studied experimentally in the gate-insulator layer and at the semiconductor-insulator interface of NMOS and PMOS structures differing in perimeter-to-area ratio. The structures are fabricated by CMOS technology on the same n-Si wafer, the NMOS structures being formed in a p-well. Heavily phosphorus doped polysilicon and noncrystalline silicon dioxide are used as the gate and insulator materials, respectively. The devices considered are MOS varactors, MOS diodes, and MOSFETs. Capacitance-voltage characteristics are measured on the MOS varactors and diodes. The gate-voltage dependence is examined of surface conduction for the MOSFETs and the surface-recombination emitter-current component for the MOS diodes. The results are used to characterize defect formation in peripheral gate-oxide regions and the lightly doped part of the source (emitter) and the drain, as well as in the central gate-oxide region and at the Si/SiO2 interface. The peripheral oxide regions are found to have a two-sided influence on the performance of the MOS structures. On the one hand, they act as a drain of uncombined hydrogen from the gate oxide, so that the effectiveness of defect deactivation by hydrogen depends on the perimeter-to-area ratio. On the other hand, the peripheral regions, particularly their corners, may have an elevated density of latent process-induced defects that can be activated by radiation, voltage, or thermal stress.

Parametric Conversion Using Custom MOS Varactors

The possible role of customized MOS varactors in amplification, mixing, and frequency control of future millimeter wave CMOS RFICs is outlined. First, the parametric conversion concept is revisited and discussed in terms of modern RF communications systems. Second, the modeling, design, and optimization of MOS varactors are reconsidered in the context of their central role in parametric circuits. Third, a balanced varactor structure is proposed for robust oscillator frequency control in the presence of large extrinsic noise expected in tightly integrated wireless communicators. Main points include the proposal of a subharmonic pumping scheme based on the MOS varactor, a nonequilibrium elastance-voltage model, optimal varactor layout suggestions, custom 0.13 µm-CMOS varactor design and measurement, device-level balanced varactor simulations, and parametric circuit evaluation based on measured device characteristics.

Ultra-Low Voltage Analog Integrated Circuits

The operation of analog circuits from ultra low supply voltages becomes necessary due to semiconductor technology scaling. Yet traditional design techniques cannot be used. In this paper, we review techniques that allow analog circuits to operate with supply voltages as low as 0.5 V. Biasing considerations are given, and robust bias circuits are discussed. For frequency-tunable circuits, a low-voltage MOS varactor tuning technique is presented. The techniques discussed are applied to two different OTA topologies, as well as to an automatically tuned, fifth-order active RC filter. This material is largely based on the work of the authors as described in [1]-[5].

Millimeter-Wave Voltage-Controlled Oscillators in 0.13-<tex>$mu$</tex>m CMOS Technology

This paper describes the design of CMOS millimeter-wave voltage controlled oscillators. Varactor, transistor, and inductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 /spl mu/m result both good quality factor (>12) and C/sub max//C/sub min/ ratio (/spl sim/3) in the 0.13-/spl mu/m CMOS process used for the study. The components were utilized to realize a VCO operating around 60 GHz with a tuning range of 5.8 GHz. A 99-GHz VCO with a tuning range of 2.5 GHz, phase noise of -102.7 dBc/Hz at 10-MHz offset and power consumption of 7-15mW from a 1.5-V supply and a 105-GHz VCO are also demonstrated. This is the CMOS circuit with the highest fundamental operating frequency. The lumped element approach can be used even for VCOs operating near 100-GHz and it results a smaller circuit area.

Notice of Violation of IEEE Publication Principles: A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit

A multi-rate 9.953-12.5-GHz low phase noise LC oscillator was realized in a 90-GHz f/sub T/ 0.2 μm SiGe BiCMOS process. It achieves a 36% tuning range by combining a 35% open-loop frequency calibration range having a sub-0.1% residual error with a 1% closed-loop varactor frequency tuning. The oscillator gain is below 130 MHz/V, while having less than 10% variation over the entire tuning range. The varactor is realized with multiple parallel-connected cells consisting of constant capacitors and voltage-controlled resistors that bring a lower process variation and a higher quality factor in comparison with standard diode and MOS varactors. A dual regulator architecture was used to provide both high PSRR and low output voltage noise. The supply pushing was reduced below 100 kHz/V by using a pushing cancellation circuit that balances the negative and positive voltage coefficients of the different nonlinear capacitors connected to the LC tank. A discrete-time automatic amplitude control loop using a variable tail resistor architecture was implemented to optimize the VCO's phase noise performance. The VCO specifications include 9.953-12.5-GHz frequency range, 0.1% frequency calibration error, -122 dBc/Hz phase noise at 1 MHz offset, <3 kHz 1/f/sup 3/ corner frequency, <-80 dBc spurious tones, 250×400 μm/sup 2/ die area and 5-mA bias current from a 3.3-V supply.

10 GHz Low-Noise Low-Power Monolithic Integrated VCOs in Digital CMOS Technology

This paper presents the design of low-power low-noise 10 GHz CMOS monolithic integrated LC VCOs suitable for data clock recovery architectures in optical receivers of SDH (STM-64) and SONET (OC-192). Optimizations of device parameters and passive components are given in detail. For passive components, differential and single-ended inductor structures as well as MOS varactors with and without lightly doped drain/source (LDD) implantation have been investigated. The VCOs implemented in a 0.18 μm process demonstrate the single-side-band phase noise of as low as -107dBc/Hz at 1 MHz offset and 21% tuning range while consuming only 7 mW under 1.8 V supply.

Implementation of 0.18 μm RFCMOS technology for system-on-a-chip applications

The paper presents a complete portfolio of RF and baseband components by adopting RFCMOS technology for single-chip systems. Using optimised CMOS topology and deep n-well, the performance relates to the ft of 60 GHz and fmax of 53 GHz at 10 mA, an ft of 70 GHz and fmax of 58 GHz at maximum-transconductance bias, and a minimum noise figure of 1.5 dB without ground-shielded signal pad. High quality-factor inductors are obtained using thick copper interconnects; the measurement result demonstrates the corresponding quality factor of 18 at 1.7 nH. The MIM capacitors, as well as accumulation-mode MOS and junction varactors are also optimised for improving quality factor. For the purpose of eliminating inter-block coupling noise penetrating through the substrate, a deep n-well isolation and a p-well guard-ring have been adopted to suppress the substrate noise by 25 dB and 10 dB, respectively.

Full Time-Varying Phase Noise Analysis for MOS Oscillators Based on Floquet and Sylvester Theorems

In this paper a set of full time-varying analyzing methods of phase noise for oscillators based on Floquet and Sylvester theorems are established, it provides a good idea for designing oscillators with perfect phase noise performance. The periodic state solution space of a linear periodic time-varying system is constructed with Floquet and Sylvester theorems, and the phase noise perturbation vectors of an oscillator autonomous system are characterized on this space. The analytical expressions of the phase noise spectrums, both 1/(Δf)2 and Lorentzian forms, are obtained, and the contributions to the phase noise of each noise sources are determined. With a generator approach and some modification, the method could be extended to the flicker noise. For RF front-end oscillators composed of MOS active devices, planar inductors and MOS varactors, the time-varying model parameters of the small signal equivalent circuits are constructed according to the periodic varying working-points. By the means of automatic small-signal equivalent-circuit construction, state-variable selection and periodic time-varying state-matrix generation, the system perturbation vectors and phase noise power spectrums are efficiently calculated. For a 10 GHz MOS oscillator, the 1/(Δf)2 and Lorentzian spectrums are calculated. Comparing with the results of SpectreRF, it indicates the proposed methods are accurate and reliable, especially the Lorentzian spectrum close to the carrier is more reasonable than previous methods. Every noise source contributions to the phase noise are listed and the results are analyzed. At last the applications of the methods to designing low phase noise oscillators and to analyzing the phase noise of composite systems, as well as the difficulty of flicker noise analysis, are addressed.

0.5-V analog circuit techniques and their application in OTA and filter design

We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.

Design of an Optimized 2.5 GHz CMOS Differential LC Oscillator with Nonlinear Analysis for MOS Varactor

The oscillation amplitude and supply current relations for a differential CMOS oscillator are derived by using an analytic method. A simplified model to predict the phase noise performance of the oscillator is developed. The large signal analysis of a nonlinear inversion mode MOS varactor is presented. The derived expressions can help to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the method has been verified by designing an LC CMOS oscillator in a 0.25 ?m CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage.

A Physically Based, Scalable MOS Varactor Model and Extraction Methodology for RF Applications

A physically based scalable model for MOS varactors, including analytical surface potential based charge modeling and physical geometry and process parameter based parasitic modeling, is proposed. Key device performances of capacitance and quality factor Q are validated over a wide voltage, frequency, and geometrical space. The model, implemented in Verilog-A for simulator portability, provides for robust and accurate RF simulation of MOS varactors.

Substrate Voltage and Accumulation-Mode MOS Varactor Capacitance

To adjust the capacitance of an accumulation-mode MOS varactor, a voltage is applied to the drain/source with the gate grounded. In this novel arrangement, a voltage is applied to the gate V/sub gate/ and another to the substrate V/sub sub/ with the drain/source grounded. Applying V/sub sub/ between the p/sup +/-type substrate and the varactor's n-well adjusts the minimum capacitance C/sub min/ and flattens the overall capacitance-voltage (C-V) curve over a wide range of negative V/sub gate/. Measurements show the tuning range using V/sub sub/ to be as wide as that using V/sub gate/. By tuning with V/sub sub/, the capacitance C/sub min/ is constant over a range of negative V/sub gate/. In this region, it may be possible to apply a large ac signal on V/sub gate/ without modulating the capacitance. To illustrate this technique, C-V measurements of a MOS varactor are simulated in a differential LC-tank VCO circuit. Simulations show how adjusting both V/sub gate/ and V/sub sub/ alters the oscillation frequency.

Novel RF Process Monitoring Test Structure for Silicon Devices

This paper demonstrates a novel RFCMOS process monitoring test structure. Outstanding agreement in dc and radio frequency (RF) characteristics has been observed between conventional test structure and the new process monitoring test structure for MOSFET with good correlations in measured capacitances also noted for metal-insulator-metal capacitor and MOS varactor. Possible process monitoring test structure is also suggested as a reference benchmarking indicator for interconnects.

VCO phase-noise improvement by gate-finger configuration of 0.13-/spl mu/m CMOS transistors

Using a standard logic process, 0.13-/spl mu/m RF CMOS devices with multifinger gate structure have been fabricated. The flicker noise and minimum noise figure characteristics have been investigated with different gate layout splits, where the device parasitic resistance is the determining factor in this issue. The stripe-shaped gate configuration demonstrates better noise performance, due to the reduction of device gate resistance. In addition, the MOS varactors designed with different gate layouts were used in a 5.2-GHz voltage-controlled oscillator (VCO) design, where the VCO with the stripe-shaped (2 /spl mu/m /spl times/ 36 fingers) gate varactor improved about 6 dB in phase-noise performance at 100-kHz offset frequency than that of square-shaped (8 /spl mu/m /spl times/ 9 fingers) gate varactor.

Analysis and modeling of LC oscillator reliability

In this paper, MOS device degradations due to hot carrier and gate oxide breakdown are shown experimentally, and their effects on the NMOS LC oscillator have been evaluated analytically and through SpectreRF simulation. The reduction in transconductance of the differential pair transistors may cause the oscillation to cease. The amplitude of oscillation reduces as the equivalent tank resistance decreases due to the breakdown effect on the MOS varactor. The reduction of amplitude reduces the tank capacitances, and therefore shifts the frequency of oscillation and increases the oscillator phase noise. The tank amplitude of the oscillator is derived analytically. A closed-form expression for the average capacitance of the varactor that accounts for large-signal effects is presented. Finally, a set of guidelines to design an LC oscillator in reliability is presented.

Nonlinear transmission lines for pulse shaping in silicon

Nonlinear transmission lines (NLTL) are used for pulse shaping. We developed the theory of pulse propagation through the NLTL. The problem of a wide pulse degenerating into multiple pulses rather than a single pulse is solved by using a gradually scaled NLTL. We exploit certain favorable properties of accumulation-mode MOS varactors to design an NLTL that can simultaneously sharpen both rising and falling edges. There is a good agreement among the theory, simulations, and measurements.

0.13-&amp;lt;tex&amp;gt;$muhbox m$&amp;lt;/tex&amp;gt;RF CMOS and Varactors Performance Optimization by Multiple Gate Layouts

0.13-/spl mu/m radio frequency (RF) CMOS devices with multifinger gate structure have been fabricated by the standard logic process, and the measured effective gate-length is 80 nm. Extensive RF characterization has been done to obtain cutoff frequency (f/sub T/), associated power gain cutoff frequency (f/sub max/), minimum noise figure (NF/sub min/), output power (P/sub out/), and power added efficiency (PAE) for RF circuit design and to explore the optimized gate layout in terms of the extracted RF device parameters. Our important finding to be reported in this paper is that an optimized unit finger width (W/sub F/) exists by trade-off among f/sub T/, f/sub max/, NF/sub min/, P/sub out/, and PAE. Under fixed total width to achieve the same current drivability (I/sub ds/), the smaller W/sub F/ and the larger finger number (N/sub F/) leads to higher f/sub max/ but lower f/sub T/ due to trade-off between gate resistance (R/sub g/) and parasitic gate capacitance. As for NF/sub min/ complicated by f/sub T/ and R/sub g/, counter-balance between parasitic gate capacitance and R/sub g/ leads to nearly constant NF/sub min/ w.r.t. various splits of (W/sub F/,N/sub F/). Regarding P/sub out/ and PAE, W/sub F/ of 4 /spl mu/m and N/sub F/ of 18 is the optimized layout parameter, which offers the maximum P/sub out/ of around 11 dBm and PAE of 30.5% at 5.8 GHz. The performances of accumulation-mode MOS varactors with different gate layout structures are also investigated in this report. Since the same area varactors with different gate layout may result in different parasitic resistance and fringing capacitance, which will affect the capacitance tuning range and the associated Q-factor. The maximum Q-factor is about 59 of the 120 /spl mu/m/sup 2/ gate area varactor, and its tuning range is from 210 fF to 1.64 pF, where the maximum C/sub max//C/sub min/ ratio is about 7.8.

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads).