MOS RAMs Research Articles

Morphology of uranium precipitates in silicon

Soft errors induced by incident alpha particles have been observed in dynamic Metal-Oxide- Semiconductor Random Access Memory (MOS RAMs), charge coupled devices (CCDs), static MOS RAMs and in bipolar RAMS. The focus of attention has been the occurrence of soft errors as a result of alpha particle decay of uranium present even in trace amounts, typically a few ppm (parts per million), in the silicon substrate along with the devices as well as the packaging material. A study of segregation of uranium in silicon is of special interest since a single alpha particle of approximately 40 MeV that has a track length of about 20 μ in silicon can give rise to nearly 106 electron-hole pairs if all the deposited energy is converted to the generation of excess carriers. If these excess carriers are developed in a critical volume depending upon the density of devices in a product, the effect can be large enough to limit the mean time of failure to a few days or weeks for a 64k memory cell. In order to study the diffusion and segregation characteristics of uranium in silicon, uranium was deliberately ion implemented into bare silicon to a dose of 1014/cm2 and subsequently annealed at several temperatures often encountered in device processing. In this paper, we present TEM results especially pertaining to the morphology of uranium precipitates in silicon. Conventional microstructural observations, using bright field (BF) imaging, stereographic projection analysis using electron diffraction patterns, and projected directions of the precipitate with respect to matrix reflection from silicon onto a stereogram, and moire patterns using phase contrast imaging, were used to determine the morphology of fine uranium precipitates in ion implanted and annealed samples.

Holding time distribution in dynamic MOS RAMs

By continuously increasing the period between alternate write and read cycles it is possible to represent the topographic and temporal distribution of failing memory cells of DRAMs. Recording, for example, the first fail bit of each die on a wafer at 85° C, the resulting holding time histogram exhibits a characteristic profile. A failure maximum at low holding times (tH ≲ 40 ms for the 64 K DRAM) is followed by a minimum and then by a second, much more pronounced maximum. Failures up to the leading edge of the second maximum are determined by generation-dependent leakage currents (activation energy EA ≈ 0.55 eV). The position of the second maximum is characteristic of the substrate material and the temperature profile of the overall process. The failure mechanism is determined by diffusion and the temperature dependence of the leakage current is characterized by an activation energy of EA ≈ 1.1 eV. In the 64 K DRAM produced on float-zone silicon, the diffusion current maximum lies between 800–1000 ms a...

Epitaxial layer blocks unwanted charge in MOS RAMs: G. R. Mohan Rao, L. S. White, Jr and Richard N. Gossen Electronics p. 103 (30 June 1981)

Epitaxial layer blocks unwanted charge in MOS RAMs: G. R. Mohan Rao, L. S. White, Jr and Richard N. Gossen Electronics p. 103 (30 June 1981)

A novel associative approach for fault-tolerant MOS RAMs

A novel associative iterative approach providing unique advantages is developed to increase yield of large capacity, 16K bit-1M bit, semiconductor random access memories. The circuit implementation has minimum effect on performance and on the original design of the memory. The increase in access time and power dissipation is less than 2 and 0.6 percent, respectively. The flexibility of this concept allows for organization of redundant elements in blocks, rows, columns, clusters, or bits and to locate the redundancy anywhere on the chip. A wide range of programmable elements, e.g., fusable links, laser programmable cells, and content addressable memory units, are applicable. The amount of spare elements can be optimized to achieve a maximum effective yield of as much as 85 percent. The increase in active circuit area is a function of defect density and memory capacity. The redundancy control and spare memories can be added to memories as modules without modifications of the original designs. The circuits discussed here are for CMOS/SOS radiation hardened application; the concepts, however, can be applied to bulk silicon MOS technologies as well.

Circuit design of dynamic MOS RAM with consideration of soft error

AbstractDynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high‐speed, low soft error rate and low power consumption. As a result of applying it to a 5‐V 16‐K MOS (D) RAM, a performance index of 0.6 pJ/bit and soft error rate of 4 × 107 device. hours are obtained. The adequacy of the modified scaling law is examined by considering a 12‐V 16‐K MOS (D) RAM with scaling constant k = 1 and a 5‐V 16‐K MOS (D) RAM with k = 2. It is shown that circuit design with consideration of soft error cannot achieve large improvement of the performance index of high‐capacity MOS (D) RAM and that the soft error is an impediment to high‐performance MOS (D) RAM.

Epitaxial layer blocks unwanted charge in MOS RAMs: G. R. Mohan Rao, L. S. White, Jr. and Richard N. Gossen. Electronics p. 103 (30 June 1981)

Epitaxial layer blocks unwanted charge in MOS RAMs: G. R. Mohan Rao, L. S. White, Jr. and Richard N. Gossen. Electronics p. 103 (30 June 1981)

"In Situ" Radiation Tolerance Tests of MOS RAMs

To design the 4Mbit Scientific Data Store for the Faint Object Camera of the NASA/ESA space telescope, MOS RAM radiation hardness has been tested extensively. The radiation tolerance of 36 MOS RAM types has been evaluated by "in situ" testing. For comparison, one I2L type was added. The principal aim was the evaluation of failure doses. Beyond that, the impact of technology, storage mechanism, integration density and manufacturer on failure dose and failure mechanism has been studied. The tests have been performed with different test patterns, to ensure the recognition of specific failure types. Various irradiation sources have been used : X-ray tube, Co60-4329515-source and 1.5 MeV electron accelerator. The irradiation procedure and the functional test equipment are described in this paper. The results are presented and discussed. The influence of technological parameters is less pronounced than expected. Highly integrated memories are therefore preferable for those applications, where weight and shielding problems are involved.

Quantitative measurement with high time resolution of internal waveforms on MOS RAMs using a modified scanning electron microscope

The growing packing density of integrated circuits calls, to an increasing extent, for the testing of the functioning of the individual circuits of ICs. If a mechanical prober is used for this purpose, the resulting capacitive loading of the circuit is liable to alter its performance. It is shown in the present work that the electron beam represents an ideal nonloading and nondestructive probe which can be finely focused and positioned on measuring points within the circuit under test. A modified scanning electron microscope allows the recording of waveforms within a circuit with a voltage resolution of the order of 10-100 mV and a time resolution of less than 1 ns. The efficiency of the technique was demonstrated by measuring the internally derived clock pulses and the voltage distributions of a digit-line of a 4096-bit MOS RAM and comparing the results with computer simulations.

Cosmic Ray Induced in MOS Memory Cells

A model for estimating the cosmic ray induced bit error rate in dynamic MOS RAMs is developed and used to calculate the bit error rate in NMDS dynamic RAMs used in an operating satellite system. The calculated error rate agrees sufficiently well with the observed error rate to conclude that cosmic ray ionization is a likely cause of observed satellite bit errors. The susceptibility of M1S RAMs to cosmic ray induced error is a result of the small charge (sub-picocoulamb) typically stored on a MDS gate to represent a data bit. Relatively small energy deposition (a few MeV) can discharge a storage node, resulting in a bit error. The heavy ion particles present in galactic cosmic rays can provide this energy, resulting in a significant bit error rate for large nmeory systems in satellites. The dynamic RAM operational factors and design factors affecting ionization-induced bit error rates are discussed.

An integrated test concept for switched-capacitor dynamic MOS RAM's

An approach to dynamic MOS RAM testing has been developed. This paper deals in particular with the test problems of switched-capacitor (or single-transistor) MOS RAMs. Test procedures are developed from an understanding of the technology with which the memory circuits are built. The associated design weaknesses and failure modes are first reviewed, and four simple pattern-sensitivity programs are generated. Finally, an efficient test flow is recommended for rigorous functional verification as well as design and yield improvements.

Computers: Memories: Smaller, faster, and cheaper: A review of magnetic-bubble, electron-beam-accessed, disk- and tape-file memories; MOS RAMs and CCDs excel

A review of magnetic-bubble, electron-beam-accessed, disk- and tape-file memories; MOS RAMs and CCDs excel.