MOS Gate Electrode Research Articles

CV characteristics of polycrystalline sige films with low GE concentration

SiGe alloys are currently used for HBT and MOS as epitaxial layers for base or strained channel, respectively. In the poly phase, SiGe has been studied as a replacement for poly-Si in MOS gates due to its lower thermal budget and gate depletion and also due to the Workfunction Engineering for Vt adjustments. However, for application to CMOS technology as poly-SiGe gates, others constrains emerge such as quality of the oxide interface and etch chemistry. For both applications, the Ge fraction normally lies between 20% and 40%. In this study, authors use a low Ge contents (1%) poly-SiGe thin films aiming for MOS gate electrode. The Ge fraction was determined by RBS analysis. 230nm thick samples were deposited onto 10nm thermally oxidized 〈100〉, p-type Si substrates using silane and germane. Films were deposited in the temperature of 500°C and total pressure of 667Pa (5Torr) by vertical LPCVD. The samples were doped using 31P+ ion implantation from 5×1014cm−2 up to 2×1016cm−2 and annealed by RTP (40s) from 500°C up to 900°C. Rs values were obtained by 4-point probe technique and CV curves were extracted from nMOS capacitors with 200μm diameter. The same processing steps were used to fabricate similar poly-Si samples and capacitors for comparison.The poly-SiGe samples presented Rs values one order of magnitude lower than poly-Si and CV analysis of nMOS capacitors showed very good characteristics. The 1% Ge in the alloy ensures a low thermal budget for the overall process. Although a relatively high annealing temperature (800°C) must be used to reduce oxide charge and interface traps, the temperature is well below the necessary for poly-Si processing and can allow formation of the shallow junctions needed for next technological nodes.

Electrical and Physical Analysis of MoTa Alloy for Gate Electrode Applications

This article presents as a potential candidate for dual metal complementary metal oxide semiconductor (CMOS) applications. The electrical characterization results of alloy indicates that the effective work function can be controlled to around on and is suitable for n-type MOS gate electrode application. The alloy forms a solid solution instead of an intermetallic compound. We report that the solid solution can achieve low work function values and is stable up to . X-ray diffraction results indicated only a single alloy phase. X-ray photoelectron spectroscopy analysis confirmed that no compound bonding formed within the alloy. Moreover, from Auger electron spectroscopy and Rutherford backscattering spectroscopy analysis, was found to be stable on under high-temperature anneals and no metal diffusion into substrate Si channel was detected. This indicates that is a good candidate for CMOS metal gate applications.

Low electrical resistivity polycrystalline SiGe films obtained by vertical LPCVD for MOS devices

In this study, authors present some morphological and electrical characterization of polycrystalline SiGe thin films (poly-SiGe) deposited by vertical LPCVD using SiH 4, GeH 4 and H 2 mixture in different deposition parameters aiming for MOS gate electrodes. The obtained thin films are very uniform and smooth, with small grain size, feasible to deep submicrom fabrication. The SiGe samples presented resistivity values as low as 0.42 mΩ cm, one order of magnitude lower than poly-Si reference samples. CV and IV measurements points this poly-SiGe as a suitable material for MOS gate electrodes.

Investigation of the Thermal Stability of Reactively Sputter-Deposited TiN MOS Gate Electrodes

The effective work function of TiN, deposited by reactive magnetron sputtering, was found to be unaltered at /spl sim/5 eV after rapid thermal processing (RTP) annealing in nitrogen atmosphere at temperatures below 700/spl deg/C. However, further increase in the RTP temperature lowered the extracted work function by 0.4-0.5 eV to midgap values. In this brief, RTP anneals of TiN/SiO/sub 2//p-Si MOS capacitors were evaluated by extracting the metal gate TiN work function from capacitance-voltage measurements of MOS capacitors with multiple SiO/sub 2/ thicknesses. The RTP anneals were performed in nitrogen between 600/spl deg/C and 1000/spl deg/C for 30 s. The effective oxide charge density in the capacitors increased by a factor of five at RTP temperatures exceeding 800/spl deg/C. The resistivity seems to decrease slightly with increasing RTP temperature. The crystallographic orientation of the TiN films remain (111) after annealing up to 900/spl deg/C and is apparently not responsible for the change in work function. Analysis by X-ray photoelectron spectroscopy indicates no significant change in the binding states of titanium and nitrogen in the TiN/SiO/sub 2/ interface with increasing temperature.

Monolithic bidirectional switch.: I. Device concept

A new device structure is introduced which facilitates the production of monolithic bidirectional switches. Astonishingly enough, the diverse demands on the characteristics can be completely realized by intrinsic silicon exhibiting the only doped zones to form ohmic contacts. Emitters are formed by accumulation layers which are caused by a suited potential on MOS-gate electrodes. This allows to invert the type of charge carriers as is required for bidirectional operation. The emitter regions are proposed as tiny mesas of 0.3 μm width and 1.0 μm height covering about 6% of both the surfaces. Thus, the structure appears rather simple, but its production requires fine line resolution and processing on both the surfaces of the wafer.

The Effect of Impurities in Tin Film When Used As Mos Gate Electrodes

ABSTRACTRefractory metal gates have been studied for CMOS gate electrodes on ultra thin gate oxide due to its midgap work function, low resistivity and no gate depletion, etc. In particular, titanium nitride received most attention because of its process maturity and its good diffusion barrier properties for backend applications. Different TiN film properties are important when TiN is used as a gate material than when it is used for backend applications. One issue is the effect of TiN film impurities on the gate oxides and their high temperature stability since some high temperature processes are usually needed after gate formation. This paper reports the study of different TiN films used as MOS gate electrodes on ultra thin gate oxide and the effects of their impurities on gate oxide electrical performance. PVD TiN films deposited with different process conditions show different oxygen content, and different gate oxide properties were observed when these PVD TiN films were used as gate electrodes. On the other hand CVD TiN films deposited using different precursors also showed different impurities, including carbon, oxygen or silicon, which largely affect CVD TiN performance when used as gate material. The different TiN films were characterized by X-ray glancing angle reflection, XPS, SIMS and TEM, and the electrical properties were studied by I-V, C-V, charge to breakdown (Qbd) and ramp voltage breakdown tests on MOS capacitors. The results showed that the high purity TiN films provide stable gate material with small damage to the gate oxide, but impurities, especially oxygen, affect the gate oxide properties after high temperature anneal. However, due to the different TiN process capabilities, TiN films with impurities may still have advantages over pure TiN film in some cases of different MOS gate applications.

IGBT negative gate capacitance and related instability effects

For high collector voltages, Insulated Gate Bipolar Transistors (IGBTs) exhibit a negative gate capacitance. In this condition, a p-channel inversion layer is formed on the N-base surface. The positive charges in the p-channel induce negative charges in the MOS gate electrode. This results in a negative gate capacitance. As a consequence of this negative capacitance, IGBT operation is inherently unstable, leading to current redistribution between cells or even chips.

Single-Wafer RTCVD of Polysilicon: a Complementary Step in Front-End Integrated Processing

AbstractPolycrystalline silicon is used in the fabrication of integrated circuits in various applications. These include a MOS gate material, bipolar emitter and base contacts, trench refill, complementary material for elevated source / drain structures, solid diffusion source for formation of shallow junctions and the active material in thin film transistors. The deposition of polysilicon as the MOS gate electrode or the bipolar emitter contact follows the most critical processing steps in fabrication of these devices. Maximum reproducibility and highest device performance are achieved when the interfaces between the polysilicon and the underneath substrate are well controlled. This level of control can be obtained by combining the compatible processing steps under a controlled environment. Single-wafer RTCVD of polysilicon was introduced to complement the emerging front-end integrated processing technology for MOS, bipolar and BICMOS devices.

Turn-On Principles of the MOS-GTO

MOS-GTO's (GTO thyristors which are turned off by the action of a MOS-gate) represent a new generation of controllable thyristors offering considerable advantages in turn-off behavior as compared to conventional GTO's. However, MOS-GTO's generally require one control electrode for turn-on and another control electrode for turn-off, which might be regarded as a disadvantage. It is shown that in MOS-GTO's with a p-channel cathode structure it is possible to turn the thyristor on and off by controlling just one MOS gate electrode. As a triggering current for turn-on, the MOS capacitor charging current is used.

MOS-Controlled thyristors—A new class of power devices

A new class of power devices is described that is based on an optimal combination of MOS and thyristor elements. Devices of this class function in the ON-state and OFF-state in a manner indistinguishable from a thyristor yet can switch from on-to-off or off-to-on by applying a voltage to its MOS gate. Thus, the devices exhibit extremely low forward drop, high surge current capability, and enjoy negative thermal feedback. To turn off the device, one activates the gate so that FET's are turned on to effectively short one of the emitting junctions of the thyristor. These FET's need only block a maximum of about 1 V when off and carry a sizable current for about 1 µs when on. To turn on the device, any of the normal methods may be employed. However, it is most convenient to use the same MOS gate electrode (and polysilicon layer) and a voltage of the opposite polarity to turn on the thyristor with another FET-just as if it were a normal MOS gated thyristor. The current density that can be turned off depends on the density and effective resistance of the turn-off FET's while turn-on speed and di/ dt rating depend on the initial turn-on area, which in turn depends on the density of the ON-FET's. If the OFF-gate voltage is maintained during the desired OFF-state period, the device has, effectively, an infinite dv/dt capability. Switching speed is most similar to, but somewhat faster than, that of gate turn-off thyristors (GTO's) and, as in other bipolar devices, depends chiefly on carrier recombination time, device thickness, and turn-off di/dt .

6173. Surface preciption of boron nitrate on the surface of type 304]' stainless steels doped with nitrogen, boron, and cerium

SiGe alloys are currently used for HBT and MOS as epitaxial layers for base or strained channel, respectively. In the poly phase, SiGe has been studied as a replacement for poly-Si in MOS gates due to its lower thermal budget and gate depletion and also due to the Workfunction Engineering for Vt adjustments. However, for application to CMOS technology as poly-SiGe gates, others constrains emerge such as quality of the oxide interface and etch chemistry. For both applications, the Ge fraction normally lies between 20% and 40%. In this study, authors use a low Ge contents (1%) poly-SiGe thin films aiming for MOS gate electrode. The Ge fraction was determined by RBS analysis. 230 nm thick samples were deposited onto 10 nm thermally oxidized 〈1 0 0〉, p-type Si substrates using silane and germane. Films were deposited in the temperature of 500 °C and total pressure of 667 Pa (5 Torr) by vertical LPCVD. The samples were doped using 31P+ ion implantation from 5 × 1014 cm−2 up to 2 × 1016 cm−2 and annealed by RTP (40 s) from 500 °C up to 900 °C. Rs values were obtained by 4-point probe technique and CV curves were extracted from nMOS capacitors with 200 μm diameter. The same processing steps were used to fabricate similar poly-Si samples and capacitors for comparison.The poly-SiGe samples presented Rs values one order of magnitude lower than poly-Si and CV analysis of nMOS capacitors showed very good characteristics. The 1% Ge in the alloy ensures a low thermal budget for the overall process. Although a relatively high annealing temperature (800 °C) must be used to reduce oxide charge and interface traps, the temperature is well below the necessary for poly-Si processing and can allow formation of the shallow junctions needed for next technological nodes.

Oxygen‐Doped Molybdenum Films for MOS Gate Application

Intentionally oxygen‐doped Mo films for MOS gate electrodes are investigated to eliminate the penetration of implanted As ions into the silicon substrate through the gate electrodes and gate oxides. The films are prepared by reactive sputtering of Mo in a mixture of Ar and gases. Depth profiles of As ions and MOS C‐V curves are measured to estimate stopping properties. For as‐deposited films, whose oxygen concentrations are higher than 20 atom percent (a/o), As ion penetration depth is within 0.15 μm under 100 keV As ion implantation. This depth is about one third of that in normal Mo films. This excellent stopping property can be attributed to the nearly amorphous structure, which suppresses As ion channeling in the films resulting from oxygen doping. The resistivity of films with 39 a/o oxygen after annealing at 1000°C for 30 min is 25 μΩ‐cm, which is only three times as large as that for normal Mo films. In gate MOS structures, MOS characteristics are independent of oxygen concentrations in the films, and are almost the same as the characteristics for normal Mo gate electrodes.

Design Considerations for Single-Chip Computers of the Future

In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emerging VLSI circuits are analyzed. Desirable architectural features in modern computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one milion transistors to the various functional blocks is given, and the result is a memory intensive design.

Design Considerations for Single-Chip Computers of the Future

In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emeging VLSI circuits are analyzed. Desirable architectural features in modem computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one million transistors to the various functional blocks is given, and the result is a memory intensive design.