MOS Capacitors Research Articles

Charge trapping and recovery in ALD HfO2/β-Ga2O3 (010) MOS capacitors

The reliability of atomic layer deposited HfO2 β-Ga2O3 (010) MOS capacitors (MOSCAPs) was tested using constant voltage stress measurements. The HfO2/β-Ga2O3 MOSCAPs showed significant positive flatband voltage shifts (ΔV fb) of up to +1.3 V after 4.3 × 103 s stress, likely due to electron trapping in the dielectric in border traps. Results indicate there may exist an electric field threshold between 0.98 and 1.23 MV cm−1 for electron trapping to occur in these MOSCAPs. Deep ultra-violet (DUV) illumination enables full recovery from the charge trapping. In contrast, HfO2/Si MOSCAPs do not recover under DUV illumination and exhibit smaller voltage shifts upon initial testing. We thus surmise that the type-II band alignment between HfO2 and β-Ga2O3 enables full recovery from stress-induced charge trapping via photogeneration of electron–hole pairs and hole transport across the negative valence band offset. This hypothesis is borne out by the observation of photo-current in the HfO2/β-Ga2O3 MOSCAPs when biased in depletion. In sum, HfO2/β-Ga2O3 MOS structures appear to be susceptible to flatband voltage shifts during stress bias due to the availability and accessibility of border traps. This work highlights the unique challenges in forming reliable ultra-wide band gap MOS devices, due to the significant role that border traps in the lower half of the insulator band gap play in bias stress response.

Effect of oxide and interface traps on electrical characteristics of post-deposition annealed HfSiO4/n-Si structures

This study presents detailed results on the modifications in chemical composition, defective bonds, crystal properties based on x-ray photoelectron spectroscopy (XPS) depth profiles and x-ray diffraction of post-deposition annealed HfSiO4/Si structure. It also leads to a link to defect centers and their effect on the electrical characteristics of MOS capacitors. The HfSiO4 films were deposited on n-Si wafers by RF magnetron sputtering and annealed at room temperature (RT), 300 °C, 700 °C, 900 °C, 1100 °C under N2 ambient. That the atomic concentration values of each element in the oxide did not change significantly depending on the annealing temperature showed that the film was deposited with high homogeneity. It was determined that the shift direction of the binding energies of Hf 4f and O 1s XPS spectra were related to the bonding preference of oxygen rather than its concentration. The increase in Hf–M and Hf–Si oxygen defective bonds decreased the binding energy of the XPS spectra. It was determined from the XPS analyses of amorphous films that Hf–Si and Si–Si oxygen defective bonds may cause the positive charge trapping, resulting in the highest negative charge trapping/positive effective oxide charge density () in the 300 °C-MOS capacitor. It was determined that Hf–Hf oxygen defective bonds may be the precursors of negative charge trapping. Interface states only contributed to the dielectric constant (k) in the RT-MOS capacitor. The (barrier height) values showed that the efficiency of acceptor-like and donor-like interface states changes depending on the frequency.

Comparison of high-k Y2O3/TiO2 bilayer and Y-doped TiO2 thin films on Ge substrate

Y2O3/TiO2 bilayer thin films and Y-doped TiO2 (YTO) thin films were deposited on a Ge substrate by atomic layer deposition at a substrate temperature of 250 °C. They were used as gate insulators to examine the electrical properties of Pt/TiN/TiO2/Y2O3/p-Ge and Pt/TiN/YTO/p-Ge metal–oxide–semiconductor capacitors. A 7 nm thick bilayer thin film showed a lower leakage current density by more than one order of magnitude compared to a YTO thin film with the same thickness due to the high conduction band offset between the Y2O3 layer and Ge substrate. However, the bilayer thin film showed a large hysteresis of 950 mV. On the other hand, the YTO thin film showed significantly reduced hysteresis of 120 mV due to the smaller slow trap density. The voltage acceleration factors of the bilayer thin film and YTO thin film were 1.12 and 1.25, respectively, higher in the YTO thin film. The interfacial trap density of the 7 nm thick bilayer and YTO thin films were 3.5 × 1011 cm−2 eV−1 and 2.7 × 1011cm−2 eV−1, respectively. The equivalent oxide thickness of the YTO film could be scaled down to 0.9 nm, and a leakage current density of 1.4 × 10−4A cm−2 at flat band voltage −1 V was achieved. This study confirmed that the YTO film can be used as a promising ternary high-k oxide for a Ge-based field-effect-transistor.

Si racetrack optical modulator based on the III-V/Si hybrid MOS capacitor.

We have fabricated a Si racetrack optical modulator based on a III-V/Si hybrid metal-oxide-semiconductor (MOS) capacitor. The III-V/Si hybrid MOS optical phase shifter was integrated to a Si racetrack resonator with a coupling length of 200 µm and a coupling gap of 700 nm. The fabricated Si racetrack resonator demonstrated a small VπL of 0.059 Vcm. For 10-dB optical intensity modulation, the Si racetrack resonator showed a 60% smaller driving voltage than a Mach-Zehnder interferometer modulator with the same phase shifter, leading to a better balance between high energy efficiency and large modulation bandwidth.

HfO2 as gate insulator on N-polar GaN–AlGaN heterostructures

To further increase the operation frequency of GaN high electron mobility transistors (HEMTs) with high power gain in the mm-wave band (30–300 GHz), channel thickness must be scaled. High-k dielectrics such as HfO2 can be inserted as gate insulator to reduce the leakage, while maintaining good gate control. In this work, we investigated HfO2 on N-polar HEMT structure by performing frequency dependent capacitance–voltage measurements on metal-oxide-semiconductor capacitors (MOSCAPs). The impact of annealing on the quality of HfO2 was studied. Moreover, we compared the CV characteristics of MOSCAPs with HfO2 deposited on the GaN channel with that deposited on the AlGaN cap layer. We showed that HfO2 deposition on AlGaN cap leads to Fermi level pinning, which prevents the channel being pinched off by applying gate voltage. On the other hand, well-behaved CV profiles were achieved by depositing HfO2 directly on GaN or SiN dielectric.

Mg:TiO2 alloy thin films based MOS capacitors grown on GaAs substrates

Electron beam evaporation technique is employed to synthesise TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 thin films (TFs) grown on (100) n-type GaAs substrates. Field emission gun-scanning electron microscope (FEG-SEM) results show that the TFs have a thickness of ~225 nm. The non- contact atomic force microscopy (NC-AFM) images shows the pore volume of the TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 TFs enhanced gradually. UV-Vis absorption measurements are performed on the samples to determine the main bandgap and defect level transition of the material. A unique modified Urbach theoretical model has been introduced to simulate the experimental absorption spectrum. The main bandgap energy of the TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 samples are calculated to be ~3.45 eV, 3.85 eV and 4.30 eV respectively. A gradual enhancement in main bandgap transition probability and decrease in defect level transition of the material has been observed with enhanced incorporation of Mg into the TiO2 host material. X-ray diffraction (XRD) is performed, which shows a continuous change in lattice constant of TiO2 with Mg. Current (I)-voltage (V) characteristics of the TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 Schottky devices revealed that the leakage current at −1 V was 1.28 × 10−6 A, 1.46 × 10−9 A and 2.44 × 10−10 A respectively. Capacitance (C)–voltage (V) measurements are performed on the devices at different frequencies. A theoretical simulation has been adopted by amending the delta depletion model at 1 MHz. The dielectric constant and the flat band voltage of the TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 devices are found to be 100, 120 and 160 and 16.1 V, 14.7 V and 9.7 V respectively. Hill-Coleman’s method shows a gradual enhancement of the density of interface states (Dit) with Mg concentration. The calculated Dit value of the TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 TF devices are ~6.16 × 1010 eV−1 cm−2, 6.44 × 1010 eV−1 cm−2 and 1.11 × 1011 eV−1 cm−2 respectively. The observed C-V hysteresis confirms an enhancement in the charge retention into the film with increasing Mg concentration, which in turn improves the memory window (MW) from ~0.36 V (at±7 V) to ~0.67 V (at±7 V) and ~0.87 V (at±10 V) to ~1.0 V (at±10 V) with sweeping voltage.

Interface Optimization and Modulation of Leakage Current Conduction Mechanism of Yb2O3/GaSb MOS Capacitors with ALD-Driven Laminated Interlayers

In this report, the impact of atomic-layer-deposition-derived different laminated gate stacks on the interface chemistry and electrical performance of Yb2O3/GaSb metal-oxide-semiconductor (MOS) cap...

Reliability enhancement in dipole-doped metal oxide semiconductor capacitor induced by low-temperature and high-pressure nitridation

In this work, low-temperature (100 °C–200 °C) and high-pressure (LTHP) nitridation treatment was applied to improve the performance and reliability of dipole-doped metal oxide semiconductor capacitor. After the LTHP nitridation, the gate leakage and the capacitance of the dipole sample demonstrated obvious enhancements. Furthermore, the degradation of positive bias stress (PBS) and time dependent dielectric breakdown on these LTHP-treated devices apparently decrease. The LTHP was confirmed to effectively enhance the performance and the endurance of the dipole sample. Finally, the mechanism of LTHP nitridation treatment was established to explain the improvements in dipole samples.

TCAD Modeling of Surface Radiation Damage Effects: A State-Of-The-Art Review

A comprehensive numerical model which accounts for surface damage effects induced by radiation on silicon particle detectors is presented with reference to the state-of-the-art Synopsys Sentaurus Technology CAD (TCAD) tool. The overall aim of this work is to present the “Perugia 2019 Surface” damage modeling scheme, fully implemented within the TCAD environment, which effectively describes the surface damage effects induced by radiation in silicon sensors relying on a limited number of parameters relevant for physics. To this end, extensive measurement campaigns have been recently performed on gated-diodes and MOS capacitors at Fondazione Bruno Kessler (FBK) in Italy, Hamamatsu Photonics (HPK) in Japan and Infineon Technologies (IFX) in Austria on both n-type and p-type substrates (with and without p-spray isolation implants), in order to extrapolate the relevant parameters which rule the surface damage effects. The integrated interface trap density and the oxide charge density, have been determined before and after X-ray irradiation with doses ranging from 0.05 to 100 Mrad(SiO2), for each specific foundry and technology flavor. The main guidelines of this study are the versatility and generality of the simulation approach.

A method for characterizing near-interface traps in SiC metal–oxide–semiconductor capacitors from conductance–temperature spectroscopy measurements

The state-of-the-art technology for gate oxides on SiC involves the introduction of nitrogen to reduce the density of interface defects. However, SiC metal–oxide–semiconductor (MOS) field-effect transistors still suffer from low channel mobility even after the nitridation treatment. Recent reports have indicated that this is due to near-interface traps (NITs) that communicate with electrons in the SiC conduction band via tunneling. In light of this evidence, it is clear that conventional interface trap analysis is not appropriate for these defects. To address this shortcoming, we introduce a new characterization method based on conductance–temperature spectroscopy. We present simple equations to facilitate the comparison of different fabrication methods based on the density and location of NITs and give some information about their origin. These techniques can also be applied to NITs in other MOS structures.

Polycrystalline/Amorphous HfO2 Bilayer Structure as a Gate Dielectric for β-Ga2O3 MOS Capacitors

We report the comparison of the atomic layer deposited polycrystalline (p-)/amorphous (a-) HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bilayer gate dielectric with p-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /a-Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> for enhanced β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> metal oxide semiconductor capacitors (MOSCAPs). A discrepancy in the temperature-dependent hysteretic behaviors is observed, and thus, pulse capacitance- voltage (C-V) measurements are employed to investigate interface properties at the border between the amorphous (Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> or HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) and polycrystalline (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) oxide layers. The proposed p-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /a-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> exhibits similar interface trap densities (Dit) at the interface between the bilayer dielectric and β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , and shows lower border trap density (Nbt). An effective barrier height of 1.62 eV for the p-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /a-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> with a breakdown field of 9.1 MV/cm, which is higher than 1.01 eV of p-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /a-Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , is obtained from the current density-voltage (J-V) characteristics using the Folwer-Nordheim model. Moreover, as compared with a p-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> single layer, the additional a-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer on top of p-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is beneficial to improve hysteretic and leakage characteristics, while maintaining its high-quality interface. The p-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /a-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bilayer with improved interface properties as well as a large positive flat-band voltage of 4.7 V is a promising candidate for the metal/high-k-stack of β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> MOSCAPs.

Mobility improvement of 4H-SiC (0001) MOSFETs by a three-step process of H2 etching, SiO2 deposition, and interface nitridation

4H-SiC(0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) and MOS capacitors were fabricated by the following procedures: H2 etching, SiO2 deposition, and nitridation, and their electrical characteristics were evaluated. Substantially low interface state densities (4–6 × 1010 cm−2 eV−1) and high channel mobilities (80–85 cm2 V−1 s−1) were achieved by N2 annealing or NO annealing after H2 etching and SiO2 deposition. The threshold voltage of the MOSFETs fabricated with N2 annealing was shifted negatively when the oxide was formed by deposition. On the other hand, normally-off operation and high channel mobility were compatible for the MOSFETs fabricated with NO annealing.

MOS capacitor based Dickson charge pump and ripple cancellation techniques using an LC circuit

This paper proposes a new architecture using integrated inductor and MOS capacitor based on Dickson charge pump associated with two parallel LC circuit after the first stage and output stage which cancel the ripple voltage that is generated in the output stage. In this circuit, the MOS capacitor as used instead of pumping capacitor, which helps in reducing the circuit Silicon area. Efficiency up to 80–90% can be achieved by reducing the parasitic effects and by using a MOS capacitor. The efficiency conversion and voltage gain increase or decreases depending on inductor and capacitor values. Vt drop loss is managed using high voltage clock. It shows that 3.5 V output voltage is generated from input voltage of 1.0 V with five stages of MOS capacitor (used as Pumping capacitor) in working frequency of 100 MHz the simulations were performed in Cadence Virtuoso platform with 0.18 μm CMOS process.

Effect of annealing temperature on the electrical characteristics of Al/Er2O3/n-Si/Al MOS capacitors

In this work, Er2O3 films deposited by electron beam (E-beam) evaporation technique were annealed at 450 °C, 550 °C, and 650 °C in N2 atmosphere for 30 min. We then compared the electrical properties, the frequency dependency of the density of interface states, and series resistance of as-deposited and annealed Al/Er2O3/n-Si/Al MOS capacitors. The grain size measurements carried out by X-ray diffractometer (XRD) and the root mean square (RMS) surface roughness values obtained by atomic force microscopy (AFM) increased with an increase of annealing temperature. The C-V and G/ω-V measurements were carried out at a frequency of 1 MHz for as-deposited and annealed MOS capacitors. The capacitance in the accumulation region decreased with an increase in annealing temperature, and the capacitor film annealed at 450 °C had the highest capacitance in the accumulation region as well as high-k value, and low barrier height. In addition, the C-V and G/ω-V measurements carried out in the frequency range of 20 kHz to 1 MHz were analyzed to understand the effect of frequency on the series resistance Rs and interface states Dit. The measured and calculated results reveal a significant influence of frequency on both Rs and Dit of the fabricated MOS capacitor characteristics.

A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction

A fully integrated high efficiency switched-capacitor (SC) DC-DC converter with pulse frequency modulation (PFM) control is presented. The small signal model of the multiphase-interleaving SC converter is given and it is verified through the simulation and the measurement results. For high efficiency, this design set the dominant pole at the output of the error amplifier (EA) and the 14-phase interleaving topology can push the non-dominant pole away from the Unit Gain Frequency (UGF) for the loop stability. By combining the flying-well and the deep n-well (DNW) isolation techniques, the proposed high-density MOS capacitor can reduce both the parasitic loss and the charge sharing loss of the converter. The conversion ratio of the converter is 2:1 under 3.3V power supply. This SC DC-DC converter is fabricated in the 40 nm CMOS process. It obtains the peak efficiency of 86.2% and the output power-density of 226 mW/mm2. It maintains the efficiency above 80% from 8 mA to 50 mA load condition.

Fast Near-Interface Traps in 4H-SiC MOS Capacitors Measured by an Integrated-Charge Method

Oxide traps existing in 4H-SiC MOS capacitors with fast response times that are active in the strong accumulation and depletion regions were characterized by an integrated-charge method. The method is based on the measurement of charging and discharging voltages across MOS capacitors in response to high-frequency voltage pulses. This method can identify traps with response times in the order of hundreds of nanoseconds. The results reveal an increasing density of near-interface traps with energy levels above the bottom of the conduction band, which are the active defects reducing the channel-carrier mobility in 4H-SiC MOSFETs.

An 0.4–2.8 GHz CMOS Power Amplifier With On-Chip Broadband-Pre-Distorter (BPD) Achieving 36.1–38.6% PAE and 21 dBm Maximum Linear Output Power

A broadband 180 nm CMOS power amplifier (PA) operating from a frequency bandwidth of 400 MHz to 2.8 GHz is presented in this paper. The PA is integrated with an inductor-less Broadband-Pre-Distorter (BPD) to enhance its linearity for wide bandwidth. The BPD consists only of MOS transistors, resistors, and capacitors which contribute to the wideband operation thus independent of the Q factor of passive inductors which contributes to the effectiveness of many other APDs available. The integrated BPD improves the Amplitude Modulation-to-Amplitude Modulation (AM-AM) and Amplitude Modulation-to-Phase Modulation (AM-PM) deviation of the PA across maximum linear output power of 21 dBm. Utilizing a silicon area of 1.69 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , mounted on Roger's RO4000/FR4 PCB, the BPD-PA produces a maximum output power of more than 22 dBm for 2.4 GHz bandwidth with a minimum power gain of 15 dB. The corresponding peak power added efficiency (PAE) of more than 35% is achieved across the operating bandwidth. The fabricated BPD-PA meets the Adjacent Channel Leakage Ratio (ACLR) specification of -30 dBc at a maximum linear output power of 21 dBm (3 dB back-off from maximum output power) when tested with 20 MHz LTE signal at 1.7 GHz.

Novel Multiple-Layer Stack Capacitor and Its Application in the IRPFA Readout Circuit

In this paper, a kind of four-layer stack capacitor is proposed, which has realized the compatibility with the conventional standard 0.5μm CMOS technology. The effective capacitance per area of the proposed stack capacitor is about three times larger than that of the mono-layer MOS capacitor. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the presented four-layer stack capacitor has been also established with considering the fringe effect. The results show that the root mean square error of the proposed SPICE model is less than 2%. The model has been applied in the simulation design of the infrared focal plane array readout circuit (IRFPA ROIC) successfully. Based on the improved 0.5μm CMOS process with four-layer stack capacitor, an IRFPA ROIC with 640×512 array has been implemented and the dynamic range is improved from 73db to 78dB.

Sub-Pico-Second Hole Generation Lifetime in Thin Film IGZO Sputtered and Annealed on P-Silicon Substrate

Indium-gallium-zinc-oxide (IGZO) sputtered and annealed in the absence of oxygen shows large oxygen vacancy concentration leading to n-type doping of the thin film. However, because of low intrinsic carrier concentration minority carrier (hole) concentration remains weak. Thus, measurement of thermal hole generation lifetime in unipolar IGZO is challenging. In this work, utilizing the charge transient of an appropriately biased depleted HfO2/IGZO thin film MOS capacitor fabricated on a p-silicon substrate, we extracted hole thermal generation lifetime of IGZO. The measured lifetime was found between 0.62–0.064 ps whence IGZO film received 400 °C to 700 °C anneal treatments followed by its direct sputtering on p-silicon substrate. Further, a morphology analysis of the IGZO was presented. Difference in the lifetime which occurred due to amorphous to the nano-crystalline transition of the IGZO thin film with increased anneal temperature was furthermore validated through XRD, SEM and AFM measurements. Hole capture cross-sections as we obtained from surface generation velocities at the IGZO/HfO2 interface and energy distributions of interface state density were found in agreement, which indirectly demonstrates the accuracy of the measured hole generation lifetime employing the transient capacitance extrapolation, since under the steady state condition hole generation through the interface states of IGZO/HfO2 tends to balance its bulk (IGZO) counterpart

Interface Optimization and Modulation of Leakage Current Conduction Mechanism of Yb2O3/GaSb MOS Capacitors With (NH4)2S Solutions Passivation

In current work, the impact of ammonium sulfide (NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> ) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> S solution passivation with varied pH value on the Yb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /n-GaSb interface has been investigated comparatively. Compared with control samples, the neutral (NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> ) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> S solution passivation can effectively reduce oxides layer on GaSb surface and gate leakage via X-ray photoelectron spectroscopy(XPS) measurements and electrical characterization. High-low frequency capacitance method was used to evaluate interface-state density Dit, it was found that capping with Yb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> can delaythe interface-state generation and the lowest Dit value of 5.18 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> for Yb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /GaSb capacitor with neutral (NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> ) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> S was achieved. Moreover, the possible leakage current conduction mechanisms for capacitors measured at room temperature and low temperature have also been discussed systematically.