AbstractTo suppress the phase jitter in digital PLL as is done in analog PLL, it is necessary to narrow the bandwidth of the loop. On the other hand, the narrow‐band loop has an adverse effect on the range of synchronization and the initial pull‐in. Several proposals have been made to solve this problem [3, 6].This paper proposes a new DPLL to solve the problem using a binary quantized phase and frequency comparator (PFC) composed of a general‐purpose shift register, monostable multivibrators and OR gates. Assuming the same jitter suppression performance, the proposed DPLL can broaden the range of synchronization by several times, compared with the traditional DPLL. The performance of the proposed loop structure is calculated theoretically, and the agreement with the result of experiment is verified.