Monolithic Receiver Research Articles

Fully integrated optical receiver using single-photon avalanche diodes in high-voltage CMOS

A monolithic optical receiver containing four single-photon avalanche diodes (SPADs) fabricated in 0.35-μm high-voltage (HV) CMOS is introduced and compared with two 4-SPAD receivers realized in pin-photodiode CMOS belonging to the same process family. This HV-CMOS SPAD receiver achieves sensitivities of −55.1 dBm at 50 Mbit / s and −52.0 dBm at 100 Mbit / s, both with digital processing, a bit error rate (BER) of 2 × 10 − 3, and return-to-zero coding using a wavelength of 642 nm. Also at 143 Mbit / s, this BER is achievable. This receiver is especially interesting for applications in which low light intensities can be expected, such as quantum key distribution, optical communications from deep space, and visible light communication for short-range consumer applications.

Low-power fully monolithic MICS band receiver for 402-405 MHz implantable devices

ABSTRACTA 402–405MHz fully monolithic Radio Frequency (RF) low-Intermediate Frequency (IF) receiver is presented. The proposed low-power RF receiver consists of a differential Common gate-Common Source Low-Noise Amplifier (CG-CS LNA) with a positive–negative feedback technique, passive mixer, fully integrated Voltage Controlled Oscillator (VCO), and an IF Variable Gain Amplifier (VGA). To achieve a wide tuning range while keeping a low gain (Kvco), the VCO has 16 bands selectable by a 4-bit digital control. The complete receiver prototype is implemented in a 0.13μm CMOS process and occupies 0.625 mm2 active chip area. The receiver consumes only 3.76 mW of power from a 1.2 V power supply and has a gain of 45 dB and a noise figure of 13.6 dB (integrated from 20 Hz to 0.5 GHz). The design achieves an in-band IIP3 of 2 dBm, IIP2 better than 44 dBm. It presents a 3-dB IF bandwidth of 3 MHz with −80 dBm sensitivity.

A 25-Gb/s Monolithic Optical Receiver With Improved Sensitivity and Energy Efficiency

A 25-Gb/s Monolithic Optical Receiver With Improved Sensitivity and Energy Efficiency

Exact error rate analysis of free-space optical communications with spatial diversity over Gamma–Gamma atmospheric turbulence

The error rate performances and outage probabilities of free-space optical (FSO) communications with spatial diversity are studied for Gamma–Gamma turbulent environments. Equal gain combining (EGC) and selection combining (SC) diversity are considered as practical schemes to mitigate turbulence. The exact bit-error rate (BER) expression and outage probability are derived for direct detection EGC multiple aperture receiver system. BER performances and outage probabilities are analyzed and compared for different number of sub-apertures each having aperture area A with EGC and SC techniques. BER performances and outage probabilities of a single monolithic aperture and multiple aperture receiver system with the same total aperture area are compared under thermal-noise-limited and background-noise-limited conditions. It is shown that multiple aperture receiver system can greatly improve the system communication performances. And these analytical tools are useful in providing highly accurate error rate estimation for FSO communication systems.

Research and Design on On-Line Contact of High Voltage Switch Circuit Breaker Temperature Rise Monitoring Device

In order to make on-line monitoring on the temperature of high voltage switch circuit breakerand find outthermal fault in time. This paper puts forward a new method with radio frequency and magnetic saturation power supply technology to make on-line monitoring on the temperature of high voltage switch circuit breaker, it designs the high voltage switch circuit breaker contact temperature online monitoring device. The device mainly includes monolithic temperature collector and data receiver, they transmit data wirelessly, and this makes high temperature monitoring terminal and the data receiving terminal completely electrical isolated. Integrated temperature collector doesn’t need external power supply, it uses small CT saturation technology for continuous power. The experiment shows that the temperature error is ±2°C, it can meet online temperature monitoring requirements of high voltage switch circuit breaker contact.

Monolithic InP Receiver Chip With a Variable Optical Attenuator for Colorless WDM Detection

We demonstrate a monolithically integrated quadrature coherent receiver photonic integrated circuit (PIC) on an InP substrate. The PIC comprises a 90° optical hybrid, a variable optical attenuator (VOA), and four RF photodetectors. With a dynamic range of 25 dB, the VOA enables the usage of the receiver PIC for colorless WDM detection.

A 150-Mb/s CMOS Monolithic Optical Receiver for Plastic Optical Fiber Link

This paper describes a 150-Mb/s monolithic optical receiver for plastic optical fiber link using a standard CMOS technology. The receiver integrates a photodiode using an N-well/P-substrate junction, a pre amplifier, a post amplifier, and an output driver. The size, PN-junction type, and the number of metal fingers of the photodiode are optimized to meet the link requirements. The N-well/P-substrate photodiode has a 200-μm by 200-μm optical window, 0.1-A/W responsivity, 7.6-pF junction capacitance and 113-MHz bandwidth. The monolithic receiver can successfully convert 150-Mb/s optical signal into digital data through up to 30-m plastic optical fiber link with -10.4 dBm of optical sensitivity. The receiver occupies 0.56-mm2 area including electrostatic discharge protection diodes and bonding pads. To reduce unnecessary power consumption when the light is not over threshold or not modulating, a simple light detector and a signal detector are introduced. In active mode, the receiver core consumes 5.8-mA DC currents at 150-Mb/s data rate from a single 3.3 V supply, while consumes only 120 μW in the sleep mode.

Low‐power 24 GHz CMOS receiver front‐end using isolation enhancement technique for automatic radar systems

AbstractThis article describes a monolithic receiver front‐end comprising a low‐noise amplifier, a dual‐gate mixer, and an intermediate‐frequency (IF) amplifier implemented in a standard 0.18 μm CMOS technology. Over the frequency band of interest, flat and high conversion‐gain (CG) and flat and low noise‐figure (NF) are achieved simultaneously by adopting slightly under‐damped Q‐factors for the second‐order CG and NF frequency responses. To suppress the high‐frequency noise and to enhance the RF–IF and LO–IF isolation, RC low‐pass filters (i.e., IF filters) are added at output of the dual‐gate mixer and the cascode IF amplifier. The receiver front‐end dissipates 16.4 mW and exhibits an NF of 6.86 dB and a CG of 22.26 dB at 24 GHz. In addition, excellent isolation is also achieved. The measured LO–IF, RF–IF, and LO–RF isolation is −31.31, −49.36, and −58.93 dB, respectively, at 24 GHz. The chip area is only 1.21 × 0.7 mm2, that is, 0.847 mm2, excluding the test pads. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1471–1476, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26835

Low power and high conversion gain 21‐GHz receiver front end in a standard 0.18 μm CMOS technology

AbstractThis article describes a monolithic receiver front end comprising a low‐noise amplifier (LNA), a mixer, an intermediate‐frequency (IF) amplifier, and an IF filter implemented in a standard 0.18 μm CMOS technology.Current‐reused technique is used in the LNA to reduce power dissipation. Current bleeding technique is used in the mixer to improve conversion gain and power linearity. To enhance RF–IF and LO–IF isolation, an RC low‐pass filter (i.e., IF filter) is added in the drain terminal of the input transistor of the cascode IF amplifier. At an RF of 21 GHz and IF of 2.4 GHz, the receiver front end dissipated 43.2 mW and exhibited a noise figure (NF) of 8.6 dB, and a conversion gain of 20.3 dB. In addition, excellent isolation was also achieved. The measured LO–IF and LO‐RF isolation is −30.9 dB and −51.1 dB, respectively, at LOin of −1 dBm. The measured RF–IF isolation is −57.3 dB at RFin of −30 dBm. The chip area is only 0.97 × 0.9 mm2, that is, 0.873 mm2, excluding the test pads. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2875–2879, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26423

A 5-GHz-Band CMOS Receiver With Low LO Self-Mixing Front End

A 5.0-GHz-band monolithic direct-conversion receiver front end employing subharmonic mixers (SHMs) is demonstrated in 0.18-mum CMOS technology. Instead of using transistors as transconductors, the SHMs adopt on-chip 1:4 transformers to achieve voltage gain, and hence, excellent local-oscillator self-mixing suppression and good linearity can be obtained. Additionally, a CMOS-compatible postprocess is used to selectively remove the silicon substrate underneath the inductors and transformers of the receiver front end. While dissipating 43.9 mW from a 1.8-V supply, the micromachined receiver front end exhibits a voltage gain of 28.0 dB, a noise figure of 9.7 dB, a third-order input intercept point of -7.8 dBm at 5.0 GHz, and an input-referred dc offset of -118.0 dBm. The proposed receiver front end is further integrated with analog baseband circuits, a fractional-N frequency synthesizer, and a serial-to-parallel data converter to accomplish a multioperation-mode receiver.

Time-Frequency Channel Parameterization with Application to Multi-Mode Receivers

There is a trend towards flexible radios which are able to cope with a range of wireless communication standards. For the integrated processing of widely different signals—including single-carrier, multicarrier, and spread-spectrum signals—monolithic baseband receivers need universal formats for the signal representation and channel description. We consider a reconfigurable receiver architecture building on concepts from time-frequency (TF) signal analysis. The core elements are TF signal representations in form of a Gabor expansion along with a compatible parameterization of time-variant channels. While applicable to arbitrary signal types, the TF channel parameterization offers similar advantages as the frequency domain channel description employed by orthogonal frequency-division multiplexing receivers. The freedom in the choice of the underlying analysis window function and the scalability in time and frequency facilitate the handling of diverse signal types as well as the adaptation to radio channels with different delay and Doppler spreads. Optimized window shapes limit the inherent model error, as demonstrated using the example of direct-sequence spread-spectrum signaling.

A simple monolithically integrated optical receiver consisting of an optical preamplifier and a p-i-n photodiode

We demonstrate a monolithic optical receiver consisting of the integration of a semiconductor optical amplifier and a p-i-n photodetector based on asymmetric twin-waveguide technology. Multiple quantum wells with 1% compressive strain are used for both optical amplification and detection. The device has a peak external responsivity of 8.2/spl plusmn/0.4 A/W (/spl sim/9-dB fiber-to-detector gain), and a 3-dB optical bandwidth of 11/spl plusmn/1GHz, equivalent to a 265-GHz gain-bandwidth product. The efficient coupling of light between individual optical components is achieved by a lateral adiabatic taper that reduces the fabrication complexity. This work represents a considerable simplification over previously demonstrated high-performance integrated optical receivers.

The application of complex quantized feedback in integrated wireless receivers

Integrated wireless receiver architectures, such as direct-conversion receivers, offer many advantages over the conventional heterodyne receivers including smaller size, lower cost, and reduced power consumption. However, the design of monolithic receivers, using direct-conversion, involves many challenges including dealing with low-frequency disturbances, namely, dc-offset and 1/f noise (especially in CMOS implementations), in-phase (I) and quadrature (Q) amplitude and phase mismatch, local oscillator (LO) leakage, and even-order distortions. A cost-effective method to minimize the low-frequency disturbances is to use ac-coupling in the baseband signal path. However, it results in baseline wander effects, especially in spectrally efficient modulation schemes such as quadrature amplitude modulation (QAM) where the baseband signal spectrum contains a significant amount of energy near dc. A system solution to mitigate the effects of low-frequency disturbance is presented in this paper. The quantized feedback (QFB) technique is used in conjunction with ac-coupling to minimize the baseline wander effects. A cross-coupled (CC) QFB extension to compensate for the receiver local oscillator phase error as well as the IQ mismatch is also described. Simulation results are presented to demonstrate the effectiveness of this complex QFB technique

Low-cost, high-efficiency, and high-speed SiGe phototransistors in commercial BiCMOS

We present a new approach to obtain low-cost and high-performance SiGe phototransistors in a commercial BiCMOS process. Photoresponsivity of 2.7 A/W was obtained for 850-nm detection due to the transistor gain, corresponding to 393% quantum efficiency. Responsivities of 0.13 A/W and 0.07mA/W were achieved for 1060 and 1310 nm with SiGe absorption. With V/sub ce/=2 V, we measure a -3-dB bandwidth of up to 5.3 GHz for phototransistors with a 4-μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area and 2.0 GHz for phototransistors with 60-μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area and finger contacts. This high-efficiency and high-speed phototransistor is an enabling device for monolithic receiver integration.

Multiband monolithic BiCMOS low-power low-IF WLAN receivers

This letter presents the design, implementation, and measurements of two monolithic low-IF receivers compliant with the main WLAN standards. The first receiver targets the three 5GHz U-NII bands, while the second allows dual-band operation in the 2GHz and 5GHz bands. Fabricated in a 47GHz-f/sub t/ BiCMOS technology, both consist of a low-noise preamplifier, two matched active singly-balanced mixers and two polyphase filters, used to generate quadrature LO signals and provide image-rejection. The single-band receiver exhibits 25 dB of conversion gain, 8.9 dB of NF and -19 dBm of P/sub 1 dB/, while consuming 19 mW. The dual-band receiver shows similar performances in the 5GHz band, and extends its operation in the 2GHz band, achieving 33.4dB of conversion gain, 4.1dB of NF and -26dBm of P/sub 1 dB/, while consuming 14.9mW.

A 12-GHz silicon bipolar dual-conversion receiver for digital satellite applications

A 12-GHz monolithic silicon bipolar receiver for digital video broadcasting via satellite (DVB-S) is presented. The receiver is based on a dual-conversion superheterodyne architecture that employs a single LO integrated in the same die. To comply with the stringent LO phase noise requirement of -101 dBc/Hz at 100 kHz offset from the carrier, an innovative VCO topology, based on a three-layer monolithic transformer, was used. The VCO exhibits a phase noise of -102 dBc/Hz at 100 kHz offset from a 5.3-GHz carrier and a 1.1-GHz tuning range. At 12 GHz, the conversion gain is 33.6 dB, the single-sideband noise figure is 5.9 dB and the output IP3 is +16 dBm. This work reports the first 12-GHz DVB-S monolithic receiver integrated in a low-cost silicon bipolar technology.

A monolithic 12-GHz heterodyne receiver for DVB-S applications in silicon bipolar technology

A monolithic heterodyne receiver for digital video broadcasting via-satellite (DVB-S) applications is presented. The integrated circuit consists of a down-converter block and a phase-locked-loop-based local-oscillator synthesizer to translate the DVB-S RF-band (10.7-12.75 GHz) to an IF ranging in the L-band (0.95-2.15 GHz). The receiver exhibits a conversion gain of 38 dB, a single-sideband noise figure of 7 dB, and an output 1-dB compression point of +5 dBm. A 2.2-GHz-wide voltage-controlled oscillator (VCO) tuning range, extending from 8.6 to 10.8 GHz, is achieved adopting a transformer-based topology. The VCO phase noise is as low as -95 dBc/Hz at 100-kHz offset from a 10.6-GHz carrier. The integrated receiver draws 160 mA from a 3.3-V supply voltage. This paper demonstrates the feasibility of a Ku-band DVB-S heterodyne receiver integrated in low-cost 46-GHz-f/sub T/ silicon bipolar technology.

Monolithic InGaP-GaAs HBT receiver front-end with 6 mW DC power consumption for 5 GHz band WLAN applications

A very low power consumption (6 mW) 5 GHz band receiver front-end using InGaP-GaAs HBT technology is reported. The receiver front-end is composed of a cascode low noise amplifier followed by a double-balanced mixer with the RF transconductor stage placed above the Gilbert quad for direct-coupled connection. The RF band of this receiver front-end is set to be 5.2 GHz, being downconverted to 1 GHz IF frequency. Input-return-loss (S11) in RF port smaller than −12 dB and excellent power-conversion-gain of 35.4 dB are achieved. Input 1 dB compression point (P1dB) and input third-order intercept point (IIP3) of −24 and −3 dBm, respectively, are also achieved.

A Ku-band monolithic receiver for DVB-S applications

Despite the incessant progress observed in fixed and wireless terrestrial communication networks, satellite systems remain an appealing solution for broadcasting, point-to-point, and multicasting telecommunications, because of undemanding customer equipment and wide coverage capability. In this scenario, digital video broadcasting via satellite (DVB-S) is recognized as one of the main market-attractive telecommunication fields. Up to now, expensive discrete GaAs HEMT or FET devices have been used to build up circuitry for satellite applications at Ku-band. This article presents the first 12-GHz monolithic receiver for DVB-S applications, implemented in a low-cost silicon bipolar technology. The receiver is based on a superheterodyne architecture, employing a fully integrated LO. To comply with the severe LO phase noise requirement of -101 dBc/Hz at a 100 kHz offset from the carrier, an innovative VCO topology was used implementing a three-metal-layer integrated transformer. The performance parameters of the integrated receiver fulfill DVB-S standard specifications.

Low-cost circuit solutions for micro- and millimeter-wave systems using commercially available SiGe technologies

Increased use of wireless technologies for communications and sensing results in spectral overcrowding in the lower GHz range. Spectrum allocations in the upper microwave and in the millimeter-wave ranges are available, yet realizing low-cost circuits, e.g. for the 24 GHz ISM band remains a challenge. We are investigating the use of two Si/SiGe hetero-junction bipolar transistor technologies at Atmel Germany (the commercially available SiGe1 and the emerging SiGe2 processes), combined with compact circuit design and back-end micromachining techniques, for the realization of cost-efficient RF frontend solutions at frequencies above 20 GHz. Results presented here include a fully monolithic receiver IC for 24 GHz, and a 33 GHz oscillator module combined with a thin-film antenna structure using wafer-level integration.